From d02758f56be00005b5f97db6c1502ab1408d30f5 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Mon, 8 Jul 2024 18:24:16 +0800 Subject: [PATCH 1/2] feat(spi_flash): Increase flash frequency from 40M to 80M --- components/esptool_py/Kconfig.projbuild | 3 ++- .../hal/esp32c5/include/hal/spimem_flash_ll.h | 23 +++++++++++++++++-- components/soc/esp32c5/include/soc/soc_caps.h | 1 - 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/components/esptool_py/Kconfig.projbuild b/components/esptool_py/Kconfig.projbuild index 49661e1b79..ec7e12ee2a 100644 --- a/components/esptool_py/Kconfig.projbuild +++ b/components/esptool_py/Kconfig.projbuild @@ -93,7 +93,7 @@ menu "Serial flasher config" prompt "Flash SPI speed" # TODO: [ESP32C5] IDF-8649 switch back to 80M # TODO: [ESP32C61] IDF-9256 - default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61 + default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C61 default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT default ESPTOOLPY_FLASHFREQ_60M if IDF_TARGET_ESP32C2 config ESPTOOLPY_FLASHFREQ_120M @@ -153,6 +153,7 @@ menu "Serial flasher config" config ESPTOOLPY_FLASHFREQ_80M_DEFAULT bool default y if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6 + default y if IDF_TARGET_ESP32C5 help This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed. diff --git a/components/hal/esp32c5/include/hal/spimem_flash_ll.h b/components/hal/esp32c5/include/hal/spimem_flash_ll.h index 3542b319e3..8ecb69909d 100644 --- a/components/hal/esp32c5/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c5/include/hal/spimem_flash_ll.h @@ -29,6 +29,8 @@ #include "hal/spi_flash_types.h" #include "soc/pcr_struct.h" #include "esp_rom_sys.h" +#include "hal/clk_tree_ll.h" +#include "soc/clk_tree_defs.h" #ifdef __cplusplus extern "C" { @@ -626,8 +628,25 @@ static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_ */ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) { - // TODO: [ESP32C5] IDF-8649 - return 80; + int source_clk_mhz = 0; + + switch (PCR.mspi_clk_conf.mspi_func_clk_sel) + { + case 0: + source_clk_mhz = clk_ll_xtal_get_freq_mhz(); + break; + case 1: + source_clk_mhz = (SOC_CLK_RC_FAST_FREQ_APPROX/(1 * 1000 * 1000)); + break; + case 2: + source_clk_mhz = clk_ll_bbpll_get_freq_mhz(); + break; + default: + break; + } + + uint8_t clock_val = source_clk_mhz / (PCR.mspi_clk_conf.mspi_fast_div_num + 1); + return clock_val; } /** diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index a4cd2d4b73..00e8fb6eec 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -424,7 +424,6 @@ // #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) // #define SOC_SPI_MEM_SUPPORT_WRAP (1) -// TODO: [ESP32C5] IDF-8649 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 From eaccf8aedbca9039c1c513ef4566d2b0deffd14b Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Thu, 11 Jul 2024 13:59:42 +0800 Subject: [PATCH 2/2] fix(spi_flash): Fix the mpll clock source always pinned to 80M on PP4 --- .../hal/esp32p4/include/hal/spimem_flash_ll.h | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/components/hal/esp32p4/include/hal/spimem_flash_ll.h b/components/hal/esp32p4/include/hal/spimem_flash_ll.h index 2fc156aaa2..178853f3f9 100644 --- a/components/hal/esp32p4/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32p4/include/hal/spimem_flash_ll.h @@ -29,6 +29,7 @@ #include "hal/misc.h" #include "hal/efuse_hal.h" #include "soc/chip_revision.h" +#include "hal/clk_tree_ll.h" #ifdef __cplusplus extern "C" { @@ -645,7 +646,26 @@ static inline void spimem_flash_ll_set_extra_dummy(spi_mem_dev_t *dev, uint32_t */ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) { - return 80; + // return 80; + int source_clk_mhz = 0; + + switch (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel) + { + case 0: + source_clk_mhz = clk_ll_xtal_load_freq_mhz(); + break; + case 1: + source_clk_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // SPLL + break; + case 2: + source_clk_mhz = CLK_LL_PLL_400M_FREQ_MHZ; // CPLL + break; + default: + break; + } + + uint8_t clock_val = source_clk_mhz / (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_div_num + 1); + return clock_val; } /**