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fix(spi_flash): Fix the mpll clock source always pinned to 80M on PP4
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@ -29,6 +29,7 @@
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#include "hal/misc.h"
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#include "hal/efuse_hal.h"
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#include "soc/chip_revision.h"
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#include "hal/clk_tree_ll.h"
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#ifdef __cplusplus
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extern "C" {
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@ -645,7 +646,26 @@ static inline void spimem_flash_ll_set_extra_dummy(spi_mem_dev_t *dev, uint32_t
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*/
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static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
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{
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return 80;
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// return 80;
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int source_clk_mhz = 0;
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switch (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel)
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{
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case 0:
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source_clk_mhz = clk_ll_xtal_load_freq_mhz();
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break;
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case 1:
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source_clk_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // SPLL
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break;
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case 2:
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source_clk_mhz = CLK_LL_PLL_400M_FREQ_MHZ; // CPLL
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break;
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default:
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break;
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}
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uint8_t clock_val = source_clk_mhz / (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_div_num + 1);
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return clock_val;
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}
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/**
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