alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Merge branch 'feat/heap-support-esp32c61' into 'master'

Browse Source 
feat(heap): Add support for esp32c61

Closes IDF-9858 and IDF-10989

See merge request espressif/esp-idf!33556
This commit is contained in:
Guillaume Souchere 2024-09-20 16:01:20 +08:00
commit 19d512ebee
5 changed files with 52 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
components/heap/port/esp32c61/memory_layout.c
View File

@ -12,6 +12,11 @@
#include "heap_memory_layout.h" #include "heap_memory_layout.h"
#include "esp_heap_caps.h" #include "esp_heap_caps.h"
/* Memory layout for ESP32C61 SoC
* Note that the external memory is not represented in this file since
* it is handled by the esp_psram component
*/
/** /**
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC. * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
* Each type of memory map consists of one or more regions in the address space. * Each type of memory map consists of one or more regions in the address space.
@ -27,16 +32,14 @@
/* Index of memory in `soc_memory_types[]` */ /* Index of memory in `soc_memory_types[]` */
enum { enum {
SOC_MEMORY_TYPE_RAM = 0, SOC_MEMORY_TYPE_RAM,
SOC_MEMORY_TYPE_RTCRAM = 1,
SOC_MEMORY_TYPE_NUM,
}; };
/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */ /* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT) #define ESP32C61_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
#else #else
#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC) #define ESP32C61_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
#endif #endif
/** /**
@ -45,10 +48,9 @@ enum {
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching * if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
* in turn to continue matching. * in turn to continue matching.
*/ */
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { const soc_memory_type_desc_t soc_memory_types[] = {
/* Mem Type Name High Priority Matching Medium Priority Matching Low Priority Matching */ /* Mem Type Name High Priority Matching Medium Priority Matching Low Priority Matching */
[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C6_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }}, [SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C61_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32C6_MEM_COMMON_CAPS, 0 }},
}; };
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
@ -64,19 +66,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
/** /**
* Register the shared buffer area of the last memory block into the heap during heap initialization * Register the shared buffer area of the last memory block into the heap during heap initialization
*/ */
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) #define APP_USABLE_DIRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
const soc_memory_region_t soc_memory_regions[] = { const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory { SOC_DIRAM_DRAM_LOW, (APP_USABLE_DIRAM_END - SOC_DIRAM_DRAM_LOW), SOC_MEMORY_TYPE_RAM, SOC_DIRAM_IRAM_LOW, false}, //D/IRAM, can be used as trace memory
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory { APP_USABLE_DIRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DIRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DIRAM_END, true}, //D/IRAM, can be used as trace memory (ROM reserved area)
{ 0x40840000, (APP_USABLE_DRAM_END-0x40840000), SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level2, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
}; };
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; extern int _data_start, _heap_start, _iram_start, _iram_end;
/** /**
* Reserved memory regions. * Reserved memory regions.

3
components/heap/test_apps/.build-test-rules.yml
View File

@ -3,9 +3,6 @@
components/heap/test_apps/heap_tests: components/heap/test_apps/heap_tests:
disable: disable:
- if: IDF_TARGET == "linux" - if: IDF_TARGET == "linux"
- if: IDF_TARGET in ["esp32c61"]
temporary: true
reason: not support yet # TODO: [esp32c61] IDF-9858
- if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
- if: CONFIG_NAME == "psram_all_ext" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "psram_all_ext" and SOC_SPIRAM_SUPPORTED != 1
# These 3 configs are build only for non-nightly, buildig for a single target is sufficient # These 3 configs are build only for non-nightly, buildig for a single target is sufficient

4
components/heap/test_apps/heap_tests/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

27
components/heap/test_apps/heap_tests/pytest_heap.py
View File

@ -6,7 +6,6 @@ from pytest_embedded import Dut
@pytest.mark.generic @pytest.mark.generic
@pytest.mark.supported_targets @pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='support TBD') # TODO [ESP32C61] IDF-9858 IDF-10989
@pytest.mark.nightly_run @pytest.mark.nightly_run
@pytest.mark.parametrize( @pytest.mark.parametrize(
'config', 'config',
@ -40,7 +39,6 @@ def test_heap_poisoning_qemu(dut: Dut) -> None:
@pytest.mark.generic @pytest.mark.generic
@pytest.mark.supported_targets @pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='support TBD') # TODO [ESP32C61] IDF-9858 IDF-10989
@pytest.mark.parametrize( @pytest.mark.parametrize(
'config', 'config',
[ [
@ -52,9 +50,14 @@ def test_heap_in_flash(dut: Dut) -> None:
@pytest.mark.generic @pytest.mark.generic
@pytest.mark.esp32 @pytest.mark.parametrize(
@pytest.mark.esp32s2 'target',
@pytest.mark.esp32s3 [
'esp32',
'esp32s2',
'esp32s3',
]
)
@pytest.mark.parametrize( @pytest.mark.parametrize(
'config', 'config',
[ [
@ -67,7 +70,12 @@ def test_heap(dut: Dut) -> None:
@pytest.mark.generic @pytest.mark.generic
@pytest.mark.esp32 @pytest.mark.parametrize(
'target',
[
'esp32',
]
)
@pytest.mark.parametrize( @pytest.mark.parametrize(
'config', 'config',
[ [
@ -86,7 +94,12 @@ def test_heap_misc_options(dut: Dut) -> None:
@pytest.mark.generic @pytest.mark.generic
@pytest.mark.esp32 @pytest.mark.parametrize(
'target',
[
'esp32',
]
)
@pytest.mark.parametrize( @pytest.mark.parametrize(
'config', 'config',
[ [

31
components/soc/esp32c61/include/soc/soc.h
View File

@ -146,20 +146,21 @@
* should be defined statically! * should be defined statically!
*/ */
#define SOC_IROM_LOW 0x42000000 #define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH 0x44000000 #define SOC_IROM_HIGH 0x44000000
#define SOC_EXTRAM_DATA_LOW 0x42000000 #define SOC_EXTRAM_DATA_LOW 0x42000000
#define SOC_EXTRAM_DATA_HIGH 0x44000000 #define SOC_EXTRAM_DATA_HIGH 0x44000000
#define SOC_DROM_LOW SOC_IROM_LOW #define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
#define SOC_DROM_HIGH SOC_IROM_HIGH #define SOC_DROM_LOW SOC_IROM_LOW
#define SOC_IROM_MASK_LOW 0x40000000 #define SOC_DROM_HIGH SOC_IROM_HIGH
#define SOC_IROM_MASK_HIGH 0x40040000 #define SOC_IROM_MASK_LOW 0x40000000
#define SOC_DROM_MASK_LOW 0x40000000 #define SOC_IROM_MASK_HIGH 0x40040000
#define SOC_DROM_MASK_HIGH 0x40040000 #define SOC_DROM_MASK_LOW 0x40000000
#define SOC_IRAM_LOW 0x40800000 #define SOC_DROM_MASK_HIGH 0x40040000
#define SOC_IRAM_HIGH 0x40850000 #define SOC_IRAM_LOW 0x40800000
#define SOC_DRAM_LOW 0x40800000 #define SOC_IRAM_HIGH 0x40850000
#define SOC_DRAM_HIGH 0x40850000 #define SOC_DRAM_LOW 0x40800000
#define SOC_DRAM_HIGH 0x40850000
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x40800000 #define SOC_DIRAM_IRAM_LOW 0x40800000
@ -196,7 +197,7 @@
#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot // Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4084c9f0 #define SOC_ROM_STACK_START 0x4084ea70
#define SOC_ROM_STACK_SIZE 0x2000 #define SOC_ROM_STACK_SIZE 0x2000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.