esp-idf/components/idf_test/include/idf_performance.h

#pragma once

/* declare the performance here */
#define IDF_PERFORMANCE_MAX_HTTPS_REQUEST_BIN_SIZE                              800
#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP                     200
#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM               300
#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE             130
#define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL                         1000
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                            30
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA                     27
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                               15
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA                        15
/* Due to code size & linker layout differences interacting with cache, VFS
   microbenchmark currently runs slower with PSRAM enabled. */
#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME                           20000
#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM                     25000
// throughput performance by iperf
#define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT                                   50
#define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT                                   40
#define IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT                                   80
#define IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT                                   50
// events dispatched per second by event loop library
#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH                                      25000
#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM                                21000
// esp_sha() time to process 32KB of input data from RAM
#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA1_32KB                                5000
#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA512_32KB                              4500
// AES-CBC hardware throughput (accounts for worst-case performance with PSRAM workaround)
#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC                            8.5
unity: separate common and IDF specific functionality New unity component can be used for testing other applications. Upstream version of Unity is included as a submodule. Utilities specific to ESP-IDF unit tests (partitions, leak checking setup/teardown functions, etc) are kept only in unit-test-app. Kconfig options are added to allow disabling certain Unity features. 2018-10-25 00:52:32 -04:00			`#pragma once`
test: check and collect performance via CI 2017-11-07 23:27:57 -05:00
			`/* declare the performance here */`
test: enlarge https bin size threshold: use performance matrix to tracking bin size is not convenient. bin size do change for a lot reasons. we'll implement a new method to track it. before that, set a large enough threshold, so we can still keep tracking it. 2018-01-31 20:57:00 -05:00			`#define IDF_PERFORMANCE_MAX_HTTPS_REQUEST_BIN_SIZE 800`
test: check and collect performance via CI 2017-11-07 23:27:57 -05:00			`#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP 200`
freertos: bump limit for spinlock performance test to 300 cycles 2018-06-27 02:47:31 -04:00			`#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM 300`
test: check and collect performance via CI 2017-11-07 23:27:57 -05:00			`#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE 130`
			`#define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL 1000`
test(spi_master): add performance display for spi master. 2018-02-07 02:45:10 -05:00			`#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 30`
test(spi_master): test spi master speed performance by median value. also increase the boundary of SPI limit by a little. 2018-01-30 22:15:23 -05:00			`#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 27`
spi_master: add new polling mode to decrease time cost each transaction 2018-01-30 22:15:23 -05:00			`#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15`
			`#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15`
tests: Increase performance threshold for VFS running with PSRAM Cache effects on microbenchmarks in cached flash can be significant, depending on linker layout in flash. 2018-05-17 07:12:45 -04:00			`/* Due to code size & linker layout differences interacting with cache, VFS`
			`microbenchmark currently runs slower with PSRAM enabled. */`
Fix VFS_OPEN_WRITE_CLOSE_TIME unit test issue Closes idf/esp-idf#44 2018-11-23 02:07:59 -05:00			`#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME 20000`
			`#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM 25000`
example test: add test case for iperf example 2018-01-07 07:28:09 -05:00			`// throughput performance by iperf`
			`#define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT 50`
			`#define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT 40`
			`#define IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT 80`
			`#define IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT 50`
event: Implement event loop library 2018-10-26 01:14:19 -04:00			`// events dispatched per second by event loop library`
esp_event: lower test performance threshold for PSRAM config 2018-10-31 23:01:35 -04:00			`#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH 25000`
			`#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM 21000`
esp32: Chunk input blocks for esp_sha() function performance, add perf test 2019-03-11 03:24:32 -04:00			`// esp_sha() time to process 32KB of input data from RAM`
mbedtls: Add AES-CBC performance test Hardware AES engine gets 11.0MB/sec on Release config Software AES is around 2.3MB/sec on Release config 2019-05-19 19:44:42 -04:00			`#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA1_32KB 5000`
			`#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA512_32KB 4500`
			`// AES-CBC hardware throughput (accounts for worst-case performance with PSRAM workaround)`
			`#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 8.5`