uint32_tin_done:1;/*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
uint32_tin_suc_eof:1;/*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
uint32_tin_err_eof:1;/*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/
uint32_tout_done:1;/*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
uint32_tout_eof:1;/*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */
uint32_tin_dscr_err:1;/*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
uint32_tout_dscr_err:1;/*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/
uint32_tin_dscr_empty:1;/*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/
uint32_tout_total_eof:1;/*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
uint32_tinfifo_ovf:1;/*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */
uint32_tinfifo_udf:1;/*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */
uint32_toutfifo_ovf:1;/*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */
uint32_toutfifo_udf:1;/*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */
uint32_treserved13:19;/*reserved*/
};
uint32_tval;
}raw;
union{
struct{
uint32_tin_done:1;/*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
uint32_tin_suc_eof:1;/*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_tin_err_eof:1;/*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_tout_done:1;/*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
uint32_tout_eof:1;/*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
uint32_tin_dscr_err:1;/*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_tout_dscr_err:1;/*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_tin_dscr_empty:1;/*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_tout_total_eof:1;/*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_tinfifo_ovf:1;/*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_tinfifo_udf:1;/*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_toutfifo_ovf:1;/*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_toutfifo_udf:1;/*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_treserved13:19;/*reserved*/
};
uint32_tval;
}st;
union{
struct{
uint32_tin_done:1;/*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
uint32_tin_suc_eof:1;/*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_tin_err_eof:1;/*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_tout_done:1;/*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
uint32_tout_eof:1;/*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_tin_dscr_err:1;/*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_tout_dscr_err:1;/*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_tin_dscr_empty:1;/*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_tout_total_eof:1;/*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_tinfifo_ovf:1;/*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_tinfifo_udf:1;/*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_toutfifo_ovf:1;/*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_toutfifo_udf:1;/*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_treserved13:19;/*reserved*/
};
uint32_tval;
}ena;
union{
struct{
uint32_tin_done:1;/*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
uint32_tin_suc_eof:1;/*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
uint32_tin_err_eof:1;/*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
uint32_tout_done:1;/*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
uint32_tout_eof:1;/*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
uint32_tin_dscr_err:1;/*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_tout_dscr_err:1;/*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_tin_dscr_empty:1;/*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_tout_total_eof:1;/*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_tinfifo_ovf:1;/*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_tinfifo_udf:1;/*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_toutfifo_ovf:1;/*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_toutfifo_udf:1;/*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_treserved13:19;/*reserved*/
};
uint32_tval;
}clr;
}intr[1];
uint32_treserved_10;
uint32_treserved_14;
uint32_treserved_18;
uint32_treserved_1c;
uint32_treserved_20;
uint32_treserved_24;
uint32_treserved_28;
uint32_treserved_2c;
uint32_treserved_30;
uint32_treserved_34;
uint32_treserved_38;
uint32_treserved_3c;
union{
struct{
uint32_tahb_testmode:3;/*reserved*/
uint32_treserved3:1;/*reserved*/
uint32_tahb_testaddr:2;/*reserved*/
uint32_treserved6:26;/*reserved*/
};
uint32_tval;
}ahb_test;
union{
struct{
uint32_tahbm_rst_inter:1;/*Set this bit, then clear this bit to reset the internal ahb FSM.*/
uint32_treserved1:1;
uint32_tarb_pri_dis:1;/*Set this bit to disable priority arbitration function.*/
uint32_tclk_en:1;/*reg_clk_en*/
uint32_treserved4:28;
};
uint32_tval;
}misc_conf;
uint32_tdate;
uint32_treserved_4c;
uint32_treserved_50;
uint32_treserved_54;
uint32_treserved_58;
uint32_treserved_5c;
uint32_treserved_60;
uint32_treserved_64;
uint32_treserved_68;
uint32_treserved_6c;
struct{
struct{
union{
struct{
uint32_tin_rst:1;/*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
uint32_tin_loop_test:1;/*reserved*/
uint32_tindscr_burst_en:1;/*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_tin_data_burst_en:1;/*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */
uint32_tmem_trans_en:1;/*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
uint32_treserved5:27;/*reserved*/
};
uint32_tval;
}in_conf0;
union{
struct{
uint32_treserved0:12;
uint32_tin_check_owner:1;/*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_treserved13:19;/*reserved*/
};
uint32_tval;
}in_conf1;
union{
struct{
uint32_tinfifo_full:1;/*L1 Rx FIFO full signal for Rx channel 0.*/
uint32_tinfifo_empty:1;/*L1 Rx FIFO empty signal for Rx channel 0.*/
uint32_tinfifo_cnt:6;/*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
uint32_treserved8:15;/*reserved*/
uint32_tin_remain_under_1b:1;/*reserved*/
uint32_tin_remain_under_2b:1;/*reserved*/
uint32_tin_remain_under_3b:1;/*reserved*/
uint32_tin_remain_under_4b:1;/*reserved*/
uint32_tin_buf_hungry:1;/*reserved*/
uint32_treserved28:4;/*reserved*/
};
uint32_tval;
}infifo_status;
union{
struct{
uint32_tinfifo_rdata:12;/*This register stores the data popping from DMA FIFO.*/
uint32_tinfifo_pop:1;/*Set this bit to pop data from DMA FIFO.*/
uint32_treserved13:19;/*reserved*/
};
uint32_tval;
}in_pop;
union{
struct{
uint32_taddr:20;/*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
uint32_tauto_ret:1;/*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/
uint32_tstop:1;/*Set this bit to stop dealing with the inlink descriptors.*/
uint32_tstart:1;/*Set this bit to start dealing with the inlink descriptors.*/
uint32_trestart:1;/*Set this bit to mount a new inlink descriptor.*/
uint32_tpark:1;/*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_treserved25:7;
};
uint32_tval;
}in_link;
union{
struct{
uint32_tdscr_addr:18;/*This register stores the current inlink descriptor's address.*/
uint32_tin_dscr_state:2;/*reserved*/
uint32_tin_state:3;/*reserved*/
uint32_treserved23:9;/*reserved*/
};
uint32_tval;
}in_state;
uint32_tin_suc_eof_des_addr;
uint32_tin_err_eof_des_addr;
uint32_tin_dscr;
uint32_tin_dscr_bf0;
uint32_tin_dscr_bf1;
union{
struct{
uint32_trx_pri:4;/*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/
uint32_treserved4:28;
};
uint32_tval;
}in_pri;
union{
struct{
uint32_tsel:6;/*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
uint32_treserved6:26;
};
uint32_tval;
}in_peri_sel;
uint32_treserved_a4;
uint32_treserved_a8;
uint32_treserved_ac;
uint32_treserved_b0;
uint32_treserved_b4;
uint32_treserved_b8;
uint32_treserved_bc;
uint32_treserved_c0;
uint32_treserved_c4;
uint32_treserved_c8;
uint32_treserved_cc;
}in;
struct{
union{
struct{
uint32_tout_rst:1;/*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
uint32_tout_loop_test:1;/*reserved*/
uint32_tout_auto_wrback:1;/*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_tout_eof_mode:1;/*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
uint32_toutdscr_burst_en:1;/*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_tout_data_burst_en:1;/*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */
uint32_treserved6:26;
};
uint32_tval;
}out_conf0;
union{
struct{
uint32_treserved0:12;
uint32_tout_check_owner:1;/*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_treserved13:19;/*reserved*/
};
uint32_tval;
}out_conf1;
union{
struct{
uint32_toutfifo_full:1;/*L1 Tx FIFO full signal for Tx channel 0.*/
uint32_toutfifo_empty:1;/*L1 Tx FIFO empty signal for Tx channel 0.*/
uint32_toutfifo_cnt:6;/*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
uint32_treserved8:15;/*reserved*/
uint32_tout_remain_under_1b:1;/*reserved*/
uint32_tout_remain_under_2b:1;/*reserved*/
uint32_tout_remain_under_3b:1;/*reserved*/
uint32_tout_remain_under_4b:1;/*reserved*/
uint32_treserved27:5;/*reserved*/
};
uint32_tval;
}outfifo_status;
union{
struct{
uint32_toutfifo_wdata:9;/*This register stores the data that need to be pushed into DMA FIFO.*/
uint32_toutfifo_push:1;/*Set this bit to push data into DMA FIFO.*/
uint32_treserved10:22;/*reserved*/
};
uint32_tval;
}out_push;
union{
struct{
uint32_taddr:20;/*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
uint32_tstop:1;/*Set this bit to stop dealing with the outlink descriptors.*/
uint32_tstart:1;/*Set this bit to start dealing with the outlink descriptors.*/
uint32_trestart:1;/*Set this bit to restart a new outlink from the last address. */
uint32_tpark:1;/*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/
uint32_treserved24:8;
};
uint32_tval;
}out_link;
union{
struct{
uint32_tdscr_addr:18;/*This register stores the current outlink descriptor's address.*/
uint32_tout_dscr_state:2;/*reserved*/
uint32_tout_state:3;/*reserved*/
uint32_treserved23:9;/*reserved*/
};
uint32_tval;
}out_state;
uint32_tout_eof_des_addr;
uint32_tout_eof_bfr_des_addr;
uint32_tout_dscr;
uint32_tout_dscr_bf0;
uint32_tout_dscr_bf1;
union{
struct{
uint32_ttx_pri:4;/*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/
uint32_treserved4:28;
};
uint32_tval;
}out_pri;
union{
struct{
uint32_tsel:6;/*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
