esp-idf/components/soc/esp32s3/ld/esp32s3.peripherals.ld

/*
 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
PROVIDE ( UART0 = 0x60000000 );
PROVIDE ( SPIMEM1 = 0x60002000 );
PROVIDE ( SPIMEM0 = 0x60003000 );
PROVIDE ( GPIO = 0x60004000 );
PROVIDE ( SDM = 0x60004f00 );
PROVIDE ( EFUSE = 0x60007000 );
PROVIDE ( RTCCNTL = 0x60008000 );
PROVIDE ( RTCIO = 0x60008400 );
PROVIDE ( SENS = 0x60008800 );
PROVIDE ( HINF = 0x6000B000 );
PROVIDE ( I2S0 = 0x6000F000 );
PROVIDE ( I2S1 = 0x6002D000 );
PROVIDE ( UART1 = 0x60010000 );
PROVIDE ( I2C0 = 0x60013000 );
PROVIDE ( UHCI0 = 0x60014000 );
PROVIDE ( UHCI1 = 0x60014000 );
PROVIDE ( HOST = 0x60015000 );
PROVIDE ( RMT = 0x60016000 );
PROVIDE ( RMTMEM = 0x60016800 );
PROVIDE ( PCNT = 0x60017000 );
PROVIDE ( SLC = 0x60018000 );
PROVIDE ( LEDC = 0x60019000 );
PROVIDE ( MCPWM0 = 0x6001E000 );
PROVIDE ( MCPWM1 = 0x6002C000 );
PROVIDE ( MCP = 0x600c3000 );
PROVIDE ( TIMERG0 = 0x6001F000 );
PROVIDE ( TIMERG1 = 0x60020000 );
PROVIDE ( SYSTIMER = 0x60023000 );
PROVIDE ( GPSPI2  = 0x60024000 );
PROVIDE ( GPSPI3  = 0x60025000 );
PROVIDE ( SYSCON = 0x60026000 );
PROVIDE ( I2C1 = 0x60027000 );
PROVIDE ( SDMMC = 0x60028000 );
PROVIDE ( TWAI = 0x6002B000 );
PROVIDE ( GPSPI4 = 0x60037000 );
PROVIDE ( GDMA = 0x6003F000 );
PROVIDE ( UART2  = 0x6002E000 );
PROVIDE ( DMA = 0x6003F000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( LCD_CAM    = 0x60041000 );
PROVIDE ( USB_SERIAL_JTAG  = 0x60038000 );
PROVIDE ( USB0     = 0x60080000 );
PROVIDE ( USBH     = 0x60080000 );
PROVIDE ( USB_WRAP = 0x60039000 );
esp32s2, esp32s3: update copyright notice 2021-06-02 10:34:38 -04:00			`/*`
soc: Adds efuse hal Replaced eFuse ROM funcs with hal layer 2021-12-22 09:18:43 -05:00			`* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD`
esp32s2, esp32s3: update copyright notice 2021-06-02 10:34:38 -04:00			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`
esp32s3: clk, memory layout 2020-07-23 01:40:10 -04:00			`PROVIDE ( UART0 = 0x60000000 );`
			`PROVIDE ( SPIMEM1 = 0x60002000 );`
			`PROVIDE ( SPIMEM0 = 0x60003000 );`
			`PROVIDE ( GPIO = 0x60004000 );`
sdm: clean up soc/hal/ll code 2022-05-17 01:47:14 -04:00			`PROVIDE ( SDM = 0x60004f00 );`
soc: Adds efuse hal Replaced eFuse ROM funcs with hal layer 2021-12-22 09:18:43 -05:00			`PROVIDE ( EFUSE = 0x60007000 );`
esp32s3: clk, memory layout 2020-07-23 01:40:10 -04:00			`PROVIDE ( RTCCNTL = 0x60008000 );`
			`PROVIDE ( RTCIO = 0x60008400 );`
			`PROVIDE ( SENS = 0x60008800 );`
			`PROVIDE ( HINF = 0x6000B000 );`
			`PROVIDE ( I2S0 = 0x6000F000 );`
driver: support I2S on ESP32-S3 & ESP32-C3 1. refactor I2S driver. 2. support TDM mode for esp2s3 & esp32c3. 2020-05-31 21:47:48 -04:00			`PROVIDE ( I2S1 = 0x6002D000 );`
esp32s3: clk, memory layout 2020-07-23 01:40:10 -04:00			`PROVIDE ( UART1 = 0x60010000 );`
			`PROVIDE ( I2C0 = 0x60013000 );`
			`PROVIDE ( UHCI0 = 0x60014000 );`
			`PROVIDE ( UHCI1 = 0x60014000 );`
			`PROVIDE ( HOST = 0x60015000 );`
			`PROVIDE ( RMT = 0x60016000 );`
			`PROVIDE ( RMTMEM = 0x60016800 );`
			`PROVIDE ( PCNT = 0x60017000 );`
			`PROVIDE ( SLC = 0x60018000 );`
			`PROVIDE ( LEDC = 0x60019000 );`
mcpwm: fix wrong meta information 2021-01-07 04:31:18 -05:00			`PROVIDE ( MCPWM0 = 0x6001E000 );`
			`PROVIDE ( MCPWM1 = 0x6002C000 );`
esp32s3: clk, memory layout 2020-07-23 01:40:10 -04:00			`PROVIDE ( MCP = 0x600c3000 );`
			`PROVIDE ( TIMERG0 = 0x6001F000 );`
			`PROVIDE ( TIMERG1 = 0x60020000 );`
systimer: update soc data 2021-04-02 00:41:08 -04:00			`PROVIDE ( SYSTIMER = 0x60023000 );`
esp32s3: clk, memory layout 2020-07-23 01:40:10 -04:00			`PROVIDE ( GPSPI2 = 0x60024000 );`
			`PROVIDE ( GPSPI3 = 0x60025000 );`
			`PROVIDE ( SYSCON = 0x60026000 );`
			`PROVIDE ( I2C1 = 0x60027000 );`
soc: add esp32s3 sdmmc support * sync the latest struct header file from ESP32 * add soc_caps.h macros to distinguish between IO MUX and GPIO Matrix support in SDMMC on different chips. * store GPIO matrix signal numbers in sdmmc_slot_info_t 2021-01-04 14:34:31 -05:00			`PROVIDE ( SDMMC = 0x60028000 );`
TWAI: bringup for S3 and C3 2021-01-13 21:44:59 -05:00			`PROVIDE ( TWAI = 0x6002B000 );`
esp32s3: clk, memory layout 2020-07-23 01:40:10 -04:00			`PROVIDE ( GPSPI4 = 0x60037000 );`
async memcpy: support async memcopy on esp32s2/s3 Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA 2020-09-08 08:17:18 -04:00			`PROVIDE ( GDMA = 0x6003F000 );`
Support ESP32S3 Beta 3 target Update ROM API. Port changes from bringup branch. 2021-03-17 06:48:05 -04:00			`PROVIDE ( UART2 = 0x6002E000 );`
crypto accelerator support on esp32s3 SHA: passing unit tests RSA: pass tests AES: tests passing 2020-08-19 02:39:12 -04:00			`PROVIDE ( DMA = 0x6003F000 );`
esp32s3: clk, memory layout 2020-07-23 01:40:10 -04:00			`PROVIDE ( APB_SARADC = 0x60040000 );`
			`PROVIDE ( LCD_CAM = 0x60041000 );`
usb_serial_jtag: add initial support for S3 (including flashing, monitoring, writing, and reading) but console is not avaliable now 2021-06-04 02:48:20 -04:00			`PROVIDE ( USB_SERIAL_JTAG = 0x60038000 );`
usb: update LL to support PHY selection ESP32-S3 has two USB peripheral, one is USB_OTG, another is USB_JTAG_SERIAL A new mux has been introduced to select internal/external PHY interface. 2021-07-08 23:09:28 -04:00			`PROVIDE ( USB0 = 0x60080000 );`
usb/hal/soc: initial copy of usbh support from esp32s2 copy required usbh driver files from esp32s2 check usb host functionality using unit tests on esp32s3 2021-06-02 05:57:50 -04:00			`PROVIDE ( USBH = 0x60080000 );`
soc/hal: add tinyusb support esp32s3 add usb hal/soc, usb_ll files and esp32s3 target for usb move usb_hal.h into soc common folder soc/hal: fix soc and periph for usb tinyusb: fix tinyusb io header hal: usb_ll fix pull up/down config for esp32s3 soc/hal: fix peripheral addresses 2021-05-06 04:20:54 -04:00			`PROVIDE ( USB_WRAP = 0x60039000 );`