2021-08-05 11:35:07 -04:00
|
|
|
/*
|
2022-01-25 01:23:53 -05:00
|
|
|
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
2021-08-05 11:35:07 -04:00
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
*/
|
2021-03-30 02:50:27 -04:00
|
|
|
|
2022-01-05 01:08:37 -05:00
|
|
|
|
2022-01-25 01:23:53 -05:00
|
|
|
#include "esp_attr.h"
|
2021-03-30 02:50:27 -04:00
|
|
|
#include <stdint.h>
|
2022-01-05 01:08:37 -05:00
|
|
|
#include "freertos/FreeRTOS.h"
|
|
|
|
#include "freertos/semphr.h"
|
2022-06-16 05:06:39 -04:00
|
|
|
#include "hal/regi2c_ctrl.h"
|
2021-03-30 02:50:27 -04:00
|
|
|
|
|
|
|
static portMUX_TYPE mux = portMUX_INITIALIZER_UNLOCKED;
|
|
|
|
|
|
|
|
uint8_t IRAM_ATTR regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
|
|
|
|
{
|
2022-03-03 03:55:08 -05:00
|
|
|
portENTER_CRITICAL_SAFE(&mux);
|
2022-01-05 01:08:37 -05:00
|
|
|
uint8_t value = regi2c_read_reg_raw(block, host_id, reg_add);
|
2022-03-03 03:55:08 -05:00
|
|
|
portEXIT_CRITICAL_SAFE(&mux);
|
2021-03-30 02:50:27 -04:00
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t IRAM_ATTR regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
|
|
|
|
{
|
2022-03-03 03:55:08 -05:00
|
|
|
portENTER_CRITICAL_SAFE(&mux);
|
2022-01-05 01:08:37 -05:00
|
|
|
uint8_t value = regi2c_read_reg_mask_raw(block, host_id, reg_add, msb, lsb);
|
2022-03-03 03:55:08 -05:00
|
|
|
portEXIT_CRITICAL_SAFE(&mux);
|
2021-03-30 02:50:27 -04:00
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
|
|
|
void IRAM_ATTR regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
|
|
|
|
{
|
2022-03-03 03:55:08 -05:00
|
|
|
portENTER_CRITICAL_SAFE(&mux);
|
2022-01-05 01:08:37 -05:00
|
|
|
regi2c_write_reg_raw(block, host_id, reg_add, data);
|
2022-03-03 03:55:08 -05:00
|
|
|
portEXIT_CRITICAL_SAFE(&mux);
|
2021-03-30 02:50:27 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
void IRAM_ATTR regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
|
|
|
|
{
|
2022-03-03 03:55:08 -05:00
|
|
|
portENTER_CRITICAL_SAFE(&mux);
|
2022-01-05 01:08:37 -05:00
|
|
|
regi2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data);
|
2022-03-03 03:55:08 -05:00
|
|
|
portEXIT_CRITICAL_SAFE(&mux);
|
2021-03-30 02:50:27 -04:00
|
|
|
}
|
2022-01-25 01:23:53 -05:00
|
|
|
|
2022-03-01 03:12:45 -05:00
|
|
|
void IRAM_ATTR regi2c_enter_critical(void)
|
|
|
|
{
|
|
|
|
portENTER_CRITICAL_SAFE(&mux);
|
|
|
|
}
|
|
|
|
|
|
|
|
void IRAM_ATTR regi2c_exit_critical(void)
|
|
|
|
{
|
|
|
|
portEXIT_CRITICAL_SAFE(&mux);
|
|
|
|
}
|
|
|
|
|
2022-01-25 01:23:53 -05:00
|
|
|
/**
|
|
|
|
* Restore regi2c analog calibration related configuration registers.
|
|
|
|
* This is a workaround, and is fixed on later chips
|
|
|
|
*/
|
|
|
|
#if REGI2C_ANA_CALI_PD_WORKAROUND
|
2022-06-16 05:06:39 -04:00
|
|
|
#include "soc/regi2c_saradc.h"
|
2022-01-25 01:23:53 -05:00
|
|
|
|
|
|
|
static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM];
|
|
|
|
|
|
|
|
void IRAM_ATTR regi2c_analog_cali_reg_read(void)
|
|
|
|
{
|
2022-03-06 22:45:02 -05:00
|
|
|
for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
|
2022-01-25 01:23:53 -05:00
|
|
|
reg_val[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void IRAM_ATTR regi2c_analog_cali_reg_write(void)
|
|
|
|
{
|
2022-03-06 22:45:02 -05:00
|
|
|
for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
|
2022-01-25 01:23:53 -05:00
|
|
|
regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif //#if ADC_CALI_PD_WORKAROUND
|