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esp-idf/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

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build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
adc: support adc dma driver on all chips
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config SOC_ADC_SUPPORTED
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
config SOC_GDMA_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
config SOC_BT_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_USB_SERIAL_JTAG_SUPPORTED
bool
default y
config SOC_TEMP_SENSOR_SUPPORTED
bool
default y
config SOC_XT_WDT_SUPPORTED
bool
default y
docs: update docs to be able to build with esp8684
2021-11-09 04:11:01 -05:00
config SOC_WIFI_SUPPORTED
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
efuse(esp32c2): Support eFuse key APIs
2021-12-02 12:48:47 -05:00
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
reset_reasons: EFUSE_RST is treated as POWERON_RST ESP32 does not have the EFUSE_RST, the rest chips has this reset reason.
2021-08-11 03:20:17 -04:00
config SOC_EFUSE_HAS_EFUSE_RST_BUG
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
docs: update system API-guides for ESP32-C2
2022-07-11 05:11:27 -04:00
config SOC_RTC_MEM_SUPPORTED
bool
default y
CI: Enable ESP8684 build stage CI on master
2021-11-26 04:03:47 -05:00
config SOC_I2S_SUPPORTED
bool
default y
config SOC_RMT_SUPPORTED
bool
default y
sdm: clean up soc/hal/ll code
2022-05-17 01:47:14 -04:00
config SOC_SDM_SUPPORTED
CI: Enable ESP8684 build stage CI on master
2021-11-26 04:03:47 -05:00
bool
default y
docs: translate coexist from CN to EN
2021-07-28 23:20:52 -04:00
config SOC_SUPPORT_COEXISTENCE
bool
default y
soc: add capability macros for crypto peripherals Closes IDF-4790
2022-03-17 05:32:14 -04:00
config SOC_AES_SUPPORTED
bool
default y
config SOC_MPI_SUPPORTED
bool
default y
config SOC_SHA_SUPPORTED
bool
default y
config SOC_HMAC_SUPPORTED
bool
default y
config SOC_DIG_SIGN_SUPPORTED
bool
default y
soc: add capability macros for security features - Security features covers "secure boot", "flash encryption" etc. - ECO revision specific modifications still need to be handled through kconfig itself, as soc_caps.h is processed before ECO revision selection - This will simplify addition of security features for newer chips by using these SOC capability macros
2022-03-31 08:13:50 -04:00
config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_SECURE_BOOT_SUPPORTED
bool
default y
esp_system: move MEMPROT related configuration to soc capability header Closes IDF-4506
2022-06-23 00:52:11 -04:00
config SOC_MEMPROT_SUPPORTED
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_GDMA
bool
default y
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
adc: support adc dma driver on all chips
2021-12-15 01:15:32 -05:00
config SOC_ADC_DIG_CTRL_SUPPORTED
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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config SOC_ADC_ARBITER_SUPPORTED
bool
default y
config SOC_ADC_FILTER_SUPPORTED
bool
default y
config SOC_ADC_MONITOR_SUPPORTED
bool
default y
esp_adc: new esp_adc component and adc drivers
2022-07-15 00:52:44 -04:00
config SOC_ADC_DMA_SUPPORTED
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
adc: create common adc hal layer
2022-03-24 05:45:58 -04:00
config SOC_ADC_ATTEN_NUM
int
default 4
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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config SOC_ADC_DIGI_CONTROLLER_NUM
adc: support adc dma driver on all chips
2021-12-15 01:15:32 -05:00
int
default 1
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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config SOC_ADC_PATT_LEN_MAX
int
default 8
esp_adc: new esp_adc component and adc drivers
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config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
esp_adc: new esp_adc component and adc drivers
2022-07-15 00:52:44 -04:00
config SOC_ADC_DIGI_RESULT_BYTES
int
default 4
config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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config SOC_ADC_DIGI_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
adc: create common adc hal layer
2022-03-24 05:45:58 -04:00
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_APB_BACKUP_DMA
bool
default y
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
cache/mmu: implememnt cache and mmu hal APIs in bootloader
2022-02-11 02:30:54 -05:00
config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
refactor (soc, esp_rom)!: removed target-specific ROM dependencies
2022-05-23 04:23:07 -04:00
config SOC_CACHE_MEMORY_IBANK_SIZE
hex
default 0x4000
esp_hw_support: Add esp_cpu.h abstraction and API This commit updates the esp_cpu.h API. The new API presents a new abstraction of the CPU where CPU presents the following interfaces: - CPU Control (to stall/unstall/reset the CPU) - CPU Registers (to read registers commonly used in SW such as SP, PC) - CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts) - Memory Port (to configure the CPU's memory bus for memory protection) - Debugging (to configure/control the CPU's debugging port) Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc builds for esp_cpu.h
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config SOC_CPU_CORES_NUM
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
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int
esp_hw_support: Add esp_cpu.h abstraction and API This commit updates the esp_cpu.h API. The new API presents a new abstraction of the CPU where CPU presents the following interfaces: - CPU Control (to stall/unstall/reset the CPU) - CPU Registers (to read registers commonly used in SW such as SP, PC) - CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts) - Memory Port (to configure the CPU's memory bus for memory protection) - Debugging (to configure/control the CPU's debugging port) Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc builds for esp_cpu.h
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default 1
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
esp_hw_support: Add esp_cpu.h abstraction and API This commit updates the esp_cpu.h API. The new API presents a new abstraction of the CPU where CPU presents the following interfaces: - CPU Control (to stall/unstall/reset the CPU) - CPU Registers (to read registers commonly used in SW such as SP, PC) - CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts) - Memory Port (to configure the CPU's memory bus for memory protection) - Debugging (to configure/control the CPU's debugging port) Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc builds for esp_cpu.h
2022-06-07 02:46:23 -04:00
config SOC_CPU_INTR_NUM
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
int
esp_hw_support: Add esp_cpu.h abstraction and API This commit updates the esp_cpu.h API. The new API presents a new abstraction of the CPU where CPU presents the following interfaces: - CPU Control (to stall/unstall/reset the CPU) - CPU Registers (to read registers commonly used in SW such as SP, PC) - CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts) - Memory Port (to configure the CPU's memory bus for memory protection) - Debugging (to configure/control the CPU's debugging port) Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc builds for esp_cpu.h
2022-06-07 02:46:23 -04:00
default 32
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_CPU_HAS_FLEXIBLE_INTC
bool
default y
esp_hw_support: Add esp_cpu.h abstraction and API This commit updates the esp_cpu.h API. The new API presents a new abstraction of the CPU where CPU presents the following interfaces: - CPU Control (to stall/unstall/reset the CPU) - CPU Registers (to read registers commonly used in SW such as SP, PC) - CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts) - Memory Port (to configure the CPU's memory bus for memory protection) - Debugging (to configure/control the CPU's debugging port) Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc builds for esp_cpu.h
2022-06-07 02:46:23 -04:00
config SOC_CPU_BREAKPOINTS_NUM
int
default 8
config SOC_CPU_WATCHPOINTS_NUM
int
default 8
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_CPU_WATCHPOINT_SIZE
hex
default 0x80000000
config SOC_DS_SIGNATURE_MAX_BIT_LEN
int
default 3072
config SOC_DS_KEY_PARAM_MD_IV_LENGTH
int
default 16
config SOC_DS_KEY_CHECK_MAX_WAIT_US
int
default 1100
config SOC_GDMA_GROUPS
int
default 1
config SOC_GDMA_PAIRS_PER_GROUP
int
default 3
config SOC_GDMA_TX_RX_SHARE_INTERRUPT
bool
default y
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 22
config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_SUPPORT_SLP_SWITCH
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
fast_gpio: fix wrong initial occupy mask
2021-12-01 07:15:05 -05:00
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
bool
default y
config SOC_I2C_NUM
int
default 1
config SOC_I2C_FIFO_LEN
int
default 32
i2c: support esp32c2
2022-01-04 06:46:53 -05:00
config SOC_I2C_SUPPORT_SLAVE
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_RTC
bool
default y
config SOC_I2S_NUM
i2s: extract std/pdm/tdm modes Type structures of these modes are defined. Driver and HAL layer are modified to fit these concepts.
2022-03-13 23:34:46 -04:00
bool
default y
config SOC_I2S_HW_VERSION_2
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_I2S_SUPPORTS_PCM
bool
default y
i2s: extract std/pdm/tdm modes Type structures of these modes are defined. Driver and HAL layer are modified to fit these concepts.
2022-03-13 23:34:46 -04:00
config SOC_I2S_SUPPORTS_PDM
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_SUPPORTS_PDM_CODEC
bool
default y
config SOC_I2S_SUPPORTS_TDM
bool
default y
ledc: Provide support for esp32c2 and esp32h2 LEDC examples, unit test, and programming guide are all updated.
2022-02-08 23:50:19 -05:00
config SOC_LEDC_SUPPORT_APB_CLOCK
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6
config SOC_LEDC_TIMER_BIT_WIDE_NUM
int
default 14
ledc: Add ledc_fade_stop API to support stopping the fade operation. Note that ESP32 cannot support this new feature.
2022-01-10 08:07:58 -05:00
config SOC_LEDC_SUPPORT_FADE_STOP
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
bool
default n
config SOC_MPU_MIN_REGION_SIZE
hex
default 0x20000000
config SOC_MPU_REGIONS_MAX_NUM
int
default 8
config SOC_MPU_REGION_RO_SUPPORTED
bool
default n
config SOC_MPU_REGION_WO_SUPPORTED
bool
default n
config SOC_RMT_GROUPS
int
default 1
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_CHANNELS_PER_GROUP
int
default 4
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
default 48
config SOC_RMT_SUPPORT_RX_PINGPONG
bool
default y
config SOC_RMT_SUPPORT_RX_DEMODULATION
bool
default y
rmt: document and improve LL driver
2022-03-01 02:06:29 -05:00
config SOC_RMT_SUPPORT_TX_ASYNC_STOP
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
bool
default y
config SOC_RMT_SUPPORT_TX_SYNCHRO
bool
default y
driver_ng: implement new rmt driver The legacy driver can't handle the breaking change between esp chips very well. And it's not elegant to extend new feature like DMA, ETM. The new driver can return a opaque handle for each RMT channel. An obvious transaction concept was also introduced. TX and RX functionalities are splited out.
2022-04-06 23:59:46 -04:00
config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
rmt: document and improve LL driver
2022-03-01 02:06:29 -05:00
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_RMT_SUPPORT_XTAL
bool
default y
rmt: add more clock source caps
2022-04-21 02:46:06 -04:00
config SOC_RMT_SUPPORT_APB
bool
default y
config SOC_RMT_SUPPORT_RC_FAST
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
int
default 128
config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
int
default 108
pm: fixed RTC8M domain power issues introduced in e44ead535640525969c7e85892f38ca349d5ddf4 1. The int8M power domain config by default is PD. While LEDC is using RTC8M as clock source, this power domain will be kept on. But when 8MD256 is used as RTC clock source, the power domain should also be kept on. On ESP32, there was protection for it, but broken by commit e44ead535640525969c7e85892f38ca349d5ddf4. Currently the power domain will be forced on when LEDC is using RTC8M as clock source && !int8m_pd_en (user enable ESP_PDP_DOMAIN_RTC8M in lightsleep). Otherwise the power domain will be powered off, regardless of RTC clock source. In other words, int8M domain will be forced off (even when 8MD256 used as RTC clock source) if LEDC not using RTC8M as clock source, user doesn't enable ESP_PDP_DOMAIN_RTC8M, or in deep sleep. On later chips, there's no such protection, so 8MD256 could't be used as RTC clock source in sleep modes. This commit adds protection of 8MD256 clock to other chips. Fixes the incorrect protection logic overriding on ESP32. Now the power domain will be determiend by the logic below (order by priority): 1. When RTC clock source uses 8MD256, power up 2. When LEDC uses RTC8M clock source, power up 3. In deepsleep, power down 4. Otherwise determined by user config of ESP_PDP_DOMAIN_RTC8M, power down by default. (This is preferred to have highest priority, but it's kept as is because of current code structure.) 2. Before, after the macro `RTC_SLEEP_CONFIG_DEFAULT` decides dbias, the protection above may force the int8m PU. This may cause the inconsistent of dbias and the int8m PU status. This commit lifts the logic of pd int8m/xtal fpu logic to upper layer (sleep_modes.c). Related: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089 temp
2022-03-26 15:02:22 -04:00
config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_RTCIO_PIN_COUNT
soc: updated soc_caps about rtc_io and the format
2021-12-31 03:58:03 -05:00
int
default 0
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_RSA_MAX_BIT_LEN
int
default 3072
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
sdm: clean up soc/hal/ll code
2022-05-17 01:47:14 -04:00
config SOC_SDM_GROUPS
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
int
default 1
sdm: clean up soc/hal/ll code
2022-05-17 01:47:14 -04:00
config SOC_SDM_CHANNELS_PER_GROUP
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
int
default 4
config SOC_SPI_PERIPH_NUM
int
default 2
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
bool
default y
config SOC_SPI_MEM_SUPPORT_IDLE_INTR
bool
default y
config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_CHECK_SUS
bool
default y
fix ld err since esp32c2 do not suport config gpio of spi flash via efuse
2022-01-24 22:02:52 -05:00
config SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
bool
default y
spi_flash: refactor the spi_flash clock configuration, and add support for esp32c2
2022-04-12 04:37:40 -04:00
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
hal: use systimer HAL IMPL in ESP32C2 ROM
2022-04-24 04:40:32 -04:00
config SOC_SYSTIMER_SUPPORTED
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_SYSTIMER_COUNTER_NUM
int
default 2
config SOC_SYSTIMER_ALARM_NUM
int
default 3
config SOC_SYSTIMER_BIT_WIDTH_LO
int
default 32
config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
esp_timer, hal: add support for non-integer systimer frequency When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always assumed that systimer tick frequency is integer (and 1 MHz * power of two, above that!). This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV. It should be set in such a way that: 1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the actual systimer tick frequency, 2. and SYSTIMER_LL_TICKS_PER_US is integer. For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and SYSTIMER_LL_TICKS_PER_US_DIV = 5. This introduced two possible issues: 1. Overflow when multiplying systimer counter by 5 - Should not be an issue, since systimer counter is 52-bit, so counter * 5 is no more than 55-bit. 2. The code needs to perform: - divide by 5: when converting from microseconds to ticks - divide by 52: when converting from ticks to microseconds The latter potentially introduces a performance issue for the esp_timer_get_time function.
2022-07-01 13:58:23 -04:00
config SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_SYSTIMER_INT_LEVEL
bool
default y
config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_TIMER_GROUPS
int
default 2
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
timer: fix wrong kconfig soc caps
2021-12-16 10:13:09 -05:00
int
default 1
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 54
config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
clk_tree: added default clock source for peripheral
2022-04-13 01:12:30 -04:00
config SOC_TIMER_GROUP_SUPPORT_APB
bool
default y
timer: fix wrong kconfig soc caps
2021-12-16 10:13:09 -05:00
config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_TWAI_BRP_MIN
int
default 2
config SOC_TWAI_BRP_MAX
int
default 16384
config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
soc: add capability macros for security features - Security features covers "secure boot", "flash encryption" etc. - ECO revision specific modifications still need to be handled through kconfig itself, as soc_caps.h is processed before ECO revision selection - This will simplify addition of security features for newer chips by using these SOC capability macros
2022-03-31 08:13:50 -04:00
config SOC_SECURE_BOOT_V2_RSA
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 32
soc: add capability macros for security features - Security features covers "secure boot", "flash encryption" etc. - ECO revision specific modifications still need to be handled through kconfig itself, as soc_caps.h is processed before ECO revision selection - This will simplify addition of security features for newer chips by using these SOC capability macros
2022-03-31 08:13:50 -04:00
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
esp_system: move MEMPROT related configuration to soc capability header Closes IDF-4506
2022-06-23 00:52:11 -04:00
config SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
int
default 16
config SOC_MEMPROT_MEM_ALIGN_SIZE
int
default 512
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_UART_NUM
int
default 2
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_RTC_CLK
bool
default y
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
uart: support light sleep on esp32s3
2022-01-11 22:03:38 -05:00
config SOC_UART_SUPPORT_WAKEUP_INT
debug: esp32c3 uart1 wakeup
2021-07-27 03:46:23 -04:00
bool
default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig.
2021-11-05 05:23:24 -04:00
config SOC_UART_REQUIRE_CORE_RESET
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_COEX_HW_PTI
bool
default y
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21
config SOC_MAC_BB_PD_MEM_SIZE
int
default 192
config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int
default 12
config SOC_PM_SUPPORT_WIFI_WAKEUP
bool
default y
config SOC_PM_SUPPORT_BT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_WIFI_PD
bool
default y
config SOC_PM_SUPPORT_BT_PD
bool
default y
Temperature_sensor: Create new temperature sensor API
2022-03-04 05:04:20 -05:00
config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
bool
default y
config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL
bool
default y
esp_wifi: optimize wifi kconfig
2022-05-10 04:00:01 -04:00
config SOC_WIFI_HW_TSF
bool
default y
config SOC_WIFI_FTM_SUPPORT
bool
default y
config SOC_WIFI_GCMP_SUPPORT
bool
default y
esp_wifi: esp32c2 does not support wapi.
2022-06-19 23:42:12 -04:00
config SOC_WIFI_WAPI_SUPPORT
bool
default y
esp_wifi: esp32c2 does not support csi.
2022-06-20 09:35:52 -04:00
config SOC_WIFI_CSI_SUPPORT
bool
default y
esp_wifi: esp32c2 does not support wifi mesh
2022-06-21 04:48:52 -04:00
config SOC_WIFI_MESH_SUPPORT
bool
default y
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