2021-10-25 05:13:46 -04:00
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/*
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2021-12-15 10:30:29 -05:00
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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2021-10-25 05:13:46 -04:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2019-04-10 04:24:50 -04:00
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#include <string.h>
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#include <stdlib.h>
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#include <sys/cdefs.h>
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2021-12-01 03:53:25 -05:00
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#include <stdarg.h>
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2021-10-25 05:13:46 -04:00
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#include "esp_private/periph_ctrl.h"
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2019-04-10 04:24:50 -04:00
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#include "driver/gpio.h"
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2019-11-13 23:03:14 -05:00
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#include "esp_attr.h"
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2019-04-10 04:24:50 -04:00
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#include "esp_log.h"
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2021-04-01 08:00:54 -04:00
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#include "esp_check.h"
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2022-05-27 03:06:42 -04:00
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#include "esp_eth_driver.h"
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2019-11-29 01:49:02 -05:00
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#include "esp_pm.h"
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2022-01-12 01:53:47 -05:00
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#include "esp_mac.h"
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2022-07-21 07:24:42 -04:00
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#include "esp_cpu.h"
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2019-04-10 04:24:50 -04:00
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#include "esp_heap_caps.h"
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#include "esp_intr_alloc.h"
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2021-05-07 05:38:36 -04:00
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#include "esp_private/esp_clk.h"
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2019-04-10 04:24:50 -04:00
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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2021-05-07 05:38:36 -04:00
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#include "hal/emac_hal.h"
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2021-03-15 22:55:05 -04:00
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#include "hal/gpio_hal.h"
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2019-04-10 04:24:50 -04:00
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#include "soc/soc.h"
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2022-01-12 01:53:47 -05:00
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#include "clk_ctrl_os.h"
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2019-04-10 04:24:50 -04:00
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#include "sdkconfig.h"
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2020-06-19 00:00:58 -04:00
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#include "esp_rom_gpio.h"
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2020-07-21 01:07:34 -04:00
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#include "esp_rom_sys.h"
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2021-05-07 05:38:36 -04:00
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#include "hal/emac_ll.h"
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2019-04-10 04:24:50 -04:00
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2021-04-01 08:00:54 -04:00
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static const char *TAG = "esp.emac";
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2019-04-10 04:24:50 -04:00
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2019-06-25 07:36:56 -04:00
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#define PHY_OPERATION_TIMEOUT_US (1000)
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2023-01-30 03:28:44 -05:00
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#define MAC_STOP_TIMEOUT_US (2500) // this is absolute maximum for 10Mbps, it is 10 times faster for 100Mbps
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2020-07-20 08:42:52 -04:00
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#define FLOW_CONTROL_LOW_WATER_MARK (CONFIG_ETH_DMA_RX_BUFFER_NUM / 3)
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#define FLOW_CONTROL_HIGH_WATER_MARK (FLOW_CONTROL_LOW_WATER_MARK * 2)
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2019-04-10 04:24:50 -04:00
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typedef struct {
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esp_eth_mac_t parent;
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esp_eth_mediator_t *eth;
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2019-07-10 22:47:17 -04:00
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emac_hal_context_t hal;
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2019-04-10 04:24:50 -04:00
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intr_handle_t intr_hdl;
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TaskHandle_t rx_task_hdl;
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uint32_t sw_reset_timeout_ms;
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uint32_t frames_remain;
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2020-07-20 08:42:52 -04:00
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uint32_t free_rx_descriptor;
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uint32_t flow_control_high_water_mark;
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uint32_t flow_control_low_water_mark;
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2019-11-13 23:03:14 -05:00
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int smi_mdc_gpio_num;
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int smi_mdio_gpio_num;
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2021-06-23 10:23:58 -04:00
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eth_mac_clock_config_t clock_config;
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2019-04-10 04:24:50 -04:00
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uint8_t addr[6];
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uint8_t *rx_buf[CONFIG_ETH_DMA_RX_BUFFER_NUM];
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uint8_t *tx_buf[CONFIG_ETH_DMA_TX_BUFFER_NUM];
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2019-07-10 23:01:51 -04:00
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bool isr_need_yield;
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2020-07-20 08:42:52 -04:00
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bool flow_ctrl_enabled; // indicates whether the user want to do flow control
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bool do_flow_ctrl; // indicates whether we need to do software flow control
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2021-12-02 07:24:19 -05:00
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bool use_apll; // Only use APLL in EMAC_DATA_INTERFACE_RMII && EMAC_CLK_OUT
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2019-11-29 01:49:02 -05:00
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_handle_t pm_lock;
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#endif
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2022-01-14 03:29:08 -05:00
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eth_mac_dma_burst_len_t dma_burst_len;
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2019-04-10 04:24:50 -04:00
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} emac_esp32_t;
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2021-07-13 03:09:11 -04:00
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static esp_err_t esp_emac_alloc_driver_obj(const eth_mac_config_t *config, emac_esp32_t **emac_out_hdl, void **out_descriptors);
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static void esp_emac_free_driver_obj(emac_esp32_t *emac, void *descriptors);
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2022-01-26 03:55:36 -05:00
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static esp_err_t emac_esp32_start(esp_eth_mac_t *mac);
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static esp_err_t emac_esp32_stop(esp_eth_mac_t *mac);
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2021-07-13 03:09:11 -04:00
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2019-04-10 04:24:50 -04:00
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static esp_err_t emac_esp32_set_mediator(esp_eth_mac_t *mac, esp_eth_mediator_t *eth)
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{
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esp_err_t ret = ESP_OK;
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_FALSE(eth, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac's mediator to null");
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2019-04-10 04:24:50 -04:00
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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emac->eth = eth;
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_esp32_write_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr, uint32_t phy_reg, uint32_t reg_value)
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{
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esp_err_t ret = ESP_OK;
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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2021-05-07 05:38:36 -04:00
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ESP_GOTO_ON_FALSE(!emac_ll_is_mii_busy(emac->hal.mac_regs), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
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emac_ll_set_phy_data(emac->hal.mac_regs, reg_value);
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2019-07-10 22:47:17 -04:00
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emac_hal_set_phy_cmd(&emac->hal, phy_addr, phy_reg, true);
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2019-06-25 07:36:56 -04:00
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/* polling the busy flag */
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uint32_t to = 0;
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bool busy = true;
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do {
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2020-07-21 01:07:34 -04:00
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esp_rom_delay_us(100);
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2021-05-07 05:38:36 -04:00
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busy = emac_ll_is_mii_busy(emac->hal.mac_regs);
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2019-06-25 07:36:56 -04:00
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to += 100;
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} while (busy && to < PHY_OPERATION_TIMEOUT_US);
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_FALSE(!busy, ESP_ERR_TIMEOUT, err, TAG, "phy is busy");
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2019-04-10 04:24:50 -04:00
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_esp32_read_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr, uint32_t phy_reg, uint32_t *reg_value)
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{
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esp_err_t ret = ESP_OK;
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_FALSE(reg_value, ESP_ERR_INVALID_ARG, err, TAG, "can't set reg_value to null");
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2019-04-10 04:24:50 -04:00
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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2021-05-07 05:38:36 -04:00
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ESP_GOTO_ON_FALSE(!emac_ll_is_mii_busy(emac->hal.mac_regs), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
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2019-07-10 22:47:17 -04:00
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emac_hal_set_phy_cmd(&emac->hal, phy_addr, phy_reg, false);
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2019-06-25 07:36:56 -04:00
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/* polling the busy flag */
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uint32_t to = 0;
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bool busy = true;
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do {
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2020-07-21 01:07:34 -04:00
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esp_rom_delay_us(100);
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2021-05-07 05:38:36 -04:00
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busy = emac_ll_is_mii_busy(emac->hal.mac_regs);
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2019-06-25 07:36:56 -04:00
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to += 100;
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} while (busy && to < PHY_OPERATION_TIMEOUT_US);
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_FALSE(!busy, ESP_ERR_TIMEOUT, err, TAG, "phy is busy");
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2019-04-10 04:24:50 -04:00
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/* Store value */
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2021-05-07 05:38:36 -04:00
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*reg_value = emac_ll_get_phy_data(emac->hal.mac_regs);
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2019-04-10 04:24:50 -04:00
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_esp32_set_addr(esp_eth_mac_t *mac, uint8_t *addr)
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{
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esp_err_t ret = ESP_OK;
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac addr to null");
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2019-04-10 04:24:50 -04:00
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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memcpy(emac->addr, addr, 6);
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2019-07-10 22:47:17 -04:00
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emac_hal_set_address(&emac->hal, emac->addr);
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2019-04-10 04:24:50 -04:00
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_esp32_get_addr(esp_eth_mac_t *mac, uint8_t *addr)
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{
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esp_err_t ret = ESP_OK;
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac addr to null");
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2019-04-10 04:24:50 -04:00
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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memcpy(addr, emac->addr, 6);
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_esp32_set_link(esp_eth_mac_t *mac, eth_link_t link)
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{
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esp_err_t ret = ESP_OK;
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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switch (link) {
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case ETH_LINK_UP:
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_ERROR(esp_intr_enable(emac->intr_hdl), err, TAG, "enable interrupt failed");
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2022-01-26 03:55:36 -05:00
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emac_esp32_start(mac);
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2019-04-10 04:24:50 -04:00
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break;
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case ETH_LINK_DOWN:
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_ERROR(esp_intr_disable(emac->intr_hdl), err, TAG, "disable interrupt failed");
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2022-01-26 03:55:36 -05:00
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emac_esp32_stop(mac);
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2019-04-10 04:24:50 -04:00
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break;
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default:
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2021-04-01 08:00:54 -04:00
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ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "unknown link status");
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2019-04-10 04:24:50 -04:00
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break;
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}
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return ESP_OK;
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err:
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return ret;
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}
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static esp_err_t emac_esp32_set_speed(esp_eth_mac_t *mac, eth_speed_t speed)
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{
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2021-05-07 05:38:36 -04:00
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esp_err_t ret = ESP_ERR_INVALID_ARG;
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2019-04-10 04:24:50 -04:00
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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2021-05-07 05:38:36 -04:00
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if (speed >= ETH_SPEED_10M && speed < ETH_SPEED_MAX) {
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emac_ll_set_port_speed(emac->hal.mac_regs, speed);
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ESP_LOGD(TAG, "working in %dMbps", speed == ETH_SPEED_10M ? 10 : 100);
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return ESP_OK;
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2019-04-10 04:24:50 -04:00
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}
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return ret;
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}
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static esp_err_t emac_esp32_set_duplex(esp_eth_mac_t *mac, eth_duplex_t duplex)
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{
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2021-05-07 05:38:36 -04:00
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esp_err_t ret = ESP_ERR_INVALID_ARG;
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2019-04-10 04:24:50 -04:00
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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2021-05-07 05:38:36 -04:00
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if (duplex == ETH_DUPLEX_HALF || duplex == ETH_DUPLEX_FULL) {
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emac_ll_set_duplex(emac->hal.mac_regs, duplex);
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ESP_LOGD(TAG, "working in %s duplex", duplex == ETH_DUPLEX_HALF ? "half" : "full");
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return ESP_OK;
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2019-04-10 04:24:50 -04:00
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}
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return ret;
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}
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static esp_err_t emac_esp32_set_promiscuous(esp_eth_mac_t *mac, bool enable)
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{
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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2021-05-07 05:38:36 -04:00
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emac_ll_promiscuous_mode_enable(emac->hal.mac_regs, enable);
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2019-04-10 04:24:50 -04:00
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return ESP_OK;
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}
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2020-07-20 08:42:52 -04:00
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static esp_err_t emac_esp32_enable_flow_ctrl(esp_eth_mac_t *mac, bool enable)
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{
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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emac->flow_ctrl_enabled = enable;
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return ESP_OK;
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}
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static esp_err_t emac_esp32_set_peer_pause_ability(esp_eth_mac_t *mac, uint32_t ability)
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{
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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// we want to enable flow control, and peer does support pause function
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// then configure the MAC layer to enable flow control feature
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if (emac->flow_ctrl_enabled && ability) {
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emac_hal_enable_flow_ctrl(&emac->hal, true);
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emac->do_flow_ctrl = true;
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} else {
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emac_hal_enable_flow_ctrl(&emac->hal, false);
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emac->do_flow_ctrl = false;
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ESP_LOGD(TAG, "Flow control not enabled for the link");
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}
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return ESP_OK;
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}
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2019-04-10 04:24:50 -04:00
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static esp_err_t emac_esp32_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t length)
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{
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esp_err_t ret = ESP_OK;
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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2019-12-23 04:08:38 -05:00
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uint32_t sent_len = emac_hal_transmit_frame(&emac->hal, buf, length);
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2022-01-11 10:40:39 -05:00
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ESP_GOTO_ON_FALSE(sent_len == length, ESP_ERR_NO_MEM, err, TAG, "insufficient TX buffer size");
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2019-04-10 04:24:50 -04:00
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return ESP_OK;
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err:
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return ret;
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}
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2021-12-01 03:53:25 -05:00
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static esp_err_t emac_esp32_transmit_multiple_bufs(esp_eth_mac_t *mac, uint32_t argc, va_list args)
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{
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esp_err_t ret = ESP_OK;
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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uint8_t *bufs[argc];
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uint32_t len[argc];
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uint32_t exp_len = 0;
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for (int i = 0; i < argc; i++) {
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bufs[i] = va_arg(args, uint8_t*);
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|
len[i] = va_arg(args, uint32_t);
|
|
|
|
exp_len += len[i];
|
|
|
|
}
|
|
|
|
uint32_t sent_len = emac_hal_transmit_multiple_buf_frame(&emac->hal, bufs, len, argc);
|
|
|
|
ESP_GOTO_ON_FALSE(sent_len == exp_len, ESP_ERR_INVALID_SIZE, err, TAG, "insufficient TX buffer size");
|
|
|
|
return ESP_OK;
|
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-04-10 04:24:50 -04:00
|
|
|
static esp_err_t emac_esp32_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t *length)
|
|
|
|
{
|
|
|
|
esp_err_t ret = ESP_OK;
|
2019-12-23 04:08:38 -05:00
|
|
|
uint32_t expected_len = *length;
|
2019-04-10 04:24:50 -04:00
|
|
|
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
|
2021-04-01 08:00:54 -04:00
|
|
|
ESP_GOTO_ON_FALSE(buf && length, ESP_ERR_INVALID_ARG, err, TAG, "can't set buf and length to null");
|
2020-07-20 08:42:52 -04:00
|
|
|
uint32_t receive_len = emac_hal_receive_frame(&emac->hal, buf, expected_len, &emac->frames_remain, &emac->free_rx_descriptor);
|
2019-09-18 23:27:42 -04:00
|
|
|
/* we need to check the return value in case the buffer size is not enough */
|
2021-04-01 08:00:54 -04:00
|
|
|
ESP_GOTO_ON_FALSE(expected_len >= receive_len, ESP_ERR_INVALID_SIZE, err, TAG, "received buffer longer than expected");
|
2019-09-18 23:27:42 -04:00
|
|
|
*length = receive_len;
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
err:
|
2019-12-23 04:08:38 -05:00
|
|
|
*length = expected_len;
|
2019-04-10 04:24:50 -04:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void emac_esp32_rx_task(void *arg)
|
|
|
|
{
|
|
|
|
emac_esp32_t *emac = (emac_esp32_t *)arg;
|
|
|
|
uint8_t *buffer = NULL;
|
|
|
|
while (1) {
|
2020-05-13 04:03:00 -04:00
|
|
|
// block indefinitely until got notification from underlay event
|
|
|
|
ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
|
2019-09-18 23:27:42 -04:00
|
|
|
do {
|
2022-10-20 05:40:56 -04:00
|
|
|
/* set max expected frame len */
|
|
|
|
uint32_t frame_len = ETH_MAX_PACKET_SIZE;
|
|
|
|
buffer = emac_hal_alloc_recv_buf(&emac->hal, &frame_len);
|
2022-11-24 07:37:09 -05:00
|
|
|
/* we have memory to receive the frame of maximal size previously defined */
|
|
|
|
if (buffer != NULL) {
|
|
|
|
uint32_t recv_len = emac_hal_receive_frame(&emac->hal, buffer, EMAC_HAL_BUF_SIZE_AUTO, &emac->frames_remain, &emac->free_rx_descriptor);
|
|
|
|
if (recv_len == 0) {
|
|
|
|
ESP_LOGE(TAG, "frame copy error");
|
|
|
|
free(buffer);
|
2022-10-20 05:40:56 -04:00
|
|
|
/* ensure that interface to EMAC does not get stuck with unprocessed frames */
|
|
|
|
emac_hal_flush_recv_frame(&emac->hal, &emac->frames_remain, &emac->free_rx_descriptor);
|
2022-11-24 07:37:09 -05:00
|
|
|
} else if (frame_len > recv_len) {
|
|
|
|
ESP_LOGE(TAG, "received frame was truncated");
|
|
|
|
free(buffer);
|
|
|
|
} else {
|
|
|
|
ESP_LOGD(TAG, "receive len= %d", recv_len);
|
|
|
|
emac->eth->stack_input(emac->eth, buffer, recv_len);
|
2019-08-28 04:04:50 -04:00
|
|
|
}
|
2022-11-24 07:37:09 -05:00
|
|
|
/* if allocation failed and there is a waiting frame */
|
|
|
|
} else if (frame_len) {
|
|
|
|
ESP_LOGE(TAG, "no mem for receive buffer");
|
|
|
|
/* ensure that interface to EMAC does not get stuck with unprocessed frames */
|
|
|
|
emac_hal_flush_recv_frame(&emac->hal, &emac->frames_remain, &emac->free_rx_descriptor);
|
2019-09-18 23:27:42 -04:00
|
|
|
}
|
2021-01-28 06:10:42 -05:00
|
|
|
#if CONFIG_ETH_SOFT_FLOW_CONTROL
|
2020-07-20 08:42:52 -04:00
|
|
|
// we need to do extra checking of remained frames in case there are no unhandled frames left, but pause frame is still undergoing
|
|
|
|
if ((emac->free_rx_descriptor < emac->flow_control_low_water_mark) && emac->do_flow_ctrl && emac->frames_remain) {
|
2021-05-07 05:38:36 -04:00
|
|
|
emac_ll_pause_frame_enable(emac->hal.ext_regs, true);
|
2020-07-20 08:42:52 -04:00
|
|
|
} else if ((emac->free_rx_descriptor > emac->flow_control_high_water_mark) || !emac->frames_remain) {
|
2021-05-07 05:38:36 -04:00
|
|
|
emac_ll_pause_frame_enable(emac->hal.ext_regs, false);
|
2020-07-20 08:42:52 -04:00
|
|
|
}
|
2021-01-28 06:10:42 -05:00
|
|
|
#endif
|
2019-09-18 23:27:42 -04:00
|
|
|
} while (emac->frames_remain);
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
vTaskDelete(NULL);
|
|
|
|
}
|
|
|
|
|
2019-11-13 23:03:14 -05:00
|
|
|
static void emac_esp32_init_smi_gpio(emac_esp32_t *emac)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2020-09-23 12:03:10 -04:00
|
|
|
if (emac->smi_mdc_gpio_num >= 0) {
|
|
|
|
/* Setup SMI MDC GPIO */
|
|
|
|
gpio_set_direction(emac->smi_mdc_gpio_num, GPIO_MODE_OUTPUT);
|
|
|
|
esp_rom_gpio_connect_out_signal(emac->smi_mdc_gpio_num, EMAC_MDC_O_IDX, false, false);
|
2021-03-15 22:55:05 -04:00
|
|
|
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[emac->smi_mdc_gpio_num], PIN_FUNC_GPIO);
|
2020-09-23 12:03:10 -04:00
|
|
|
}
|
|
|
|
if (emac->smi_mdio_gpio_num >= 0) {
|
|
|
|
/* Setup SMI MDIO GPIO */
|
|
|
|
gpio_set_direction(emac->smi_mdio_gpio_num, GPIO_MODE_INPUT_OUTPUT);
|
|
|
|
esp_rom_gpio_connect_out_signal(emac->smi_mdio_gpio_num, EMAC_MDO_O_IDX, false, false);
|
|
|
|
esp_rom_gpio_connect_in_signal(emac->smi_mdio_gpio_num, EMAC_MDI_I_IDX, false);
|
2021-03-15 22:55:05 -04:00
|
|
|
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[emac->smi_mdio_gpio_num], PIN_FUNC_GPIO);
|
2020-09-23 12:03:10 -04:00
|
|
|
}
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
|
|
|
|
2021-12-02 07:24:19 -05:00
|
|
|
static esp_err_t emac_config_apll_clock(void)
|
2021-05-07 05:38:36 -04:00
|
|
|
{
|
2021-12-02 07:24:19 -05:00
|
|
|
uint32_t expt_freq = 50000000; // 50MHz
|
|
|
|
uint32_t real_freq = 0;
|
|
|
|
esp_err_t ret = periph_rtc_apll_freq_set(expt_freq, &real_freq);
|
|
|
|
ESP_RETURN_ON_FALSE(ret != ESP_ERR_INVALID_ARG, ESP_FAIL, TAG, "Set APLL clock coefficients failed");
|
|
|
|
if (ret == ESP_ERR_INVALID_STATE) {
|
|
|
|
ESP_LOGW(TAG, "APLL is occupied already, it is working at %d Hz", real_freq);
|
2021-05-07 05:38:36 -04:00
|
|
|
}
|
2021-12-02 07:24:19 -05:00
|
|
|
// If the difference of real APLL frequency is not within 50 ppm, i.e. 2500 Hz, the APLL is unavailable
|
2022-01-20 03:13:05 -05:00
|
|
|
ESP_RETURN_ON_FALSE(abs((int)real_freq - (int)expt_freq) <= 2500,
|
2021-12-02 07:24:19 -05:00
|
|
|
ESP_ERR_INVALID_STATE, TAG, "The APLL is working at an unusable frequency");
|
|
|
|
|
|
|
|
return ESP_OK;
|
2021-05-07 05:38:36 -04:00
|
|
|
}
|
|
|
|
|
2019-04-10 04:24:50 -04:00
|
|
|
static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
|
|
|
|
{
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
|
|
|
|
esp_eth_mediator_t *eth = emac->eth;
|
2021-05-07 05:38:36 -04:00
|
|
|
|
2019-12-23 04:08:38 -05:00
|
|
|
/* init gpio used by smi interface */
|
2019-11-13 23:03:14 -05:00
|
|
|
emac_esp32_init_smi_gpio(emac);
|
2021-04-01 08:00:54 -04:00
|
|
|
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LLINIT, NULL), err, TAG, "lowlevel init failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
/* software reset */
|
2021-05-07 05:38:36 -04:00
|
|
|
emac_ll_reset(emac->hal.dma_regs);
|
2019-04-10 04:24:50 -04:00
|
|
|
uint32_t to = 0;
|
|
|
|
for (to = 0; to < emac->sw_reset_timeout_ms / 10; to++) {
|
2021-05-07 05:38:36 -04:00
|
|
|
if (emac_ll_is_reset_done(emac->hal.dma_regs)) {
|
2019-04-10 04:24:50 -04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
vTaskDelay(pdMS_TO_TICKS(10));
|
|
|
|
}
|
2021-04-01 08:00:54 -04:00
|
|
|
ESP_GOTO_ON_FALSE(to < emac->sw_reset_timeout_ms / 10, ESP_ERR_TIMEOUT, err, TAG, "reset timeout");
|
2019-04-10 04:24:50 -04:00
|
|
|
/* set smi clock */
|
2021-05-07 05:38:36 -04:00
|
|
|
emac_hal_set_csr_clock_range(&emac->hal, esp_clk_apb_freq());
|
2019-04-10 04:24:50 -04:00
|
|
|
/* init mac registers by default */
|
2019-07-10 22:47:17 -04:00
|
|
|
emac_hal_init_mac_default(&emac->hal);
|
2022-01-24 09:40:11 -05:00
|
|
|
/* init dma registers with selected EMAC-DMA configuration */
|
|
|
|
emac_hal_dma_config_t dma_config = { .dma_burst_len = emac->dma_burst_len };
|
|
|
|
emac_hal_init_dma_default(&emac->hal, &dma_config);
|
2019-04-10 04:24:50 -04:00
|
|
|
/* get emac address from efuse */
|
2021-04-01 08:00:54 -04:00
|
|
|
ESP_GOTO_ON_ERROR(esp_read_mac(emac->addr, ESP_MAC_ETH), err, TAG, "fetch ethernet mac address failed");
|
2019-04-10 04:24:50 -04:00
|
|
|
/* set MAC address to emac register */
|
2019-07-10 22:47:17 -04:00
|
|
|
emac_hal_set_address(&emac->hal, emac->addr);
|
2019-11-29 01:49:02 -05:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
esp_pm_lock_acquire(emac->pm_lock);
|
|
|
|
#endif
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
err:
|
|
|
|
eth->on_state_changed(eth, ETH_STATE_DEINIT, NULL);
|
2019-06-25 07:36:56 -04:00
|
|
|
periph_module_disable(PERIPH_EMAC_MODULE);
|
2019-04-10 04:24:50 -04:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t emac_esp32_deinit(esp_eth_mac_t *mac)
|
|
|
|
{
|
|
|
|
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
|
|
|
|
esp_eth_mediator_t *eth = emac->eth;
|
2019-11-29 01:49:02 -05:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
esp_pm_lock_release(emac->pm_lock);
|
|
|
|
#endif
|
2019-07-10 22:47:17 -04:00
|
|
|
emac_hal_stop(&emac->hal);
|
2019-06-25 07:36:56 -04:00
|
|
|
eth->on_state_changed(eth, ETH_STATE_DEINIT, NULL);
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2020-05-08 09:44:30 -04:00
|
|
|
static esp_err_t emac_esp32_start(esp_eth_mac_t *mac)
|
|
|
|
{
|
|
|
|
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
|
2023-01-30 03:28:44 -05:00
|
|
|
/* reset descriptor chain */
|
2021-12-20 06:45:24 -05:00
|
|
|
emac_hal_reset_desc_chain(&emac->hal);
|
2020-05-08 09:44:30 -04:00
|
|
|
emac_hal_start(&emac->hal);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t emac_esp32_stop(esp_eth_mac_t *mac)
|
|
|
|
{
|
|
|
|
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
|
2021-12-20 06:45:24 -05:00
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
int32_t to = 0;
|
|
|
|
do {
|
|
|
|
if ((ret = emac_hal_stop(&emac->hal)) == ESP_OK) {
|
|
|
|
break;
|
|
|
|
}
|
2022-01-26 03:55:36 -05:00
|
|
|
to += 25;
|
|
|
|
esp_rom_delay_us(25);
|
|
|
|
} while (to < MAC_STOP_TIMEOUT_US);
|
2021-12-20 06:45:24 -05:00
|
|
|
return ret;
|
2020-05-08 09:44:30 -04:00
|
|
|
}
|
|
|
|
|
2019-04-10 04:24:50 -04:00
|
|
|
static esp_err_t emac_esp32_del(esp_eth_mac_t *mac)
|
|
|
|
{
|
|
|
|
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
|
2021-07-13 03:09:11 -04:00
|
|
|
esp_emac_free_driver_obj(emac, emac->hal.descriptors);
|
|
|
|
periph_module_disable(PERIPH_EMAC_MODULE);
|
2019-04-10 04:24:50 -04:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2020-01-13 08:34:23 -05:00
|
|
|
// To achieve a better performance, we put the ISR always in IRAM
|
2021-05-07 05:38:36 -04:00
|
|
|
IRAM_ATTR void emac_isr_default_handler(void *args)
|
2019-07-10 23:01:51 -04:00
|
|
|
{
|
|
|
|
emac_hal_context_t *hal = (emac_hal_context_t *)args;
|
|
|
|
emac_esp32_t *emac = __containerof(hal, emac_esp32_t, hal);
|
2021-05-07 05:38:36 -04:00
|
|
|
BaseType_t high_task_wakeup = pdFALSE;
|
|
|
|
uint32_t intr_stat = emac_ll_get_intr_status(hal->dma_regs);
|
|
|
|
emac_ll_clear_corresponding_intr(hal->dma_regs, intr_stat);
|
|
|
|
|
|
|
|
#if EMAC_LL_CONFIG_ENABLE_INTR_MASK & EMAC_LL_INTR_RECEIVE_ENABLE
|
|
|
|
if (intr_stat & EMAC_LL_DMA_RECEIVE_FINISH_INTR) {
|
|
|
|
/* notify receive task */
|
|
|
|
vTaskNotifyGiveFromISR(emac->rx_task_hdl, &high_task_wakeup);
|
|
|
|
if (high_task_wakeup == pdTRUE) {
|
|
|
|
portYIELD_FROM_ISR();
|
|
|
|
}
|
2019-07-10 23:01:51 -04:00
|
|
|
}
|
2021-05-07 05:38:36 -04:00
|
|
|
#endif
|
2019-07-10 23:01:51 -04:00
|
|
|
}
|
|
|
|
|
2021-07-13 03:09:11 -04:00
|
|
|
static void esp_emac_free_driver_obj(emac_esp32_t *emac, void *descriptors)
|
2019-04-10 04:24:50 -04:00
|
|
|
{
|
2021-07-13 03:09:11 -04:00
|
|
|
if (emac) {
|
|
|
|
if (emac->rx_task_hdl) {
|
|
|
|
vTaskDelete(emac->rx_task_hdl);
|
|
|
|
}
|
|
|
|
if (emac->intr_hdl) {
|
|
|
|
esp_intr_free(emac->intr_hdl);
|
|
|
|
}
|
2021-12-02 07:24:19 -05:00
|
|
|
if (emac->use_apll) {
|
|
|
|
periph_rtc_apll_release();
|
|
|
|
}
|
2021-07-13 03:09:11 -04:00
|
|
|
for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) {
|
|
|
|
free(emac->tx_buf[i]);
|
|
|
|
}
|
|
|
|
for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) {
|
|
|
|
free(emac->rx_buf[i]);
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
if (emac->pm_lock) {
|
|
|
|
esp_pm_lock_delete(emac->pm_lock);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
free(emac);
|
|
|
|
}
|
|
|
|
if (descriptors) {
|
|
|
|
free(descriptors);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t esp_emac_alloc_driver_obj(const eth_mac_config_t *config, emac_esp32_t **emac_out_hdl, void **out_descriptors)
|
|
|
|
{
|
|
|
|
esp_err_t ret = ESP_OK;
|
2019-09-18 23:27:42 -04:00
|
|
|
emac_esp32_t *emac = NULL;
|
2021-07-13 03:09:11 -04:00
|
|
|
void *descriptors = NULL;
|
2020-01-13 08:34:23 -05:00
|
|
|
if (config->flags & ETH_MAC_FLAG_WORK_WITH_CACHE_DISABLE) {
|
|
|
|
emac = heap_caps_calloc(1, sizeof(emac_esp32_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
|
|
|
|
} else {
|
|
|
|
emac = calloc(1, sizeof(emac_esp32_t));
|
|
|
|
}
|
2021-07-13 03:09:11 -04:00
|
|
|
ESP_GOTO_ON_FALSE(emac, ESP_ERR_NO_MEM, err, TAG, "no mem for esp emac object");
|
2019-04-10 04:24:50 -04:00
|
|
|
/* alloc memory for ethernet dma descriptor */
|
|
|
|
uint32_t desc_size = CONFIG_ETH_DMA_RX_BUFFER_NUM * sizeof(eth_dma_rx_descriptor_t) +
|
|
|
|
CONFIG_ETH_DMA_TX_BUFFER_NUM * sizeof(eth_dma_tx_descriptor_t);
|
2019-09-18 23:27:42 -04:00
|
|
|
descriptors = heap_caps_calloc(1, desc_size, MALLOC_CAP_DMA);
|
2021-07-13 03:09:11 -04:00
|
|
|
ESP_GOTO_ON_FALSE(descriptors, ESP_ERR_NO_MEM, err, TAG, "no mem for descriptors");
|
2019-04-10 04:24:50 -04:00
|
|
|
/* alloc memory for ethernet dma buffer */
|
2021-07-13 03:09:11 -04:00
|
|
|
for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) {
|
2019-04-10 04:24:50 -04:00
|
|
|
emac->rx_buf[i] = heap_caps_calloc(1, CONFIG_ETH_DMA_BUFFER_SIZE, MALLOC_CAP_DMA);
|
2021-07-13 03:09:11 -04:00
|
|
|
ESP_GOTO_ON_FALSE(emac->rx_buf[i], ESP_ERR_NO_MEM, err, TAG, "no mem for RX DMA buffers");
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
2021-07-13 03:09:11 -04:00
|
|
|
for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) {
|
2019-04-10 04:24:50 -04:00
|
|
|
emac->tx_buf[i] = heap_caps_calloc(1, CONFIG_ETH_DMA_BUFFER_SIZE, MALLOC_CAP_DMA);
|
2021-07-13 03:09:11 -04:00
|
|
|
ESP_GOTO_ON_FALSE(emac->tx_buf[i], ESP_ERR_NO_MEM, err, TAG, "no mem for TX DMA buffers");
|
2019-04-10 04:24:50 -04:00
|
|
|
}
|
2021-07-13 03:09:11 -04:00
|
|
|
/* alloc PM lock */
|
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
ESP_GOTO_ON_ERROR(esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "emac_esp32", &emac->pm_lock), err, TAG, "create pm lock failed");
|
|
|
|
#endif
|
|
|
|
/* create rx task */
|
|
|
|
BaseType_t core_num = tskNO_AFFINITY;
|
|
|
|
if (config->flags & ETH_MAC_FLAG_PIN_TO_CORE) {
|
2022-07-21 07:24:42 -04:00
|
|
|
core_num = esp_cpu_get_core_id();
|
2021-07-13 03:09:11 -04:00
|
|
|
}
|
|
|
|
BaseType_t xReturned = xTaskCreatePinnedToCore(emac_esp32_rx_task, "emac_rx", config->rx_task_stack_size, emac,
|
|
|
|
config->rx_task_prio, &emac->rx_task_hdl, core_num);
|
|
|
|
ESP_GOTO_ON_FALSE(xReturned == pdPASS, ESP_FAIL, err, TAG, "create emac_rx task failed");
|
|
|
|
|
|
|
|
*out_descriptors = descriptors;
|
|
|
|
*emac_out_hdl = emac;
|
|
|
|
return ESP_OK;
|
|
|
|
err:
|
|
|
|
esp_emac_free_driver_obj(emac, descriptors);
|
|
|
|
return ret;
|
|
|
|
}
|
2021-06-23 10:23:58 -04:00
|
|
|
|
2022-01-24 09:40:11 -05:00
|
|
|
static esp_err_t esp_emac_config_data_interface(const eth_esp32_emac_config_t *esp32_emac_config, emac_esp32_t *emac)
|
2021-07-13 03:09:11 -04:00
|
|
|
{
|
|
|
|
esp_err_t ret = ESP_OK;
|
2022-01-24 09:40:11 -05:00
|
|
|
switch (esp32_emac_config->interface) {
|
2021-07-13 03:09:11 -04:00
|
|
|
case EMAC_DATA_INTERFACE_MII:
|
2022-01-24 09:40:11 -05:00
|
|
|
emac->clock_config = esp32_emac_config->clock_config;
|
2021-07-13 03:09:11 -04:00
|
|
|
/* MII interface GPIO initialization */
|
|
|
|
emac_hal_iomux_init_mii();
|
|
|
|
/* Enable MII clock */
|
|
|
|
emac_ll_clock_enable_mii(emac->hal.ext_regs);
|
|
|
|
break;
|
|
|
|
case EMAC_DATA_INTERFACE_RMII:
|
|
|
|
// by default, the clock mode is selected at compile time (by Kconfig)
|
2022-01-24 09:40:11 -05:00
|
|
|
if (esp32_emac_config->clock_config.rmii.clock_mode == EMAC_CLK_DEFAULT) {
|
2021-07-13 03:09:11 -04:00
|
|
|
#if CONFIG_ETH_RMII_CLK_INPUT
|
|
|
|
#if CONFIG_ETH_RMII_CLK_IN_GPIO == 0
|
2021-06-23 10:23:58 -04:00
|
|
|
emac->clock_config.rmii.clock_mode = EMAC_CLK_EXT_IN;
|
|
|
|
emac->clock_config.rmii.clock_gpio = CONFIG_ETH_RMII_CLK_IN_GPIO;
|
|
|
|
#else
|
|
|
|
#error "ESP32 EMAC only support input RMII clock to GPIO0"
|
2021-07-13 03:09:11 -04:00
|
|
|
#endif // CONFIG_ETH_RMII_CLK_IN_GPIO == 0
|
|
|
|
#elif CONFIG_ETH_RMII_CLK_OUTPUT
|
2021-06-23 10:23:58 -04:00
|
|
|
emac->clock_config.rmii.clock_mode = EMAC_CLK_OUT;
|
|
|
|
#if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
|
|
|
|
emac->clock_config.rmii.clock_gpio = 0;
|
|
|
|
#elif CONFIG_ETH_RMII_CLK_OUT_GPIO
|
|
|
|
emac->clock_config.rmii.clock_gpio = CONFIG_ETH_RMII_CLK_OUT_GPIO;
|
|
|
|
#endif // CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
|
2021-07-13 03:09:11 -04:00
|
|
|
#else
|
|
|
|
#error "Unsupported RMII clock mode"
|
|
|
|
#endif
|
2021-06-23 10:23:58 -04:00
|
|
|
} else {
|
2022-01-24 09:40:11 -05:00
|
|
|
emac->clock_config = esp32_emac_config->clock_config;
|
2021-06-23 10:23:58 -04:00
|
|
|
}
|
2021-07-13 03:09:11 -04:00
|
|
|
/* RMII interface GPIO initialization */
|
|
|
|
emac_hal_iomux_init_rmii();
|
|
|
|
/* If ref_clk is configured as input */
|
|
|
|
if (emac->clock_config.rmii.clock_mode == EMAC_CLK_EXT_IN) {
|
|
|
|
ESP_GOTO_ON_FALSE(emac->clock_config.rmii.clock_gpio == EMAC_CLK_IN_GPIO,
|
|
|
|
ESP_ERR_INVALID_ARG, err, TAG, "ESP32 EMAC only support input RMII clock to GPIO0");
|
|
|
|
emac_hal_iomux_rmii_clk_input();
|
|
|
|
emac_ll_clock_enable_rmii_input(emac->hal.ext_regs);
|
|
|
|
} else if (emac->clock_config.rmii.clock_mode == EMAC_CLK_OUT) {
|
|
|
|
ESP_GOTO_ON_FALSE(emac->clock_config.rmii.clock_gpio == EMAC_APPL_CLK_OUT_GPIO ||
|
|
|
|
emac->clock_config.rmii.clock_gpio == EMAC_CLK_OUT_GPIO ||
|
|
|
|
emac->clock_config.rmii.clock_gpio == EMAC_CLK_OUT_180_GPIO,
|
|
|
|
ESP_ERR_INVALID_ARG, err, TAG, "invalid EMAC clock output GPIO");
|
|
|
|
emac_hal_iomux_rmii_clk_ouput(emac->clock_config.rmii.clock_gpio);
|
|
|
|
if (emac->clock_config.rmii.clock_gpio == EMAC_APPL_CLK_OUT_GPIO) {
|
|
|
|
REG_SET_FIELD(PIN_CTRL, CLK_OUT1, 6);
|
|
|
|
}
|
|
|
|
/* Enable RMII clock */
|
|
|
|
emac_ll_clock_enable_rmii_output(emac->hal.ext_regs);
|
2021-12-02 07:24:19 -05:00
|
|
|
// Power up APLL clock
|
|
|
|
periph_rtc_apll_acquire();
|
|
|
|
ESP_GOTO_ON_ERROR(emac_config_apll_clock(), err, TAG, "Configure APLL for RMII failed");
|
|
|
|
emac->use_apll = true;
|
2021-07-13 03:09:11 -04:00
|
|
|
} else {
|
|
|
|
ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid EMAC clock mode");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
2022-01-24 09:40:11 -05:00
|
|
|
ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid EMAC Data Interface:%d", esp32_emac_config->interface);
|
2021-07-13 03:09:11 -04:00
|
|
|
}
|
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-01-24 09:40:11 -05:00
|
|
|
esp_eth_mac_t *esp_eth_mac_new_esp32(const eth_esp32_emac_config_t *esp32_config, const eth_mac_config_t *config)
|
2021-07-13 03:09:11 -04:00
|
|
|
{
|
|
|
|
esp_err_t ret_code = ESP_OK;
|
|
|
|
esp_eth_mac_t *ret = NULL;
|
|
|
|
void *descriptors = NULL;
|
|
|
|
emac_esp32_t *emac = NULL;
|
|
|
|
ESP_GOTO_ON_FALSE(config, NULL, err, TAG, "can't set mac config to null");
|
|
|
|
ret_code = esp_emac_alloc_driver_obj(config, &emac, &descriptors);
|
|
|
|
ESP_GOTO_ON_FALSE(ret_code == ESP_OK, NULL, err, TAG, "alloc driver object failed");
|
|
|
|
|
|
|
|
/* enable APB to access Ethernet peripheral registers */
|
|
|
|
periph_module_enable(PERIPH_EMAC_MODULE);
|
|
|
|
/* initialize hal layer driver */
|
|
|
|
emac_hal_init(&emac->hal, descriptors, emac->rx_buf, emac->tx_buf);
|
|
|
|
/* alloc interrupt */
|
|
|
|
if (config->flags & ETH_MAC_FLAG_WORK_WITH_CACHE_DISABLE) {
|
|
|
|
ret_code = esp_intr_alloc(ETS_ETH_MAC_INTR_SOURCE, ESP_INTR_FLAG_IRAM,
|
|
|
|
emac_isr_default_handler, &emac->hal, &(emac->intr_hdl));
|
|
|
|
} else {
|
|
|
|
ret_code = esp_intr_alloc(ETS_ETH_MAC_INTR_SOURCE, 0,
|
|
|
|
emac_isr_default_handler, &emac->hal, &(emac->intr_hdl));
|
2021-06-23 10:23:58 -04:00
|
|
|
}
|
2021-07-13 03:09:11 -04:00
|
|
|
ESP_GOTO_ON_FALSE(ret_code == ESP_OK, NULL, err, TAG, "alloc emac interrupt failed");
|
2022-01-24 09:40:11 -05:00
|
|
|
ret_code = esp_emac_config_data_interface(esp32_config, emac);
|
2021-07-13 03:09:11 -04:00
|
|
|
ESP_GOTO_ON_FALSE(ret_code == ESP_OK, NULL, err_interf, TAG, "config emac interface failed");
|
|
|
|
|
2022-01-24 09:40:11 -05:00
|
|
|
emac->dma_burst_len = esp32_config->dma_burst_len;
|
2021-07-13 03:09:11 -04:00
|
|
|
emac->sw_reset_timeout_ms = config->sw_reset_timeout_ms;
|
2022-01-24 09:40:11 -05:00
|
|
|
emac->smi_mdc_gpio_num = esp32_config->smi_mdc_gpio_num;
|
|
|
|
emac->smi_mdio_gpio_num = esp32_config->smi_mdio_gpio_num;
|
2020-07-20 08:42:52 -04:00
|
|
|
emac->flow_control_high_water_mark = FLOW_CONTROL_HIGH_WATER_MARK;
|
|
|
|
emac->flow_control_low_water_mark = FLOW_CONTROL_LOW_WATER_MARK;
|
2021-12-02 07:24:19 -05:00
|
|
|
emac->use_apll = false;
|
2019-04-10 04:24:50 -04:00
|
|
|
emac->parent.set_mediator = emac_esp32_set_mediator;
|
|
|
|
emac->parent.init = emac_esp32_init;
|
|
|
|
emac->parent.deinit = emac_esp32_deinit;
|
2020-05-08 09:44:30 -04:00
|
|
|
emac->parent.start = emac_esp32_start;
|
|
|
|
emac->parent.stop = emac_esp32_stop;
|
2019-04-10 04:24:50 -04:00
|
|
|
emac->parent.del = emac_esp32_del;
|
|
|
|
emac->parent.write_phy_reg = emac_esp32_write_phy_reg;
|
|
|
|
emac->parent.read_phy_reg = emac_esp32_read_phy_reg;
|
|
|
|
emac->parent.set_addr = emac_esp32_set_addr;
|
|
|
|
emac->parent.get_addr = emac_esp32_get_addr;
|
|
|
|
emac->parent.set_speed = emac_esp32_set_speed;
|
|
|
|
emac->parent.set_duplex = emac_esp32_set_duplex;
|
|
|
|
emac->parent.set_link = emac_esp32_set_link;
|
|
|
|
emac->parent.set_promiscuous = emac_esp32_set_promiscuous;
|
2020-07-20 08:42:52 -04:00
|
|
|
emac->parent.set_peer_pause_ability = emac_esp32_set_peer_pause_ability;
|
|
|
|
emac->parent.enable_flow_ctrl = emac_esp32_enable_flow_ctrl;
|
2019-04-10 04:24:50 -04:00
|
|
|
emac->parent.transmit = emac_esp32_transmit;
|
2021-12-01 03:53:25 -05:00
|
|
|
emac->parent.transmit_vargs = emac_esp32_transmit_multiple_bufs;
|
2019-04-10 04:24:50 -04:00
|
|
|
emac->parent.receive = emac_esp32_receive;
|
|
|
|
return &(emac->parent);
|
2019-09-18 23:27:42 -04:00
|
|
|
|
2021-07-13 03:09:11 -04:00
|
|
|
err_interf:
|
|
|
|
periph_module_disable(PERIPH_EMAC_MODULE);
|
2019-09-18 23:27:42 -04:00
|
|
|
err:
|
2021-07-13 03:09:11 -04:00
|
|
|
esp_emac_free_driver_obj(emac, descriptors);
|
2019-04-10 04:24:50 -04:00
|
|
|
return ret;
|
|
|
|
}
|