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384 lines
16 KiB
C
384 lines
16 KiB
C
/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** PARL_IO_RX_CFG0_REG register
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* Parallel RX module configuration register0.
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*/
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#define PARL_IO_RX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x0)
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/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [0]; default: 0;
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* Write 0 to select eof generated manchnism by configured data byte length. Write 1
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* to select eof generated manchnism by external enable signal.
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*/
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#define PARL_IO_RX_EOF_GEN_SEL (BIT(0))
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#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
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#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U
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#define PARL_IO_RX_EOF_GEN_SEL_S 0
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/** PARL_IO_RX_START : R/W; bitpos: [1]; default: 0;
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* Write 1 to start rx global data sampling.
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*/
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#define PARL_IO_RX_START (BIT(1))
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#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
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#define PARL_IO_RX_START_V 0x00000001U
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#define PARL_IO_RX_START_S 1
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/** PARL_IO_RX_DATA_BYTELEN : R/W; bitpos: [17:2]; default: 0;
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* Configures rx receieved data byte length.
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*/
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#define PARL_IO_RX_DATA_BYTELEN 0x0000FFFFU
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#define PARL_IO_RX_DATA_BYTELEN_M (PARL_IO_RX_DATA_BYTELEN_V << PARL_IO_RX_DATA_BYTELEN_S)
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#define PARL_IO_RX_DATA_BYTELEN_V 0x0000FFFFU
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#define PARL_IO_RX_DATA_BYTELEN_S 2
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/** PARL_IO_RX_SW_EN : R/W; bitpos: [18]; default: 0;
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* Write 1 to enable software data sampling.
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*/
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#define PARL_IO_RX_SW_EN (BIT(18))
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#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
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#define PARL_IO_RX_SW_EN_V 0x00000001U
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#define PARL_IO_RX_SW_EN_S 18
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/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [22:19]; default: 0;
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* Pulse submode selection.
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* 0000: positive pulse start(data bit included) && positive pulse end(data bit
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* included)
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* 0001: positive pulse start(data bit included) && positive pulse end (data bit
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* excluded)
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* 0010: positive pulse start(data bit excluded) && positive pulse end (data bit
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* included)
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* 0011: positive pulse start(data bit excluded) && positive pulse end (data bit
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* excluded)
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* 0100: positive pulse start(data bit included) && length end
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* 0101: positive pulse start(data bit excluded) && length end
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* 0110: negative pulse start(data bit included) && negative pulse end(data bit
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* included)
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* 0111: negative pulse start(data bit included) && negative pulse end (data bit
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* excluded)
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* 1000: negative pulse start(data bit excluded) && negative pulse end (data bit
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* included)
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* 1001: negative pulse start(data bit excluded) && negative pulse end (data bit
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* excluded)
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* 1010: negative pulse start(data bit included) && length end
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* 1011: negative pulse start(data bit excluded) && length end
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*/
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#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x0000000FU
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#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
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#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x0000000FU
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#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 19
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/** PARL_IO_RX_LEVEL_SUBMODE_SEL : R/W; bitpos: [23]; default: 0;
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* Write 0 to sample data at high level of external enable signal. Write 1 to sample
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* data at low level of external enable signal.
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*/
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#define PARL_IO_RX_LEVEL_SUBMODE_SEL (BIT(23))
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#define PARL_IO_RX_LEVEL_SUBMODE_SEL_M (PARL_IO_RX_LEVEL_SUBMODE_SEL_V << PARL_IO_RX_LEVEL_SUBMODE_SEL_S)
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#define PARL_IO_RX_LEVEL_SUBMODE_SEL_V 0x00000001U
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#define PARL_IO_RX_LEVEL_SUBMODE_SEL_S 23
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/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [25:24]; default: 0;
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* Rx data sampling mode selection.
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* 000: external level enable mode
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* 001: external pulse enable mode
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* 010: internal software enable mode
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*/
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#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U
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#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
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#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U
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#define PARL_IO_RX_SMP_MODE_SEL_S 24
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/** PARL_IO_RX_CLK_EDGE_SEL : R/W; bitpos: [26]; default: 0;
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* Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable
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* sampling data on the falling edge of rx clock.
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*/
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#define PARL_IO_RX_CLK_EDGE_SEL (BIT(26))
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#define PARL_IO_RX_CLK_EDGE_SEL_M (PARL_IO_RX_CLK_EDGE_SEL_V << PARL_IO_RX_CLK_EDGE_SEL_S)
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#define PARL_IO_RX_CLK_EDGE_SEL_V 0x00000001U
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#define PARL_IO_RX_CLK_EDGE_SEL_S 26
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/** PARL_IO_RX_BIT_PACK_ORDER : R/W; bitpos: [27]; default: 0;
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* Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0
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* to pack bits into 1byte from LSB when data bus width is 4/2/1 bits.
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*/
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#define PARL_IO_RX_BIT_PACK_ORDER (BIT(27))
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#define PARL_IO_RX_BIT_PACK_ORDER_M (PARL_IO_RX_BIT_PACK_ORDER_V << PARL_IO_RX_BIT_PACK_ORDER_S)
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#define PARL_IO_RX_BIT_PACK_ORDER_V 0x00000001U
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#define PARL_IO_RX_BIT_PACK_ORDER_S 27
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/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [30:28]; default: 0;
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* Rx data bus width selection.
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* 100: bus width is 1 bit
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* 011: bus width is 2 bits
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* 010: bus width is 4 bits
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* 001: bus width is 8 bits
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* 000: bus width is 16 bits
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*/
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#define PARL_IO_RX_BUS_WID_SEL 0x00000007U
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#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
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#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U
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#define PARL_IO_RX_BUS_WID_SEL_S 28
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/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
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* Write 1 to enable soft reset of async fifo in rx module.
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*/
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#define PARL_IO_RX_FIFO_SRST (BIT(31))
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#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
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#define PARL_IO_RX_FIFO_SRST_V 0x00000001U
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#define PARL_IO_RX_FIFO_SRST_S 31
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/** PARL_IO_RX_CFG1_REG register
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* Parallel RX module configuration register1.
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*/
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#define PARL_IO_RX_CFG1_REG (DR_REG_PARL_IO_BASE + 0x4)
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/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [2]; default: 0;
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* Write 1 to update rx register configuration signals.
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*/
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#define PARL_IO_RX_REG_UPDATE (BIT(2))
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#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
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#define PARL_IO_RX_REG_UPDATE_V 0x00000001U
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#define PARL_IO_RX_REG_UPDATE_S 2
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/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [3]; default: 1;
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* Write 1 to enable timeout count to generate error eof.
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*/
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#define PARL_IO_RX_TIMEOUT_EN (BIT(3))
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#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
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#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U
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#define PARL_IO_RX_TIMEOUT_EN_S 3
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/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [15:12]; default: 15;
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* Configures rx external enable signal selection from 16 data lines.
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*/
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#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU
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#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
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#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU
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#define PARL_IO_RX_EXT_EN_SEL_S 12
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/** PARL_IO_RX_TIMEOUT_THRESHOLD : R/W; bitpos: [31:16]; default: 4095;
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* Configures rx threshold of timeout counter.
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*/
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#define PARL_IO_RX_TIMEOUT_THRESHOLD 0x0000FFFFU
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#define PARL_IO_RX_TIMEOUT_THRESHOLD_M (PARL_IO_RX_TIMEOUT_THRESHOLD_V << PARL_IO_RX_TIMEOUT_THRESHOLD_S)
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#define PARL_IO_RX_TIMEOUT_THRESHOLD_V 0x0000FFFFU
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#define PARL_IO_RX_TIMEOUT_THRESHOLD_S 16
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/** PARL_IO_TX_CFG0_REG register
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* Parallel TX module configuration register0.
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*/
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#define PARL_IO_TX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x8)
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/** PARL_IO_TX_BYTELEN : R/W; bitpos: [17:2]; default: 0;
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* Configures tx sending data byte length.
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*/
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#define PARL_IO_TX_BYTELEN 0x0000FFFFU
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#define PARL_IO_TX_BYTELEN_M (PARL_IO_TX_BYTELEN_V << PARL_IO_TX_BYTELEN_S)
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#define PARL_IO_TX_BYTELEN_V 0x0000FFFFU
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#define PARL_IO_TX_BYTELEN_S 2
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/** PARL_IO_TX_GATING_EN : R/W; bitpos: [18]; default: 0;
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* Write 1 to enable output tx clock gating.
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*/
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#define PARL_IO_TX_GATING_EN (BIT(18))
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#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
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#define PARL_IO_TX_GATING_EN_V 0x00000001U
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#define PARL_IO_TX_GATING_EN_S 18
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/** PARL_IO_TX_START : R/W; bitpos: [19]; default: 0;
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* Write 1 to start tx global data output.
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*/
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#define PARL_IO_TX_START (BIT(19))
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#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
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#define PARL_IO_TX_START_V 0x00000001U
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#define PARL_IO_TX_START_S 19
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/** PARL_IO_TX_HW_VALID_EN : R/W; bitpos: [20]; default: 0;
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* Write 1 to enable tx hardware data valid signal.
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*/
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#define PARL_IO_TX_HW_VALID_EN (BIT(20))
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#define PARL_IO_TX_HW_VALID_EN_M (PARL_IO_TX_HW_VALID_EN_V << PARL_IO_TX_HW_VALID_EN_S)
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#define PARL_IO_TX_HW_VALID_EN_V 0x00000001U
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#define PARL_IO_TX_HW_VALID_EN_S 20
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/** PARL_IO_TX_SMP_EDGE_SEL : R/W; bitpos: [25]; default: 0;
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* Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable
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* sampling data on the falling edge of tx clock.
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*/
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#define PARL_IO_TX_SMP_EDGE_SEL (BIT(25))
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#define PARL_IO_TX_SMP_EDGE_SEL_M (PARL_IO_TX_SMP_EDGE_SEL_V << PARL_IO_TX_SMP_EDGE_SEL_S)
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#define PARL_IO_TX_SMP_EDGE_SEL_V 0x00000001U
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#define PARL_IO_TX_SMP_EDGE_SEL_S 25
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/** PARL_IO_TX_BIT_UNPACK_ORDER : R/W; bitpos: [26]; default: 0;
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* Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write
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* 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits.
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*/
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#define PARL_IO_TX_BIT_UNPACK_ORDER (BIT(26))
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#define PARL_IO_TX_BIT_UNPACK_ORDER_M (PARL_IO_TX_BIT_UNPACK_ORDER_V << PARL_IO_TX_BIT_UNPACK_ORDER_S)
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#define PARL_IO_TX_BIT_UNPACK_ORDER_V 0x00000001U
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#define PARL_IO_TX_BIT_UNPACK_ORDER_S 26
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/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [29:27]; default: 0;
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* Tx data bus width selection.
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* 100: bus width is 1 bit
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* 011: bus width is 2 bits
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* 010: bus width is 4 bits
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* 001: bus width is 8 bits
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* 000: bus width is 16 bits
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*/
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#define PARL_IO_TX_BUS_WID_SEL 0x00000007U
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#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
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#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U
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#define PARL_IO_TX_BUS_WID_SEL_S 27
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/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
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* Write 1 to enable soft reset of async fifo in tx module.
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*/
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#define PARL_IO_TX_FIFO_SRST (BIT(30))
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#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
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#define PARL_IO_TX_FIFO_SRST_V 0x00000001U
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#define PARL_IO_TX_FIFO_SRST_S 30
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/** PARL_IO_TX_CFG1_REG register
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* Parallel TX module configuration register1.
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*/
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#define PARL_IO_TX_CFG1_REG (DR_REG_PARL_IO_BASE + 0xc)
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/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [31:16]; default: 0;
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* Configures data value on tx bus when IDLE state.
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*/
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#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU
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#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
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#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU
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#define PARL_IO_TX_IDLE_VALUE_S 16
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/** PARL_IO_ST_REG register
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* Parallel IO module status register0.
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*/
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#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x10)
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/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
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* Represents the status that tx is ready.
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*/
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#define PARL_IO_TX_READY (BIT(31))
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#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
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#define PARL_IO_TX_READY_V 0x00000001U
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#define PARL_IO_TX_READY_S 31
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/** PARL_IO_INT_ENA_REG register
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* Parallel IO interrupt enable singal configuration register.
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*/
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#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x14)
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/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
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* Write 1 to enable TX_FIFO_REMPTY_INTR.
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*/
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#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0))
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#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
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#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U
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#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0
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/** PARL_IO_RX_FIFO_WFULL_INT_ENA : R/W; bitpos: [1]; default: 0;
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* Write 1 to enable RX_FIFO_WFULL_INTR.
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*/
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#define PARL_IO_RX_FIFO_WFULL_INT_ENA (BIT(1))
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#define PARL_IO_RX_FIFO_WFULL_INT_ENA_M (PARL_IO_RX_FIFO_WFULL_INT_ENA_V << PARL_IO_RX_FIFO_WFULL_INT_ENA_S)
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#define PARL_IO_RX_FIFO_WFULL_INT_ENA_V 0x00000001U
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#define PARL_IO_RX_FIFO_WFULL_INT_ENA_S 1
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/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
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* Write 1 to enable TX_EOF_INTR.
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*/
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#define PARL_IO_TX_EOF_INT_ENA (BIT(2))
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#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
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#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U
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#define PARL_IO_TX_EOF_INT_ENA_S 2
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/** PARL_IO_INT_RAW_REG register
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* Parallel IO interrupt raw singal status register.
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*/
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#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x18)
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/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status of TX_FIFO_REMPTY_INTR.
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*/
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#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0))
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#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
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#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U
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#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0
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/** PARL_IO_RX_FIFO_WFULL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status of RX_FIFO_WFULL_INTR.
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*/
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#define PARL_IO_RX_FIFO_WFULL_INT_RAW (BIT(1))
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#define PARL_IO_RX_FIFO_WFULL_INT_RAW_M (PARL_IO_RX_FIFO_WFULL_INT_RAW_V << PARL_IO_RX_FIFO_WFULL_INT_RAW_S)
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#define PARL_IO_RX_FIFO_WFULL_INT_RAW_V 0x00000001U
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#define PARL_IO_RX_FIFO_WFULL_INT_RAW_S 1
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/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status of TX_EOF_INTR.
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*/
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#define PARL_IO_TX_EOF_INT_RAW (BIT(2))
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#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
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#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U
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#define PARL_IO_TX_EOF_INT_RAW_S 2
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/** PARL_IO_INT_ST_REG register
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* Parallel IO interrupt singal status register.
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*/
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#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x1c)
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/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status of TX_FIFO_REMPTY_INTR.
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*/
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#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0))
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#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
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#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U
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#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0
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/** PARL_IO_RX_FIFO_WFULL_INT_ST : RO; bitpos: [1]; default: 0;
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* The masked interrupt status of RX_FIFO_WFULL_INTR.
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*/
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#define PARL_IO_RX_FIFO_WFULL_INT_ST (BIT(1))
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#define PARL_IO_RX_FIFO_WFULL_INT_ST_M (PARL_IO_RX_FIFO_WFULL_INT_ST_V << PARL_IO_RX_FIFO_WFULL_INT_ST_S)
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#define PARL_IO_RX_FIFO_WFULL_INT_ST_V 0x00000001U
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#define PARL_IO_RX_FIFO_WFULL_INT_ST_S 1
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/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
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* The masked interrupt status of TX_EOF_INTR.
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*/
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#define PARL_IO_TX_EOF_INT_ST (BIT(2))
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#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
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#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U
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#define PARL_IO_TX_EOF_INT_ST_S 2
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/** PARL_IO_INT_CLR_REG register
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* Parallel IO interrupt clear singal configuration register.
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*/
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#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x20)
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/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
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* Write 1 to clear TX_FIFO_REMPTY_INTR.
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*/
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#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0))
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#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
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#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U
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#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0
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/** PARL_IO_RX_FIFO_WFULL_INT_CLR : WT; bitpos: [1]; default: 0;
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* Write 1 to clear RX_FIFO_WFULL_INTR.
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*/
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#define PARL_IO_RX_FIFO_WFULL_INT_CLR (BIT(1))
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#define PARL_IO_RX_FIFO_WFULL_INT_CLR_M (PARL_IO_RX_FIFO_WFULL_INT_CLR_V << PARL_IO_RX_FIFO_WFULL_INT_CLR_S)
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#define PARL_IO_RX_FIFO_WFULL_INT_CLR_V 0x00000001U
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#define PARL_IO_RX_FIFO_WFULL_INT_CLR_S 1
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/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
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* Write 1 to clear TX_EOF_INTR.
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*/
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#define PARL_IO_TX_EOF_INT_CLR (BIT(2))
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#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
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#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U
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#define PARL_IO_TX_EOF_INT_CLR_S 2
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/** PARL_IO_CLK_REG register
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* Parallel IO clk configuration register
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*/
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#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
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/** PARL_IO_CLK_EN : R/W; bitpos: [0]; default: 0;
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* Force clock on for this register file
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*/
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#define PARL_IO_CLK_EN (BIT(0))
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#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
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#define PARL_IO_CLK_EN_V 0x00000001U
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#define PARL_IO_CLK_EN_S 0
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/** PARL_IO_VERSION_REG register
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* Version register.
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*/
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#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
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/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35660352;
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* Version of this register file
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*/
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#define PARL_IO_DATE 0x0FFFFFFFU
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#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S)
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#define PARL_IO_DATE_V 0x0FFFFFFFU
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#define PARL_IO_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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