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esp32c6: add soc/ reg and struct headers

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songruojing 2022-08-15 12:29:17 +08:00 committed by Song Ruo Jing
parent e7dbfd65cb
commit a00f217341
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417
components/soc/esp32c6/include/soc/aes_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* Key material key_0 configure register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* Key material key_1 configure register
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_1 that is a part of key material.
*/
#define AES_KEY_1 0xFFFFFFFFU
#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S)
#define AES_KEY_1_V 0xFFFFFFFFU
#define AES_KEY_1_S 0
/** AES_KEY_2_REG register
* Key material key_2 configure register
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_2 that is a part of key material.
*/
#define AES_KEY_2 0xFFFFFFFFU
#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S)
#define AES_KEY_2_V 0xFFFFFFFFU
#define AES_KEY_2_S 0
/** AES_KEY_3_REG register
* Key material key_3 configure register
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_3 that is a part of key material.
*/
#define AES_KEY_3 0xFFFFFFFFU
#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S)
#define AES_KEY_3_V 0xFFFFFFFFU
#define AES_KEY_3_S 0
/** AES_KEY_4_REG register
* Key material key_4 configure register
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_4 that is a part of key material.
*/
#define AES_KEY_4 0xFFFFFFFFU
#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S)
#define AES_KEY_4_V 0xFFFFFFFFU
#define AES_KEY_4_S 0
/** AES_KEY_5_REG register
* Key material key_5 configure register
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_5 that is a part of key material.
*/
#define AES_KEY_5 0xFFFFFFFFU
#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S)
#define AES_KEY_5_V 0xFFFFFFFFU
#define AES_KEY_5_S 0
/** AES_KEY_6_REG register
* Key material key_6 configure register
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_6 that is a part of key material.
*/
#define AES_KEY_6 0xFFFFFFFFU
#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S)
#define AES_KEY_6_V 0xFFFFFFFFU
#define AES_KEY_6_S 0
/** AES_KEY_7_REG register
* Key material key_7 configure register
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_7 that is a part of key material.
*/
#define AES_KEY_7 0xFFFFFFFFU
#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S)
#define AES_KEY_7_V 0xFFFFFFFFU
#define AES_KEY_7_S 0
/** AES_TEXT_IN_0_REG register
* source text material text_in_0 configure register
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* source text material text_in_1 configure register
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_1 that is a part of source text material.
*/
#define AES_TEXT_IN_1 0xFFFFFFFFU
#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S)
#define AES_TEXT_IN_1_V 0xFFFFFFFFU
#define AES_TEXT_IN_1_S 0
/** AES_TEXT_IN_2_REG register
* source text material text_in_2 configure register
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_2 that is a part of source text material.
*/
#define AES_TEXT_IN_2 0xFFFFFFFFU
#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S)
#define AES_TEXT_IN_2_V 0xFFFFFFFFU
#define AES_TEXT_IN_2_S 0
/** AES_TEXT_IN_3_REG register
* source text material text_in_3 configure register
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_3 that is a part of source text material.
*/
#define AES_TEXT_IN_3 0xFFFFFFFFU
#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S)
#define AES_TEXT_IN_3_V 0xFFFFFFFFU
#define AES_TEXT_IN_3_S 0
/** AES_TEXT_OUT_0_REG register
* result text material text_out_0 configure register
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* result text material text_out_1 configure register
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_1 that is a part of result text material.
*/
#define AES_TEXT_OUT_1 0xFFFFFFFFU
#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S)
#define AES_TEXT_OUT_1_V 0xFFFFFFFFU
#define AES_TEXT_OUT_1_S 0
/** AES_TEXT_OUT_2_REG register
* result text material text_out_2 configure register
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_2 that is a part of result text material.
*/
#define AES_TEXT_OUT_2 0xFFFFFFFFU
#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S)
#define AES_TEXT_OUT_2_V 0xFFFFFFFFU
#define AES_TEXT_OUT_2_S 0
/** AES_TEXT_OUT_3_REG register
* result text material text_out_3 configure register
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_3 that is a part of result text material.
*/
#define AES_TEXT_OUT_3 0xFFFFFFFFU
#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S)
#define AES_TEXT_OUT_3_V 0xFFFFFFFFU
#define AES_TEXT_OUT_3_S 0
/** AES_MODE_REG register
* AES Mode register
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_ENDIAN_REG register
* AES Endian configure register
*/
#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44)
/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0;
* endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out
* endian or out_stream endian
*/
#define AES_ENDIAN 0x0000003FU
#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S)
#define AES_ENDIAN_V 0x0000003FU
#define AES_ENDIAN_S 0
/** AES_TRIGGER_REG register
* AES trigger register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Set this bit to start AES calculation.
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* AES state register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
* idle, 1: busy, 2: calculation_done.
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* DMA-AES working mode register
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* AES cipher block mode register
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* AES block number register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of Plaintext/ciphertext block.
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function configure register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_AAD_BLOCK_NUM_REG register
* Additional Authential Data block number register
*/
#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0)
/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of AAD block.
*/
#define AES_AAD_BLOCK_NUM 0xFFFFFFFFU
#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S)
#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_AAD_BLOCK_NUM_S 0
/** AES_REMAINDER_BIT_NUM_REG register
* AES remainder bit number register
*/
#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4)
/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0;
* Those bits stores the number of remainder bit.
*/
#define AES_REMAINDER_BIT_NUM 0x0000007FU
#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S)
#define AES_REMAINDER_BIT_NUM_V 0x0000007FU
#define AES_REMAINDER_BIT_NUM_S 0
/** AES_CONTINUE_REG register
* AES continue register
*/
#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8)
/** AES_CONTINUE : WT; bitpos: [0]; default: 0;
* Set this bit to continue GCM operation.
*/
#define AES_CONTINUE (BIT(0))
#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S)
#define AES_CONTINUE_V 0x00000001U
#define AES_CONTINUE_S 0
/** AES_INT_CLEAR_REG register
* AES Interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the AES interrupt.
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* AES Interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x3FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x3FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* AES-DMA exit config
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Set this register to leave calculation done stage. Recommend to use it after
* software finishes reading DMA's output buffer.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: key register */
/** Type of key_0 register
* Key material key_0 configure register
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_0_reg_t;
/** Type of key_1 register
* Key material key_1 configure register
*/
typedef union {
struct {
/** key_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_1 that is a part of key material.
*/
uint32_t key_1:32;
};
uint32_t val;
} aes_key_1_reg_t;
/** Type of key_2 register
* Key material key_2 configure register
*/
typedef union {
struct {
/** key_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_2 that is a part of key material.
*/
uint32_t key_2:32;
};
uint32_t val;
} aes_key_2_reg_t;
/** Type of key_3 register
* Key material key_3 configure register
*/
typedef union {
struct {
/** key_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_3 that is a part of key material.
*/
uint32_t key_3:32;
};
uint32_t val;
} aes_key_3_reg_t;
/** Type of key_4 register
* Key material key_4 configure register
*/
typedef union {
struct {
/** key_4 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_4 that is a part of key material.
*/
uint32_t key_4:32;
};
uint32_t val;
} aes_key_4_reg_t;
/** Type of key_5 register
* Key material key_5 configure register
*/
typedef union {
struct {
/** key_5 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_5 that is a part of key material.
*/
uint32_t key_5:32;
};
uint32_t val;
} aes_key_5_reg_t;
/** Type of key_6 register
* Key material key_6 configure register
*/
typedef union {
struct {
/** key_6 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_6 that is a part of key material.
*/
uint32_t key_6:32;
};
uint32_t val;
} aes_key_6_reg_t;
/** Type of key_7 register
* Key material key_7 configure register
*/
typedef union {
struct {
/** key_7 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_7 that is a part of key material.
*/
uint32_t key_7:32;
};
uint32_t val;
} aes_key_7_reg_t;
/** Group: text in register */
/** Type of text_in_0 register
* source text material text_in_0 configure register
*/
typedef union {
struct {
/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
uint32_t text_in_0:32;
};
uint32_t val;
} aes_text_in_0_reg_t;
/** Type of text_in_1 register
* source text material text_in_1 configure register
*/
typedef union {
struct {
/** text_in_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_1 that is a part of source text material.
*/
uint32_t text_in_1:32;
};
uint32_t val;
} aes_text_in_1_reg_t;
/** Type of text_in_2 register
* source text material text_in_2 configure register
*/
typedef union {
struct {
/** text_in_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_2 that is a part of source text material.
*/
uint32_t text_in_2:32;
};
uint32_t val;
} aes_text_in_2_reg_t;
/** Type of text_in_3 register
* source text material text_in_3 configure register
*/
typedef union {
struct {
/** text_in_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_3 that is a part of source text material.
*/
uint32_t text_in_3:32;
};
uint32_t val;
} aes_text_in_3_reg_t;
/** Group: text out register */
/** Type of text_out_0 register
* result text material text_out_0 configure register
*/
typedef union {
struct {
/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
uint32_t text_out_0:32;
};
uint32_t val;
} aes_text_out_0_reg_t;
/** Type of text_out_1 register
* result text material text_out_1 configure register
*/
typedef union {
struct {
/** text_out_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_1 that is a part of result text material.
*/
uint32_t text_out_1:32;
};
uint32_t val;
} aes_text_out_1_reg_t;
/** Type of text_out_2 register
* result text material text_out_2 configure register
*/
typedef union {
struct {
/** text_out_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_2 that is a part of result text material.
*/
uint32_t text_out_2:32;
};
uint32_t val;
} aes_text_out_2_reg_t;
/** Type of text_out_3 register
* result text material text_out_3 configure register
*/
typedef union {
struct {
/** text_out_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_3 that is a part of result text material.
*/
uint32_t text_out_3:32;
};
uint32_t val;
} aes_text_out_3_reg_t;
/** Group: Configuration register */
/** Type of mode register
* AES Mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_mode_reg_t;
/** Type of endian register
* AES Endian configure register
*/
typedef union {
struct {
/** endian : R/W; bitpos: [5:0]; default: 0;
* endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out
* endian or out_stream endian
*/
uint32_t endian:6;
uint32_t reserved_6:26;
};
uint32_t val;
} aes_endian_reg_t;
/** Type of block_mode register
* AES cipher block mode register
*/
typedef union {
struct {
/** block_mode : R/W; bitpos: [2:0]; default: 0;
* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
*/
uint32_t block_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_block_mode_reg_t;
/** Type of block_num register
* AES block number register
*/
typedef union {
struct {
/** block_num : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of Plaintext/ciphertext block.
*/
uint32_t block_num:32;
};
uint32_t val;
} aes_block_num_reg_t;
/** Type of inc_sel register
* Standard incrementing function configure register
*/
typedef union {
struct {
/** inc_sel : R/W; bitpos: [0]; default: 0;
* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
*/
uint32_t inc_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_inc_sel_reg_t;
/** Type of aad_block_num register
* Additional Authential Data block number register
*/
typedef union {
struct {
/** aad_block_num : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of AAD block.
*/
uint32_t aad_block_num:32;
};
uint32_t val;
} aes_aad_block_num_reg_t;
/** Type of remainder_bit_num register
* AES remainder bit number register
*/
typedef union {
struct {
/** remainder_bit_num : R/W; bitpos: [6:0]; default: 0;
* Those bits stores the number of remainder bit.
*/
uint32_t remainder_bit_num:7;
uint32_t reserved_7:25;
};
uint32_t val;
} aes_remainder_bit_num_reg_t;
/** Group: Control/Status register */
/** Type of trigger register
* AES trigger register
*/
typedef union {
struct {
/** trigger : WT; bitpos: [0]; default: 0;
* Set this bit to start AES calculation.
*/
uint32_t trigger:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_trigger_reg_t;
/** Type of state register
* AES state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
* idle, 1: busy, 2: calculation_done.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} aes_state_reg_t;
/** Type of dma_enable register
* DMA-AES working mode register
*/
typedef union {
struct {
/** dma_enable : R/W; bitpos: [0]; default: 0;
* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
*/
uint32_t dma_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of continue register
* AES continue register
*/
typedef union {
struct {
/** conti : WT; bitpos: [0]; default: 0;
* Set this bit to continue GCM operation.
*/
uint32_t conti:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_continue_reg_t;
/** Type of dma_exit register
* AES-DMA exit config
*/
typedef union {
struct {
/** dma_exit : WT; bitpos: [0]; default: 0;
* Set this register to leave calculation done stage. Recommend to use it after
* software finishes reading DMA's output buffer.
*/
uint32_t dma_exit:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_exit_reg_t;
/** Group: memory type */
/** Group: interrupt register */
/** Type of int_clear register
* AES Interrupt clear register
*/
typedef union {
struct {
/** int_clear : WT; bitpos: [0]; default: 0;
* Set this bit to clear the AES interrupt.
*/
uint32_t int_clear:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_clear_reg_t;
/** Type of int_ena register
* AES Interrupt enable register
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_ena_reg_t;
/** Group: Version control register */
/** Type of date register
* AES version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538513936;
* This bits stores the version information of AES.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} aes_date_reg_t;
typedef struct aes_dev_t {
volatile aes_key_0_reg_t key_0;
volatile aes_key_1_reg_t key_1;
volatile aes_key_2_reg_t key_2;
volatile aes_key_3_reg_t key_3;
volatile aes_key_4_reg_t key_4;
volatile aes_key_5_reg_t key_5;
volatile aes_key_6_reg_t key_6;
volatile aes_key_7_reg_t key_7;
volatile aes_text_in_0_reg_t text_in_0;
volatile aes_text_in_1_reg_t text_in_1;
volatile aes_text_in_2_reg_t text_in_2;
volatile aes_text_in_3_reg_t text_in_3;
volatile aes_text_out_0_reg_t text_out_0;
volatile aes_text_out_1_reg_t text_out_1;
volatile aes_text_out_2_reg_t text_out_2;
volatile aes_text_out_3_reg_t text_out_3;
volatile aes_mode_reg_t mode;
volatile aes_endian_reg_t endian;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
volatile uint32_t h[4];
volatile uint32_t j0[4];
volatile uint32_t t0[4];
volatile aes_dma_enable_reg_t dma_enable;
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
volatile aes_aad_block_num_reg_t aad_block_num;
volatile aes_remainder_bit_num_reg_t remainder_bit_num;
volatile aes_continue_reg_t conti;
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
volatile aes_dma_exit_reg_t dma_exit;
} aes_dev_t;
extern aes_dev_t AES;
#ifndef __cplusplus
_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/apb_saradc_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** APB_SARADC_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
#define APB_SARADC_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U
#define APB_SARADC_SARADC_START_FORCE_S 0
/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
#define APB_SARADC_SARADC_START (BIT(1))
#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
#define APB_SARADC_SARADC_START_V 0x00000001U
#define APB_SARADC_SARADC_START_S 1
/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U
#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6
/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7
/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15
/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23
/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27
/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29))
#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U
#define APB_SARADC_SARADC2_PWDET_DRV_S 29
/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30
/** APB_SARADC_CTRL2_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0
/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1
/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR1_INV_S 9
/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR2_INV_S 10
/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_S 12
/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define APB_SARADC_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U
#define APB_SARADC_SARADC_TIMER_EN_S 24
/** APB_SARADC_FILTER_CTRL1_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26
/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29
/** APB_SARADC_FSM_WAIT_REG register
* digital saradc configure register
*/
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc)
/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8;
* saradc_xpd_wait
*/
#define APB_SARADC_SARADC_XPD_WAIT 0x000000FFU
#define APB_SARADC_SARADC_XPD_WAIT_M (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S)
#define APB_SARADC_SARADC_XPD_WAIT_V 0x000000FFU
#define APB_SARADC_SARADC_XPD_WAIT_S 0
/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8;
* saradc_rstb_wait
*/
#define APB_SARADC_SARADC_RSTB_WAIT 0x000000FFU
#define APB_SARADC_SARADC_RSTB_WAIT_M (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S)
#define APB_SARADC_SARADC_RSTB_WAIT_V 0x000000FFU
#define APB_SARADC_SARADC_RSTB_WAIT_S 8
/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255;
* saradc_standby_wait
*/
#define APB_SARADC_SARADC_STANDBY_WAIT 0x000000FFU
#define APB_SARADC_SARADC_STANDBY_WAIT_M (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S)
#define APB_SARADC_SARADC_STANDBY_WAIT_V 0x000000FFU
#define APB_SARADC_SARADC_STANDBY_WAIT_S 16
/** APB_SARADC_SAR1_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912;
* saradc1 status about data and channel
*/
#define APB_SARADC_SARADC_SAR1_STATUS 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR1_STATUS_M (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S)
#define APB_SARADC_SARADC_SAR1_STATUS_V 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR1_STATUS_S 0
/** APB_SARADC_SAR2_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912;
* saradc2 status about data and channel
*/
#define APB_SARADC_SARADC_SAR2_STATUS 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR2_STATUS_M (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S)
#define APB_SARADC_SARADC_SAR2_STATUS_V 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR2_STATUS_S 0
/** APB_SARADC_SAR_PATT_TAB1_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0
/** APB_SARADC_SAR_PATT_TAB2_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0
/** APB_SARADC_ONETIME_SAMPLE_REG register
* digital saradc configure register
*/
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23
/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25
/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
#define APB_SARADC_SARADC_ONETIME_START (BIT(29))
#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U
#define APB_SARADC_SARADC_ONETIME_START_S 29
/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30))
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30
/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31))
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31
/** APB_SARADC_ARB_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/** APB_SARADC_FILTER_CTRL0_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28)
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22
/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31))
#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U
#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31
/** APB_SARADC_SAR1DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c)
/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_S 0
/** APB_SARADC_SAR2DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30)
/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_S 0
/** APB_SARADC_THRES0_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34)
/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18
/** APB_SARADC_THRES1_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18
/** APB_SARADC_THRES_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c)
/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27
/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30))
#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_EN_S 30
/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31))
#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_EN_S 31
/** APB_SARADC_INT_ENA_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40)
/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31
/** APB_SARADC_INT_RAW_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44)
/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31
/** APB_SARADC_INT_ST_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48)
/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31
/** APB_SARADC_INT_CLR_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c)
/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31
/** APB_SARADC_DMA_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50)
/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U
#define APB_SARADC_APB_ADC_TRANS_S 31
/** APB_SARADC_CLKM_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54)
/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_S 0
/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
#define APB_SARADC_CLKM_DIV_B 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_S 8
/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
#define APB_SARADC_CLKM_DIV_A 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_S 14
/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
#define APB_SARADC_CLK_EN_V 0x00000001U
#define APB_SARADC_CLK_EN_S 20
/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
#define APB_SARADC_CLK_SEL 0x00000003U
#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
#define APB_SARADC_CLK_SEL_V 0x00000003U
#define APB_SARADC_CLK_SEL_S 21
/** APB_SARADC_APB_TSENS_CTRL_REG register
* digital tsens configure register
*/
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
#define APB_SARADC_TSENS_OUT 0x000000FFU
#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
#define APB_SARADC_TSENS_OUT_V 0x000000FFU
#define APB_SARADC_TSENS_OUT_S 0
/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
#define APB_SARADC_TSENS_IN_INV (BIT(13))
#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
#define APB_SARADC_TSENS_IN_INV_V 0x00000001U
#define APB_SARADC_TSENS_IN_INV_S 13
/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_S 14
/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
#define APB_SARADC_TSENS_PU (BIT(22))
#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
#define APB_SARADC_TSENS_PU_V 0x00000001U
#define APB_SARADC_TSENS_PU_S 22
/** APB_SARADC_TSENS_CTRL2_REG register
* digital tsens configure register
*/
#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c)
/** APB_SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2;
* the time that power up tsens need wait
*/
#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFFU
#define APB_SARADC_TSENS_XPD_WAIT_M (APB_SARADC_TSENS_XPD_WAIT_V << APB_SARADC_TSENS_XPD_WAIT_S)
#define APB_SARADC_TSENS_XPD_WAIT_V 0x00000FFFU
#define APB_SARADC_TSENS_XPD_WAIT_S 0
/** APB_SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0;
* force power up tsens
*/
#define APB_SARADC_TSENS_XPD_FORCE 0x00000003U
#define APB_SARADC_TSENS_XPD_FORCE_M (APB_SARADC_TSENS_XPD_FORCE_V << APB_SARADC_TSENS_XPD_FORCE_S)
#define APB_SARADC_TSENS_XPD_FORCE_V 0x00000003U
#define APB_SARADC_TSENS_XPD_FORCE_S 12
/** APB_SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1;
* inv tsens clk
*/
#define APB_SARADC_TSENS_CLK_INV (BIT(14))
#define APB_SARADC_TSENS_CLK_INV_M (APB_SARADC_TSENS_CLK_INV_V << APB_SARADC_TSENS_CLK_INV_S)
#define APB_SARADC_TSENS_CLK_INV_V 0x00000001U
#define APB_SARADC_TSENS_CLK_INV_S 14
/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U
#define APB_SARADC_TSENS_CLK_SEL_S 15
/** APB_SARADC_CALI_REG register
* digital saradc configure register
*/
#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60)
/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_S 0
/** APB_TSENS_WAKE_REG register
* digital tsens configure register
*/
#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64)
/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_S 0
/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_S 8
/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16))
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16
/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
#define APB_SARADC_WAKEUP_MODE (BIT(17))
#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
#define APB_SARADC_WAKEUP_MODE_V 0x00000001U
#define APB_SARADC_WAKEUP_MODE_S 17
/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
#define APB_SARADC_WAKEUP_EN (BIT(18))
#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
#define APB_SARADC_WAKEUP_EN_V 0x00000001U
#define APB_SARADC_WAKEUP_EN_S 18
/** APB_TSENS_SAMPLE_REG register
* digital tsens configure register
*/
#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68)
/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_S 0
/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16))
#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U
#define APB_SARADC_TSENS_SAMPLE_EN_S 16
/** APB_SARADC_CTRL_DATE_REG register
* version
*/
#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
#define APB_SARADC_DATE 0xFFFFFFFFU
#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
#define APB_SARADC_DATE_V 0xFFFFFFFFU
#define APB_SARADC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of saradc_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
uint32_t saradc_saradc_start_force:1;
/** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
uint32_t saradc_saradc_start:1;
uint32_t reserved_2:4;
/** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
uint32_t saradc_saradc_sar_clk_gated:1;
/** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
uint32_t saradc_saradc_sar_clk_div:8;
/** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t saradc_saradc_sar_patt_len:3;
uint32_t reserved_18:5;
/** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t saradc_saradc_sar_patt_p_clear:1;
uint32_t reserved_24:3;
/** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
uint32_t saradc_saradc_xpd_sar_force:2;
/** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
uint32_t saradc_saradc2_pwdet_drv:1;
/** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
uint32_t saradc_saradc_wait_arb_cycle:2;
};
uint32_t val;
} apb_saradc_ctrl_reg_t;
/** Type of saradc_ctrl2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
uint32_t saradc_saradc_meas_num_limit:1;
/** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
uint32_t saradc_saradc_max_meas_num:8;
/** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar1_inv:1;
/** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar2_inv:1;
uint32_t reserved_11:1;
/** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t saradc_saradc_timer_target:12;
/** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t saradc_saradc_timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} apb_saradc_ctrl2_reg_t;
/** Type of saradc_filter_ctrl1 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
uint32_t saradc_apb_saradc_filter_factor1:3;
/** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
uint32_t saradc_apb_saradc_filter_factor0:3;
};
uint32_t val;
} apb_saradc_filter_ctrl1_reg_t;
/** Type of saradc_fsm_wait register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8;
* saradc_xpd_wait
*/
uint32_t saradc_saradc_xpd_wait:8;
/** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8;
* saradc_rstb_wait
*/
uint32_t saradc_saradc_rstb_wait:8;
/** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255;
* saradc_standby_wait
*/
uint32_t saradc_saradc_standby_wait:8;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_fsm_wait_reg_t;
/** Type of saradc_sar1_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912;
* saradc1 status about data and channel
*/
uint32_t saradc_saradc_sar1_status:32;
};
uint32_t val;
} apb_saradc_sar1_status_reg_t;
/** Type of saradc_sar2_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912;
* saradc2 status about data and channel
*/
uint32_t saradc_saradc_sar2_status:32;
};
uint32_t val;
} apb_saradc_sar2_status_reg_t;
/** Type of saradc_sar_patt_tab1 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab1_reg_t;
/** Type of saradc_sar_patt_tab2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab2_reg_t;
/** Type of saradc_onetime_sample register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
uint32_t saradc_saradc_onetime_atten:2;
/** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
uint32_t saradc_saradc_onetime_channel:4;
/** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
uint32_t saradc_saradc_onetime_start:1;
/** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
uint32_t saradc_saradc2_onetime_sample:1;
/** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
uint32_t saradc_saradc1_onetime_sample:1;
};
uint32_t val;
} apb_saradc_onetime_sample_reg_t;
/** Type of saradc_arb_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
uint32_t saradc_adc_arb_apb_force:1;
/** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
uint32_t saradc_adc_arb_rtc_force:1;
/** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
uint32_t saradc_adc_arb_wifi_force:1;
/** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
uint32_t saradc_adc_arb_grant_force:1;
/** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
uint32_t saradc_adc_arb_apb_priority:2;
/** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
uint32_t saradc_adc_arb_rtc_priority:2;
/** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
uint32_t saradc_adc_arb_wifi_priority:2;
/** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
uint32_t saradc_adc_arb_fix_priority:1;
uint32_t reserved_13:19;
};
uint32_t val;
} apb_saradc_arb_ctrl_reg_t;
/** Type of saradc_filter_ctrl0 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:18;
/** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel1:4;
/** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel0:4;
uint32_t reserved_26:5;
/** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t saradc_apb_saradc_filter_reset:1;
};
uint32_t val;
} apb_saradc_filter_ctrl0_reg_t;
/** Type of saradc_sar1data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
uint32_t saradc_apb_saradc1_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar1data_status_reg_t;
/** Type of saradc_sar2data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
uint32_t saradc_apb_saradc2_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar2data_status_reg_t;
/** Type of saradc_thres0_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
uint32_t saradc_apb_saradc_thres0_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_high:13;
/** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres0_ctrl_reg_t;
/** Type of saradc_thres1_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
uint32_t saradc_apb_saradc_thres1_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_high:13;
/** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres1_ctrl_reg_t;
/** Type of saradc_thres_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
uint32_t saradc_apb_saradc_thres_all_en:1;
uint32_t reserved_28:2;
/** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
uint32_t saradc_apb_saradc_thres1_en:1;
/** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
uint32_t saradc_apb_saradc_thres0_en:1;
};
uint32_t val;
} apb_saradc_thres_ctrl_reg_t;
/** Type of saradc_int_ena register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
uint32_t saradc_apb_saradc_tsens_int_ena:1;
/** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
/** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
/** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
/** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
/** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
uint32_t saradc_apb_saradc2_done_int_ena:1;
/** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
uint32_t saradc_apb_saradc1_done_int_ena:1;
};
uint32_t val;
} apb_saradc_int_ena_reg_t;
/** Type of saradc_int_raw register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
uint32_t saradc_apb_saradc_tsens_int_raw:1;
/** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
/** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
/** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
/** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
/** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
uint32_t saradc_apb_saradc2_done_int_raw:1;
/** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
uint32_t saradc_apb_saradc1_done_int_raw:1;
};
uint32_t val;
} apb_saradc_int_raw_reg_t;
/** Type of saradc_int_st register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
uint32_t saradc_apb_saradc_tsens_int_st:1;
/** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
uint32_t saradc_apb_saradc_thres1_low_int_st:1;
/** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
uint32_t saradc_apb_saradc_thres0_low_int_st:1;
/** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
uint32_t saradc_apb_saradc_thres1_high_int_st:1;
/** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
uint32_t saradc_apb_saradc_thres0_high_int_st:1;
/** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
uint32_t saradc_apb_saradc2_done_int_st:1;
/** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
uint32_t saradc_apb_saradc1_done_int_st:1;
};
uint32_t val;
} apb_saradc_int_st_reg_t;
/** Type of saradc_int_clr register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
uint32_t saradc_apb_saradc_tsens_int_clr:1;
/** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
/** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
/** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
/** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
/** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
uint32_t saradc_apb_saradc2_done_int_clr:1;
/** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
uint32_t saradc_apb_saradc1_done_int_clr:1;
};
uint32_t val;
} apb_saradc_int_clr_reg_t;
/** Type of saradc_dma_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t saradc_apb_adc_eof_num:16;
uint32_t reserved_16:14;
/** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
uint32_t saradc_apb_adc_reset_fsm:1;
/** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t saradc_apb_adc_trans:1;
};
uint32_t val;
} apb_saradc_dma_conf_reg_t;
/** Type of saradc_clkm_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
uint32_t saradc_clkm_div_num:8;
/** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
uint32_t saradc_clkm_div_b:6;
/** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
uint32_t saradc_clkm_div_a:6;
/** saradc_clk_en : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
uint32_t saradc_clk_en:1;
/** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
uint32_t saradc_clk_sel:2;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_clkm_conf_reg_t;
/** Type of saradc_apb_tsens_ctrl register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
uint32_t saradc_tsens_out:8;
uint32_t reserved_8:5;
/** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
uint32_t saradc_tsens_in_inv:1;
/** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
uint32_t saradc_tsens_clk_div:8;
/** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
uint32_t saradc_tsens_pu:1;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_apb_tsens_ctrl_reg_t;
/** Type of saradc_tsens_ctrl2 register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2;
* the time that power up tsens need wait
*/
uint32_t saradc_tsens_xpd_wait:12;
/** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0;
* force power up tsens
*/
uint32_t saradc_tsens_xpd_force:2;
/** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1;
* inv tsens clk
*/
uint32_t saradc_tsens_clk_inv:1;
/** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
uint32_t saradc_tsens_clk_sel:1;
uint32_t reserved_16:16;
};
uint32_t val;
} apb_saradc_tsens_ctrl2_reg_t;
/** Type of saradc_cali register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
uint32_t saradc_apb_saradc_cali_cfg:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_cali_reg_t;
/** Type of tsens_wake register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
uint32_t saradc_wakeup_th_low:8;
/** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
uint32_t saradc_wakeup_th_high:8;
/** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
uint32_t saradc_wakeup_over_upper_th:1;
/** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
uint32_t saradc_wakeup_mode:1;
/** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
uint32_t saradc_wakeup_en:1;
uint32_t reserved_19:13;
};
uint32_t val;
} apb_tsens_wake_reg_t;
/** Type of tsens_sample register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
uint32_t saradc_tsens_sample_rate:16;
/** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
uint32_t saradc_tsens_sample_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_tsens_sample_reg_t;
/** Type of saradc_ctrl_date register
* version
*/
typedef union {
struct {
/** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
uint32_t saradc_date:32;
};
uint32_t val;
} apb_saradc_ctrl_date_reg_t;
typedef struct apb_dev_t {
volatile apb_saradc_ctrl_reg_t saradc_ctrl;
volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait;
volatile apb_saradc_sar1_status_reg_t saradc_sar1_status;
volatile apb_saradc_sar2_status_reg_t saradc_sar2_status;
volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
volatile apb_saradc_int_ena_reg_t saradc_int_ena;
volatile apb_saradc_int_raw_reg_t saradc_int_raw;
volatile apb_saradc_int_st_reg_t saradc_int_st;
volatile apb_saradc_int_clr_reg_t saradc_int_clr;
volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
volatile apb_saradc_cali_reg_t saradc_cali;
volatile apb_tsens_wake_reg_t tsens_wake;
volatile apb_tsens_sample_reg_t tsens_sample;
uint32_t reserved_06c[228];
volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
} apb_dev_t;
extern apb_dev_t APB_SARADC;
#ifndef __cplusplus
_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
* core0 monitor enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor enable
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor enbale
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11
/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
* core0 monitor interrupt status register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
* DBUS busy monitor initerrupt status
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11
/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
* core0 monitor interrupt enable register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt enbale
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
* core0 monitor interrupt clr register
*/
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
* core0 dram0 region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region0 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
* core0 dram0 region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region0 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
* core0 dram0 region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region1 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
* core0 dram0 region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region1 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
* core0 PIF region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region0 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
* core0 PIF region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region0 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
* core0 PIF region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region1 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
* core0 PIF region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region1 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
* core0 area pc status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
* the stackpointer when first touch region monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
* core0 area sp status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
* the PC when first touch region monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
* stack min value
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
* core0 sp region configuration regsiter
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
* stack max value
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
* core0 sp pc status register
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
* stack monitor pc status register
*/
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
* This regsiter stores the PC when trigger stack monitor.
*/
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
* record enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
* Set 1 to enable record PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
* record status regsiter
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
* recorded PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
* record status regsiter
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
* recorded sp
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
* reg_core_0_iram0_recording_wr_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
* reg_core_0_iram0_recording_loadstore_0
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
* reg_core_0_iram0_recording_wr_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
* reg_core_0_iram0_recording_loadstore_1
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register2
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
* reg_core_0_dram0_recording_wr_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0;
* reg_core_0_dram0_recording_byteen_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register3
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_0
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
* exception monitor status register4
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
* reg_core_0_dram0_recording_wr_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0;
* reg_core_0_dram0_recording_byteen_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
* exception monitor status register5
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_1
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
* exception monitor status register6
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_0
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
* exception monitor status register7
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_1
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
* cpu's lastpc before exception
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
* cpu debug mode status, 1 means cpu enter debug mode.
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
* cpu debug_module active status
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
/** ASSIST_DEBUG_CLOCK_GATE_REG register
* clock register
*/
#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Set 1 force on the clock gate
*/
#define ASSIST_DEBUG_CLK_EN (BIT(0))
#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
#define ASSIST_DEBUG_CLK_EN_V 0x00000001U
#define ASSIST_DEBUG_CLK_EN_S 0
/** ASSIST_DEBUG_DATE_REG register
* version register
*/
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
* version register
*/
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE 0x0FFFFFFFU
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/assist_debug_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: monitor configuration registers */
/** Type of core_0_intr_ena register
* core0 monitor enable configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor enable
*/
uint32_t core_0_area_dram0_0_rd_ena:1;
/** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor enable
*/
uint32_t core_0_area_dram0_0_wr_ena:1;
/** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor enable
*/
uint32_t core_0_area_dram0_1_rd_ena:1;
/** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor enable
*/
uint32_t core_0_area_dram0_1_wr_ena:1;
/** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor enable
*/
uint32_t core_0_area_pif_0_rd_ena:1;
/** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor enable
*/
uint32_t core_0_area_pif_0_wr_ena:1;
/** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor enable
*/
uint32_t core_0_area_pif_1_rd_ena:1;
/** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor enable
*/
uint32_t core_0_area_pif_1_wr_ena:1;
/** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor enable
*/
uint32_t core_0_sp_spill_min_ena:1;
/** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor enable
*/
uint32_t core_0_sp_spill_max_ena:1;
/** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor enable
*/
uint32_t core_0_iram0_exception_monitor_ena:1;
/** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor enbale
*/
uint32_t core_0_dram0_exception_monitor_ena:1;
uint32_t reserved_12:20;
};
uint32_t val;
} assist_debug_core_0_intr_ena_reg_t;
/** Type of core_0_area_dram0_0_min register
* core0 dram0 region0 addr configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region0 start addr
*/
uint32_t core_0_area_dram0_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_min_reg_t;
/** Type of core_0_area_dram0_0_max register
* core0 dram0 region0 addr configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region0 end addr
*/
uint32_t core_0_area_dram0_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_max_reg_t;
/** Type of core_0_area_dram0_1_min register
* core0 dram0 region1 addr configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region1 start addr
*/
uint32_t core_0_area_dram0_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_min_reg_t;
/** Type of core_0_area_dram0_1_max register
* core0 dram0 region1 addr configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region1 end addr
*/
uint32_t core_0_area_dram0_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_max_reg_t;
/** Type of core_0_area_pif_0_min register
* core0 PIF region0 addr configuration register
*/
typedef union {
struct {
/** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region0 start addr
*/
uint32_t core_0_area_pif_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_min_reg_t;
/** Type of core_0_area_pif_0_max register
* core0 PIF region0 addr configuration register
*/
typedef union {
struct {
/** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region0 end addr
*/
uint32_t core_0_area_pif_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_max_reg_t;
/** Type of core_0_area_pif_1_min register
* core0 PIF region1 addr configuration register
*/
typedef union {
struct {
/** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region1 start addr
*/
uint32_t core_0_area_pif_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_min_reg_t;
/** Type of core_0_area_pif_1_max register
* core0 PIF region1 addr configuration register
*/
typedef union {
struct {
/** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region1 end addr
*/
uint32_t core_0_area_pif_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_max_reg_t;
/** Type of core_0_area_pc register
* core0 area pc status register
*/
typedef union {
struct {
/** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
* the stackpointer when first touch region monitor interrupt
*/
uint32_t core_0_area_pc:32;
};
uint32_t val;
} assist_debug_core_0_area_pc_reg_t;
/** Type of core_0_area_sp register
* core0 area sp status register
*/
typedef union {
struct {
/** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
* the PC when first touch region monitor interrupt
*/
uint32_t core_0_area_sp:32;
};
uint32_t val;
} assist_debug_core_0_area_sp_reg_t;
/** Type of core_0_sp_min register
* stack min value
*/
typedef union {
struct {
/** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
* core0 sp region configuration regsiter
*/
uint32_t core_0_sp_min:32;
};
uint32_t val;
} assist_debug_core_0_sp_min_reg_t;
/** Type of core_0_sp_max register
* stack max value
*/
typedef union {
struct {
/** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
* core0 sp pc status register
*/
uint32_t core_0_sp_max:32;
};
uint32_t val;
} assist_debug_core_0_sp_max_reg_t;
/** Type of core_0_sp_pc register
* stack monitor pc status register
*/
typedef union {
struct {
/** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
* This regsiter stores the PC when trigger stack monitor.
*/
uint32_t core_0_sp_pc:32;
};
uint32_t val;
} assist_debug_core_0_sp_pc_reg_t;
/** Group: interrupt configuration register */
/** Type of core_0_intr_raw register
* core0 monitor interrupt status register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt status
*/
uint32_t core_0_area_dram0_0_rd_raw:1;
/** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt status
*/
uint32_t core_0_area_dram0_0_wr_raw:1;
/** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt status
*/
uint32_t core_0_area_dram0_1_rd_raw:1;
/** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt status
*/
uint32_t core_0_area_dram0_1_wr_raw:1;
/** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt status
*/
uint32_t core_0_area_pif_0_rd_raw:1;
/** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt status
*/
uint32_t core_0_area_pif_0_wr_raw:1;
/** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt status
*/
uint32_t core_0_area_pif_1_rd_raw:1;
/** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt status
*/
uint32_t core_0_area_pif_1_wr_raw:1;
/** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt status
*/
uint32_t core_0_sp_spill_min_raw:1;
/** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt status
*/
uint32_t core_0_sp_spill_max_raw:1;
/** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt status
*/
uint32_t core_0_iram0_exception_monitor_raw:1;
/** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
* DBUS busy monitor initerrupt status
*/
uint32_t core_0_dram0_exception_monitor_raw:1;
uint32_t reserved_12:20;
};
uint32_t val;
} assist_debug_core_0_intr_raw_reg_t;
/** Type of core_0_intr_rls register
* core0 monitor interrupt enable register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
uint32_t core_0_area_dram0_0_rd_rls:1;
/** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
uint32_t core_0_area_dram0_0_wr_rls:1;
/** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
uint32_t core_0_area_dram0_1_rd_rls:1;
/** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
uint32_t core_0_area_dram0_1_wr_rls:1;
/** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
uint32_t core_0_area_pif_0_rd_rls:1;
/** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
uint32_t core_0_area_pif_0_wr_rls:1;
/** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
uint32_t core_0_area_pif_1_rd_rls:1;
/** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
uint32_t core_0_area_pif_1_wr_rls:1;
/** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
uint32_t core_0_sp_spill_min_rls:1;
/** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
uint32_t core_0_sp_spill_max_rls:1;
/** core_0_iram0_exception_monitor_rls : R/W; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt enable
*/
uint32_t core_0_iram0_exception_monitor_rls:1;
/** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt enbale
*/
uint32_t core_0_dram0_exception_monitor_rls:1;
uint32_t reserved_12:20;
};
uint32_t val;
} assist_debug_core_0_intr_rls_reg_t;
/** Type of core_0_intr_clr register
* core0 monitor interrupt clr register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt clr
*/
uint32_t core_0_area_dram0_0_rd_clr:1;
/** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt clr
*/
uint32_t core_0_area_dram0_0_wr_clr:1;
/** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt clr
*/
uint32_t core_0_area_dram0_1_rd_clr:1;
/** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt clr
*/
uint32_t core_0_area_dram0_1_wr_clr:1;
/** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt clr
*/
uint32_t core_0_area_pif_0_rd_clr:1;
/** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt clr
*/
uint32_t core_0_area_pif_0_wr_clr:1;
/** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt clr
*/
uint32_t core_0_area_pif_1_rd_clr:1;
/** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt clr
*/
uint32_t core_0_area_pif_1_wr_clr:1;
/** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt clr
*/
uint32_t core_0_sp_spill_min_clr:1;
/** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt clr
*/
uint32_t core_0_sp_spill_max_clr:1;
/** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
* IBUS busy monitor interrupt clr
*/
uint32_t core_0_iram0_exception_monitor_clr:1;
/** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
* DBUS busy monitor interrupt clr
*/
uint32_t core_0_dram0_exception_monitor_clr:1;
uint32_t reserved_12:20;
};
uint32_t val;
} assist_debug_core_0_intr_clr_reg_t;
/** Group: pc reording configuration register */
/** Type of core_0_rcd_en register
* record enable configuration register
*/
typedef union {
struct {
/** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
* Set 1 to enable record PC
*/
uint32_t core_0_rcd_recorden:1;
/** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
*/
uint32_t core_0_rcd_pdebugen:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_rcd_en_reg_t;
/** Group: pc reording status register */
/** Type of core_0_rcd_pdebugpc register
* record status regsiter
*/
typedef union {
struct {
/** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
* recorded PC
*/
uint32_t core_0_rcd_pdebugpc:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugpc_reg_t;
/** Type of core_0_rcd_pdebugsp register
* record status regsiter
*/
typedef union {
struct {
/** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
* recorded sp
*/
uint32_t core_0_rcd_pdebugsp:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugsp_reg_t;
/** Group: exception monitor regsiter */
/** Type of core_0_iram0_exception_monitor_0 register
* exception monitor status register0
*/
typedef union {
struct {
/** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_0
*/
uint32_t core_0_iram0_recording_addr_0:24;
/** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
* reg_core_0_iram0_recording_wr_0
*/
uint32_t core_0_iram0_recording_wr_0:1;
/** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
* reg_core_0_iram0_recording_loadstore_0
*/
uint32_t core_0_iram0_recording_loadstore_0:1;
uint32_t reserved_26:6;
};
uint32_t val;
} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
/** Type of core_0_iram0_exception_monitor_1 register
* exception monitor status register1
*/
typedef union {
struct {
/** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_iram0_recording_addr_1
*/
uint32_t core_0_iram0_recording_addr_1:24;
/** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
* reg_core_0_iram0_recording_wr_1
*/
uint32_t core_0_iram0_recording_wr_1:1;
/** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
* reg_core_0_iram0_recording_loadstore_1
*/
uint32_t core_0_iram0_recording_loadstore_1:1;
uint32_t reserved_26:6;
};
uint32_t val;
} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
/** Type of core_0_dram0_exception_monitor_0 register
* exception monitor status register2
*/
typedef union {
struct {
/** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_0
*/
uint32_t core_0_dram0_recording_addr_0:24;
/** core_0_dram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
* reg_core_0_dram0_recording_wr_0
*/
uint32_t core_0_dram0_recording_wr_0:1;
/** core_0_dram0_recording_byteen_0 : RO; bitpos: [28:25]; default: 0;
* reg_core_0_dram0_recording_byteen_0
*/
uint32_t core_0_dram0_recording_byteen_0:4;
uint32_t reserved_29:3;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
/** Type of core_0_dram0_exception_monitor_1 register
* exception monitor status register3
*/
typedef union {
struct {
/** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_0
*/
uint32_t core_0_dram0_recording_pc_0:32;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
/** Type of core_0_dram0_exception_monitor_2 register
* exception monitor status register4
*/
typedef union {
struct {
/** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
* reg_core_0_dram0_recording_addr_1
*/
uint32_t core_0_dram0_recording_addr_1:24;
/** core_0_dram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
* reg_core_0_dram0_recording_wr_1
*/
uint32_t core_0_dram0_recording_wr_1:1;
/** core_0_dram0_recording_byteen_1 : RO; bitpos: [28:25]; default: 0;
* reg_core_0_dram0_recording_byteen_1
*/
uint32_t core_0_dram0_recording_byteen_1:4;
uint32_t reserved_29:3;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
/** Type of core_0_dram0_exception_monitor_3 register
* exception monitor status register5
*/
typedef union {
struct {
/** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
* reg_core_0_dram0_recording_pc_1
*/
uint32_t core_0_dram0_recording_pc_1:32;
};
uint32_t val;
} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
/** Type of core_x_iram0_dram0_exception_monitor_0 register
* exception monitor status register6
*/
typedef union {
struct {
/** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_0
*/
uint32_t core_x_iram0_dram0_limit_cycle_0:20;
uint32_t reserved_20:12;
};
uint32_t val;
} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
/** Type of core_x_iram0_dram0_exception_monitor_1 register
* exception monitor status register7
*/
typedef union {
struct {
/** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
* reg_core_x_iram0_dram0_limit_cycle_1
*/
uint32_t core_x_iram0_dram0_limit_cycle_1:20;
uint32_t reserved_20:12;
};
uint32_t val;
} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
/** Group: cpu status registers */
/** Type of core_0_lastpc_before_exception register
* cpu status register
*/
typedef union {
struct {
/** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
* cpu's lastpc before exception
*/
uint32_t core_0_lastpc_before_exc:32;
};
uint32_t val;
} assist_debug_core_0_lastpc_before_exception_reg_t;
/** Type of core_0_debug_mode register
* cpu status register
*/
typedef union {
struct {
/** core_0_debug_mode : RO; bitpos: [0]; default: 0;
* cpu debug mode status, 1 means cpu enter debug mode.
*/
uint32_t core_0_debug_mode:1;
/** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
* cpu debug_module active status
*/
uint32_t core_0_debug_module_active:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_debug_mode_reg_t;
/** Group: Configuration Registers */
/** Type of clock_gate register
* clock register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 force on the clock gate
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} assist_debug_clock_gate_reg_t;
/** Type of date register
* version register
*/
typedef union {
struct {
/** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
* version register
*/
uint32_t assist_debug_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} assist_debug_date_reg_t;
typedef struct assist_debug_dev_t {
volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
volatile assist_debug_clock_gate_reg_t clock_gate;
uint32_t reserved_07c[224];
volatile assist_debug_date_reg_t date;
} assist_debug_dev_t;
extern assist_debug_dev_t ASSIST_DEBUG;
#ifndef __cplusplus
_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
* memory that stores Y
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
* memory that stores M
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
* memory that stores Rb
*/
#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
#define DS_RB_MEM_SIZE_BYTES 512
/** DS_BOX_MEM register
* memory that stores BOX
*/
#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
#define DS_BOX_MEM_SIZE_BYTES 48
/** DS_IV_MEM register
* memory that stores IV
*/
#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
#define DS_IV_MEM_SIZE_BYTES 16
/** DS_X_MEM register
* memory that stores X
*/
#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
#define DS_X_MEM_SIZE_BYTES 512
/** DS_Z_MEM register
* memory that stores Z
*/
#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
#define DS_Z_MEM_SIZE_BYTES 512
/** DS_SET_START_REG register
* DS start control register
*/
#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
/** DS_SET_START : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
#define DS_SET_START (BIT(0))
#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S)
#define DS_SET_START_V 0x00000001U
#define DS_SET_START_S 0
/** DS_SET_CONTINUE_REG register
* DS continue control register
*/
#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
#define DS_SET_CONTINUE (BIT(0))
#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
#define DS_SET_CONTINUE_V 0x00000001U
#define DS_SET_CONTINUE_S 0
/** DS_SET_FINISH_REG register
* DS finish control register
*/
#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
#define DS_SET_FINISH (BIT(0))
#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S)
#define DS_SET_FINISH_V 0x00000001U
#define DS_SET_FINISH_S 0
/** DS_QUERY_BUSY_REG register
* DS query busy register
*/
#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
#define DS_QUERY_BUSY (BIT(0))
#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
#define DS_QUERY_BUSY_V 0x00000001U
#define DS_QUERY_BUSY_S 0
/** DS_QUERY_KEY_WRONG_REG register
* DS query key-wrong counter register
*/
#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
#define DS_QUERY_KEY_WRONG 0x0000000FU
#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
#define DS_QUERY_KEY_WRONG_V 0x0000000FU
#define DS_QUERY_KEY_WRONG_S 0
/** DS_QUERY_CHECK_REG register
* DS query check result register
*/
#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
#define DS_MD_ERROR (BIT(0))
#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S)
#define DS_MD_ERROR_V 0x00000001U
#define DS_MD_ERROR_S 0
/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
#define DS_PADDING_BAD (BIT(1))
#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
#define DS_PADDING_BAD_V 0x00000001U
#define DS_PADDING_BAD_S 1
/** DS_DATE_REG register
* DS version control register
*/
#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
#define DS_DATE 0x3FFFFFFFU
#define DS_DATE_M (DS_DATE_V << DS_DATE_S)
#define DS_DATE_V 0x3FFFFFFFU
#define DS_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
* DS start control register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_start_reg_t;
/** Type of set_continue register
* DS continue control register
*/
typedef union {
struct {
/** set_continue : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
uint32_t set_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_continue_reg_t;
/** Type of set_finish register
* DS finish control register
*/
typedef union {
struct {
/** set_finish : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
uint32_t set_finish:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_finish_reg_t;
/** Type of query_busy register
* DS query busy register
*/
typedef union {
struct {
/** query_busy : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
uint32_t query_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_query_busy_reg_t;
/** Type of query_key_wrong register
* DS query key-wrong counter register
*/
typedef union {
struct {
/** query_key_wrong : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
uint32_t query_key_wrong:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ds_query_key_wrong_reg_t;
/** Type of query_check register
* DS query check result register
*/
typedef union {
struct {
/** md_error : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
uint32_t md_error:1;
/** padding_bad : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
uint32_t padding_bad:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ds_query_check_reg_t;
/** Group: version control register */
/** Type of date register
* DS version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} ds_date_reg_t;
typedef struct ds_dev_t {
volatile uint32_t y[128];
volatile uint32_t m[128];
volatile uint32_t rb[128];
volatile uint32_t box[12];
volatile uint32_t iv[4];
uint32_t reserved_640[112];
volatile uint32_t x[128];
volatile uint32_t z[128];
uint32_t reserved_c00[128];
volatile ds_set_start_reg_t set_start;
volatile ds_set_continue_reg_t set_continue;
volatile ds_set_finish_reg_t set_finish;
volatile ds_query_busy_reg_t query_busy;
volatile ds_query_key_wrong_reg_t query_key_wrong;
volatile ds_query_check_reg_t query_check;
uint32_t reserved_e18[2];
volatile ds_date_reg_t date;
} ds_dev_t;
extern ds_dev_t DS;
#ifndef __cplusplus
_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
* ECC interrupt raw register, valid in level.
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register
* ECC interrupt status register.
*/
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register
* ECC interrupt enable register.
*/
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register
* ECC interrupt clear register.
*/
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register
* ECC configure register
*/
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
* the caculatrion is done.
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Write 1 to reset ECC Accelerator.
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
* The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
*/
#define ECC_MULT_KEY_LENGTH (BIT(2))
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000001U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [3]; default: 0;
* Reserved
*/
#define ECC_MULT_SECURITY_MODE (BIT(3))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 3
/** ECC_MULT_CLK_EN : R/W; bitpos: [4]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECC_MULT_CLK_EN (BIT(4))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 4
/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:5]; default: 0;
* The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2:
* Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5:
* Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
*/
#define ECC_MULT_WORK_MODE 0x00000007U
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x00000007U
#define ECC_MULT_WORK_MODE_S 5
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [8]; default: 0;
* The verification result bit of ECC Accelerator, only valid when calculation is done.
*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(8))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 8
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 1;
* ECC memory clock gate force on register
*/
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
/** ECC_MULT_DATE_REG register
* Version control register
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 35656256;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
#define ECC_MULT_DATE_V 0x0FFFFFFFU
#define ECC_MULT_DATE_S 0
/** ECC_MULT_K_MEM register
* The memory that stores k.
*/
#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
#define ECC_MULT_K_MEM_SIZE_BYTES 32
/** ECC_MULT_PX_MEM register
* The memory that stores Px.
*/
#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
#define ECC_MULT_PX_MEM_SIZE_BYTES 32
/** ECC_MULT_PY_MEM register
* The memory that stores Py.
*/
#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
#define ECC_MULT_PY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of int_raw register
* ECC interrupt raw register, valid in level.
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_raw_reg_t;
/** Type of int_st register
* ECC interrupt status register.
*/
typedef union {
struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_st_reg_t;
/** Type of int_ena register
* ECC interrupt enable register.
*/
typedef union {
struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_ena_reg_t;
/** Type of int_clr register
* ECC interrupt clear register.
*/
typedef union {
struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */
/** Type of conf register
* ECC configure register
*/
typedef union {
struct {
/** start : R/W/SC; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
* the caculatrion is done.
*/
uint32_t start:1;
/** reset : WT; bitpos: [1]; default: 0;
* Write 1 to reset ECC Accelerator.
*/
uint32_t reset:1;
/** key_length : R/W; bitpos: [2]; default: 0;
* The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
*/
uint32_t key_length:1;
/** security_mode : R/W; bitpos: [3]; default: 0;
* Reserved
*/
uint32_t security_mode:1;
/** clk_en : R/W; bitpos: [4]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** work_mode : R/W; bitpos: [7:5]; default: 0;
* The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2:
* Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5:
* Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
*/
uint32_t work_mode:3;
/** verification_result : RO/SS; bitpos: [8]; default: 0;
* The verification result bit of ECC Accelerator, only valid when calculation is done.
*/
uint32_t verification_result:1;
uint32_t reserved_9:22;
/** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 1;
* ECC memory clock gate force on register
*/
uint32_t mem_clock_gate_force_on:1;
};
uint32_t val;
} ecc_mult_conf_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35656256;
* ECC mult version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecc_mult_date_reg_t;
typedef struct ecc_mult_dev_t {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t int_raw;
volatile ecc_mult_int_st_reg_t int_st;
volatile ecc_mult_int_ena_reg_t int_ena;
volatile ecc_mult_int_clr_reg_t int_clr;
volatile ecc_mult_conf_reg_t conf;
uint32_t reserved_020[55];
volatile ecc_mult_date_reg_t date;
volatile uint32_t k[8];
volatile uint32_t px[8];
volatile uint32_t py[8];
} ecc_mult_dev_t;
extern ecc_mult_dev_t ECC;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// TODO: IDF-5797
#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0)
#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4)
/* EXTMEM_DCACHE_SHUT_DBUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable.*/
#define EXTMEM_DCACHE_SHUT_DBUS1 (BIT(1))
#define EXTMEM_DCACHE_SHUT_DBUS1_M (BIT(1))
#define EXTMEM_DCACHE_SHUT_DBUS1_V 0x1
#define EXTMEM_DCACHE_SHUT_DBUS1_S 1
/* EXTMEM_DCACHE_SHUT_DBUS0 : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable.*/
#define EXTMEM_DCACHE_SHUT_DBUS0 (BIT(0))
#define EXTMEM_DCACHE_SHUT_DBUS0_M (BIT(0))
#define EXTMEM_DCACHE_SHUT_DBUS0_V 0x1
#define EXTMEM_DCACHE_SHUT_DBUS0_S 0
#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20)
/* EXTMEM_DCACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/
#define EXTMEM_DCACHE_WRAP (BIT(4))
#define EXTMEM_DCACHE_WRAP_M (BIT(4))
#define EXTMEM_DCACHE_WRAP_V 0x1
#define EXTMEM_DCACHE_WRAP_S 4
#define EXTMEM_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24)
/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
/*description: The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power u
p.*/
#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(18))
#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (BIT(18))
#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x1
#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 18
/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
/*description: The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power
down.*/
#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(17))
#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (BIT(17))
#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x1
#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 17
/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: The bit is used to close clock gating of L1-DCache tag memory. 1: close gating,
0: open clock gating..*/
#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(16))
#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(16))
#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1
#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 16
#define EXTMEM_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28)
/* EXTMEM_DCACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
/*description: The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power
up.*/
#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU (BIT(18))
#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_M (BIT(18))
#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_V 0x1
#define EXTMEM_DCACHE_DATA_MEM_FORCE_PU_S 18
/* EXTMEM_DCACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
/*description: The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: powe
r down.*/
#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD (BIT(17))
#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_M (BIT(17))
#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_V 0x1
#define EXTMEM_DCACHE_DATA_MEM_FORCE_PD_S 17
/* EXTMEM_DCACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: The bit is used to close clock gating of L1-DCache data memory. 1: close gating
, 0: open clock gating..*/
#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON (BIT(16))
#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_M (BIT(16))
#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_V 0x1
#define EXTMEM_DCACHE_DATA_MEM_FORCE_ON_S 16
#define EXTMEM_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C)
/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */
/*description: The bit is used to indicate whether freeze operation on L1-DCache is finished or
not. 0: not finished. 1: finished..*/
#define EXTMEM_DCACHE_FREEZE_DONE (BIT(18))
#define EXTMEM_DCACHE_FREEZE_DONE_M (BIT(18))
#define EXTMEM_DCACHE_FREEZE_DONE_V 0x1
#define EXTMEM_DCACHE_FREEZE_DONE_S 18
/* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */
/*description: The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-acces
s will not stuck. 1: a miss-access will stuck..*/
#define EXTMEM_DCACHE_FREEZE_MODE (BIT(17))
#define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(17))
#define EXTMEM_DCACHE_FREEZE_MODE_V 0x1
#define EXTMEM_DCACHE_FREEZE_MODE_S 17
/* EXTMEM_DCACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
/*description: The bit is used to enable freeze operation on L1-DCache. It can be cleared by so
ftware..*/
#define EXTMEM_DCACHE_FREEZE_EN (BIT(16))
#define EXTMEM_DCACHE_FREEZE_EN_M (BIT(16))
#define EXTMEM_DCACHE_FREEZE_EN_V 0x1
#define EXTMEM_DCACHE_FREEZE_EN_S 16
#define EXTMEM_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30)
/* EXTMEM_DCACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
/*description: The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable,
1: enable..*/
#define EXTMEM_DCACHE_DATA_MEM_WR_EN (BIT(17))
#define EXTMEM_DCACHE_DATA_MEM_WR_EN_M (BIT(17))
#define EXTMEM_DCACHE_DATA_MEM_WR_EN_V 0x1
#define EXTMEM_DCACHE_DATA_MEM_WR_EN_S 17
/* EXTMEM_DCACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable,
1: enable..*/
#define EXTMEM_DCACHE_DATA_MEM_RD_EN (BIT(16))
#define EXTMEM_DCACHE_DATA_MEM_RD_EN_M (BIT(16))
#define EXTMEM_DCACHE_DATA_MEM_RD_EN_V 0x1
#define EXTMEM_DCACHE_DATA_MEM_RD_EN_S 16
#define EXTMEM_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34)
/* EXTMEM_DCACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
/*description: The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable,
1: enable..*/
#define EXTMEM_DCACHE_TAG_MEM_WR_EN (BIT(17))
#define EXTMEM_DCACHE_TAG_MEM_WR_EN_M (BIT(17))
#define EXTMEM_DCACHE_TAG_MEM_WR_EN_V 0x1
#define EXTMEM_DCACHE_TAG_MEM_WR_EN_S 17
/* EXTMEM_DCACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1
: enable..*/
#define EXTMEM_DCACHE_TAG_MEM_RD_EN (BIT(16))
#define EXTMEM_DCACHE_TAG_MEM_RD_EN_M (BIT(16))
#define EXTMEM_DCACHE_TAG_MEM_RD_EN_V 0x1
#define EXTMEM_DCACHE_TAG_MEM_RD_EN_S 16
#define EXTMEM_DCACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78)
/* EXTMEM_DCACHE_PRELOCK_RGID : HRO ;bitpos:[5:2] ;default: 4'h0 ; */
/*description: The bit is used to set the gid of l1 dcache prelock..*/
#define EXTMEM_DCACHE_PRELOCK_RGID 0x0000000F
#define EXTMEM_DCACHE_PRELOCK_RGID_M ((EXTMEM_DCACHE_PRELOCK_RGID_V)<<(EXTMEM_DCACHE_PRELOCK_RGID_S))
#define EXTMEM_DCACHE_PRELOCK_RGID_V 0xF
#define EXTMEM_DCACHE_PRELOCK_RGID_S 2
/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: The bit is used to enable the second section of prelock function on L1-DCache..*/
#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1))
#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (BIT(1))
#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x1
#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1
/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to enable the first section of prelock function on L1-DCache..*/
#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0))
#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (BIT(0))
#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x1
#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0
#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C)
/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the first section
of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SC
T0_SIZE_REG.*/
#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S))
#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0
#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80)
/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the second section
of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_S
CT1_SIZE_REG.*/
#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S))
#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0
#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84)
/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */
/*description: Those bits are used to configure the size of the second section of prelock on L1
-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG.*/
#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x00003FFF
#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S))
#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0x3FFF
#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 16
/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */
/*description: Those bits are used to configure the size of the first section of prelock on L1-
DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG.*/
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x00003FFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S))
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0x3FFF
#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 0
#define EXTMEM_CACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88)
/* EXTMEM_CACHE_LOCK_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */
/*description: The bit is used to set the gid of cache lock/unlock..*/
#define EXTMEM_CACHE_LOCK_RGID 0x0000000F
#define EXTMEM_CACHE_LOCK_RGID_M ((EXTMEM_CACHE_LOCK_RGID_V)<<(EXTMEM_CACHE_LOCK_RGID_S))
#define EXTMEM_CACHE_LOCK_RGID_V 0xF
#define EXTMEM_CACHE_LOCK_RGID_S 3
/* EXTMEM_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */
/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0:
not finished. 1: finished..*/
#define EXTMEM_CACHE_LOCK_DONE (BIT(2))
#define EXTMEM_CACHE_LOCK_DONE_M (BIT(2))
#define EXTMEM_CACHE_LOCK_DONE_V 0x1
#define EXTMEM_CACHE_LOCK_DONE_S 2
/* EXTMEM_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
unlock operation done. Note that (1) this bit and lock_ena bit are mutually exc
lusive, that is, those bits can not be set to 1 at the same time. (2) unlock ope
ration can be applied on L1-ICache, L1-DCache and L2-Cache..*/
#define EXTMEM_CACHE_UNLOCK_ENA (BIT(1))
#define EXTMEM_CACHE_UNLOCK_ENA_M (BIT(1))
#define EXTMEM_CACHE_UNLOCK_ENA_V 0x1
#define EXTMEM_CACHE_UNLOCK_ENA_S 1
/* EXTMEM_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
ock operation done. Note that (1) this bit and unlock_ena bit are mutually exclu
sive, that is, those bits can not be set to 1 at the same time. (2) lock operati
on can be applied on LL1-ICache, L1-DCache and L2-Cache..*/
#define EXTMEM_CACHE_LOCK_ENA (BIT(0))
#define EXTMEM_CACHE_LOCK_ENA_M (BIT(0))
#define EXTMEM_CACHE_LOCK_ENA_V 0x1
#define EXTMEM_CACHE_LOCK_ENA_S 0
#define EXTMEM_CACHE_LOCK_MAP_REG (DR_REG_EXTMEM_BASE + 0x8C)
/* EXTMEM_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
/*description: Those bits are used to indicate which caches in the two-level cache structure wi
ll apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-I
Cache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/
#define EXTMEM_CACHE_LOCK_MAP 0x0000003F
#define EXTMEM_CACHE_LOCK_MAP_M ((EXTMEM_CACHE_LOCK_MAP_V)<<(EXTMEM_CACHE_LOCK_MAP_S))
#define EXTMEM_CACHE_LOCK_MAP_V 0x3F
#define EXTMEM_CACHE_LOCK_MAP_S 0
#define EXTMEM_CACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x90)
/* EXTMEM_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the lock/unlock op
eration, which should be used together with CACHE_LOCK_SIZE_REG.*/
#define EXTMEM_CACHE_LOCK_ADDR 0xFFFFFFFF
#define EXTMEM_CACHE_LOCK_ADDR_M ((EXTMEM_CACHE_LOCK_ADDR_V)<<(EXTMEM_CACHE_LOCK_ADDR_S))
#define EXTMEM_CACHE_LOCK_ADDR_V 0xFFFFFFFF
#define EXTMEM_CACHE_LOCK_ADDR_S 0
#define EXTMEM_CACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x94)
/* EXTMEM_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: Those bits are used to configure the size of the lock/unlock operation, which sh
ould be used together with CACHE_LOCK_ADDR_REG.*/
#define EXTMEM_CACHE_LOCK_SIZE 0x0000FFFF
#define EXTMEM_CACHE_LOCK_SIZE_M ((EXTMEM_CACHE_LOCK_SIZE_V)<<(EXTMEM_CACHE_LOCK_SIZE_S))
#define EXTMEM_CACHE_LOCK_SIZE_V 0xFFFF
#define EXTMEM_CACHE_LOCK_SIZE_S 0
#define EXTMEM_CACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x98)
/* EXTMEM_CACHE_SYNC_RGID : HRO ;bitpos:[8:5] ;default: 4'h0 ; */
/*description: The bit is used to set the gid of cache sync operation (invalidate, clean, writ
eback, writeback_invalidate).*/
#define EXTMEM_CACHE_SYNC_RGID 0x0000000F
#define EXTMEM_CACHE_SYNC_RGID_M ((EXTMEM_CACHE_SYNC_RGID_V)<<(EXTMEM_CACHE_SYNC_RGID_S))
#define EXTMEM_CACHE_SYNC_RGID_V 0xF
#define EXTMEM_CACHE_SYNC_RGID_S 5
/* EXTMEM_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */
/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback
, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/
#define EXTMEM_CACHE_SYNC_DONE (BIT(4))
#define EXTMEM_CACHE_SYNC_DONE_M (BIT(4))
#define EXTMEM_CACHE_SYNC_DONE_V 0x1
#define EXTMEM_CACHE_SYNC_DONE_S 4
/* EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
hardware after writeback-invalidate operation done. Note that this bit and the o
ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
, that is, those bits can not be set to 1 at the same time..*/
#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3))
#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3))
#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1
#define EXTMEM_CACHE_WRITEBACK_INVALIDATE_ENA_S 3
/* EXTMEM_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */
/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
ter writeback operation done. Note that this bit and the other sync-bits (invali
date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is,
those bits can not be set to 1 at the same time..*/
#define EXTMEM_CACHE_WRITEBACK_ENA (BIT(2))
#define EXTMEM_CACHE_WRITEBACK_ENA_M (BIT(2))
#define EXTMEM_CACHE_WRITEBACK_ENA_V 0x1
#define EXTMEM_CACHE_WRITEBACK_ENA_S 2
/* EXTMEM_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
/*description: The bit is used to enable clean operation. It will be cleared by hardware after
clean operation done. Note that this bit and the other sync-bits (invalidate_ena
, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos
e bits can not be set to 1 at the same time..*/
#define EXTMEM_CACHE_CLEAN_ENA (BIT(1))
#define EXTMEM_CACHE_CLEAN_ENA_M (BIT(1))
#define EXTMEM_CACHE_CLEAN_ENA_V 0x1
#define EXTMEM_CACHE_CLEAN_ENA_S 1
/* EXTMEM_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
fter invalidate operation done. Note that this bit and the other sync-bits (clea
n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
those bits can not be set to 1 at the same time..*/
#define EXTMEM_CACHE_INVALIDATE_ENA (BIT(0))
#define EXTMEM_CACHE_INVALIDATE_ENA_M (BIT(0))
#define EXTMEM_CACHE_INVALIDATE_ENA_V 0x1
#define EXTMEM_CACHE_INVALIDATE_ENA_S 0
#define EXTMEM_CACHE_SYNC_MAP_REG (DR_REG_EXTMEM_BASE + 0x9C)
/* EXTMEM_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: Those bits are used to indicate which caches in the two-level cache structure wi
ll apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2,
[3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache..*/
#define EXTMEM_CACHE_SYNC_MAP 0x0000003F
#define EXTMEM_CACHE_SYNC_MAP_M ((EXTMEM_CACHE_SYNC_MAP_V)<<(EXTMEM_CACHE_SYNC_MAP_S))
#define EXTMEM_CACHE_SYNC_MAP_V 0x3F
#define EXTMEM_CACHE_SYNC_MAP_S 0
#define EXTMEM_CACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA0)
/* EXTMEM_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the sync operation
, which should be used together with CACHE_SYNC_SIZE_REG.*/
#define EXTMEM_CACHE_SYNC_ADDR 0xFFFFFFFF
#define EXTMEM_CACHE_SYNC_ADDR_M ((EXTMEM_CACHE_SYNC_ADDR_V)<<(EXTMEM_CACHE_SYNC_ADDR_S))
#define EXTMEM_CACHE_SYNC_ADDR_V 0xFFFFFFFF
#define EXTMEM_CACHE_SYNC_ADDR_S 0
#define EXTMEM_CACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA4)
/* EXTMEM_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Those bits are used to configure the size of the sync operation, which should be
used together with CACHE_SYNC_ADDR_REG.*/
#define EXTMEM_CACHE_SYNC_SIZE 0x00FFFFFF
#define EXTMEM_CACHE_SYNC_SIZE_M ((EXTMEM_CACHE_SYNC_SIZE_V)<<(EXTMEM_CACHE_SYNC_SIZE_S))
#define EXTMEM_CACHE_SYNC_SIZE_V 0xFFFFFF
#define EXTMEM_CACHE_SYNC_SIZE_S 0
#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xD8)
/* EXTMEM_DCACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */
/*description: The bit is used to set the gid of l1 dcache preload..*/
#define EXTMEM_DCACHE_PRELOAD_RGID 0x0000000F
#define EXTMEM_DCACHE_PRELOAD_RGID_M ((EXTMEM_DCACHE_PRELOAD_RGID_V)<<(EXTMEM_DCACHE_PRELOAD_RGID_S))
#define EXTMEM_DCACHE_PRELOAD_RGID_V 0xF
#define EXTMEM_DCACHE_PRELOAD_RGID_S 3
/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1
: descending..*/
#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2))
#define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2))
#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1
#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2
/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
/*description: The bit is used to indicate whether preload operation is finished or not. 0: not
finished. 1: finished..*/
#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1))
#define EXTMEM_DCACHE_PRELOAD_DONE_M (BIT(1))
#define EXTMEM_DCACHE_PRELOAD_DONE_V 0x1
#define EXTMEM_DCACHE_PRELOAD_DONE_S 1
/* EXTMEM_DCACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to enable preload operation on L1-DCache. It will be cleared by
hardware automatically after preload operation is done..*/
#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0))
#define EXTMEM_DCACHE_PRELOAD_ENA_M (BIT(0))
#define EXTMEM_DCACHE_PRELOAD_ENA_V 0x1
#define EXTMEM_DCACHE_PRELOAD_ENA_S 0
#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0xDC)
/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of preload on L1-DCac
he, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG.*/
#define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S))
#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF
#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0
#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0xE0)
/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
/*description: Those bits are used to configure the size of the first section of prelock on L1-
DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG.*/
#define EXTMEM_DCACHE_PRELOAD_SIZE 0x00003FFF
#define EXTMEM_DCACHE_PRELOAD_SIZE_M ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S))
#define EXTMEM_DCACHE_PRELOAD_SIZE_V 0x3FFF
#define EXTMEM_DCACHE_PRELOAD_SIZE_S 0
#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134)
/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */
/*description: The bit is used to enable the second section for autoload operation on L1-DCache
..*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(9))
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(9))
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 9
/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
/*description: The bit is used to enable the first section for autoload operation on L1-DCache..*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(8))
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(8))
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 8
/* EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: The field is used to configure trigger mode of autoload operation on L1-DCache.
0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/
#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE 0x00000003
#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_M ((EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S))
#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_V 0x3
#define EXTMEM_DCACHE_AUTOLOAD_TRIGGER_MODE_S 3
/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: The bit is used to configure the direction of autoload operation on L1-DCache. 0
: ascending. 1: descending..*/
#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(2))
#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(2))
#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1
#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 2
/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
/*description: The bit is used to indicate whether autoload operation on L1-DCache is finished
or not. 0: not finished. 1: finished..*/
#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(1))
#define EXTMEM_DCACHE_AUTOLOAD_DONE_M (BIT(1))
#define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x1
#define EXTMEM_DCACHE_AUTOLOAD_DONE_S 1
/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to enable and disable autoload operation on L1-DCache. 1: enabl
e, 0: disable..*/
#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(0))
#define EXTMEM_DCACHE_AUTOLOAD_ENA_M (BIT(0))
#define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x1
#define EXTMEM_DCACHE_AUTOLOAD_ENA_S 0
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x138)
/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the first section
for autoload operation on L1-DCache. Note that it should be used together with L
1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S))
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x13C)
/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
/*description: Those bits are used to configure the size of the first section for autoload oper
ation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD
_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA..*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S))
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x140)
/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the second section
for autoload operation on L1-DCache. Note that it should be used together with
L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S))
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x144)
/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
/*description: Those bits are used to configure the size of the second section for autoload ope
ration on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOA
D_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA..*/
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S))
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFFF
#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0
#define EXTMEM_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x158)
/* EXTMEM_DBUS1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
1-DCache due to bus1 accesses L1-DCache..*/
#define EXTMEM_DBUS1_OVF_INT_ENA (BIT(5))
#define EXTMEM_DBUS1_OVF_INT_ENA_M (BIT(5))
#define EXTMEM_DBUS1_OVF_INT_ENA_V 0x1
#define EXTMEM_DBUS1_OVF_INT_ENA_S 5
/* EXTMEM_DBUS0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
1-DCache due to bus0 accesses L1-DCache..*/
#define EXTMEM_DBUS0_OVF_INT_ENA (BIT(4))
#define EXTMEM_DBUS0_OVF_INT_ENA_M (BIT(4))
#define EXTMEM_DBUS0_OVF_INT_ENA_V 0x1
#define EXTMEM_DBUS0_OVF_INT_ENA_S 4
#define EXTMEM_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C)
/* EXTMEM_DBUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
ue to bus1 accesses L1-DCache..*/
#define EXTMEM_DBUS1_OVF_INT_CLR (BIT(5))
#define EXTMEM_DBUS1_OVF_INT_CLR_M (BIT(5))
#define EXTMEM_DBUS1_OVF_INT_CLR_V 0x1
#define EXTMEM_DBUS1_OVF_INT_CLR_S 5
/* EXTMEM_DBUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
ue to bus0 accesses L1-DCache..*/
#define EXTMEM_DBUS0_OVF_INT_CLR (BIT(4))
#define EXTMEM_DBUS0_OVF_INT_CLR_M (BIT(4))
#define EXTMEM_DBUS0_OVF_INT_CLR_V 0x1
#define EXTMEM_DBUS0_OVF_INT_CLR_S 4
#define EXTMEM_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x160)
/* EXTMEM_DBUS1_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
e due to bus1 accesses L1-DCache..*/
#define EXTMEM_DBUS1_OVF_INT_RAW (BIT(5))
#define EXTMEM_DBUS1_OVF_INT_RAW_M (BIT(5))
#define EXTMEM_DBUS1_OVF_INT_RAW_V 0x1
#define EXTMEM_DBUS1_OVF_INT_RAW_S 5
/* EXTMEM_DBUS0_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
e due to bus0 accesses L1-DCache..*/
#define EXTMEM_DBUS0_OVF_INT_RAW (BIT(4))
#define EXTMEM_DBUS0_OVF_INT_RAW_M (BIT(4))
#define EXTMEM_DBUS0_OVF_INT_RAW_V 0x1
#define EXTMEM_DBUS0_OVF_INT_RAW_S 4
#define EXTMEM_CACHE_ACS_CNT_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x164)
/* EXTMEM_DBUS1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
n L1-DCache due to bus1 accesses L1-DCache..*/
#define EXTMEM_DBUS1_OVF_INT_ST (BIT(5))
#define EXTMEM_DBUS1_OVF_INT_ST_M (BIT(5))
#define EXTMEM_DBUS1_OVF_INT_ST_V 0x1
#define EXTMEM_DBUS1_OVF_INT_ST_S 5
/* EXTMEM_DBUS0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
n L1-DCache due to bus0 accesses L1-DCache..*/
#define EXTMEM_DBUS0_OVF_INT_ST (BIT(4))
#define EXTMEM_DBUS0_OVF_INT_ST_M (BIT(4))
#define EXTMEM_DBUS0_OVF_INT_ST_V 0x1
#define EXTMEM_DBUS0_OVF_INT_ST_S 4
#define EXTMEM_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x168)
/* EXTMEM_DCACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due
to cpu accesses L1-DCache..*/
#define EXTMEM_DCACHE_FAIL_INT_ENA (BIT(4))
#define EXTMEM_DCACHE_FAIL_INT_ENA_M (BIT(4))
#define EXTMEM_DCACHE_FAIL_INT_ENA_V 0x1
#define EXTMEM_DCACHE_FAIL_INT_ENA_S 4
#define EXTMEM_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x16C)
/* EXTMEM_DCACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t
o cpu accesses L1-DCache..*/
#define EXTMEM_DCACHE_FAIL_INT_CLR (BIT(4))
#define EXTMEM_DCACHE_FAIL_INT_CLR_M (BIT(4))
#define EXTMEM_DCACHE_FAIL_INT_CLR_V 0x1
#define EXTMEM_DCACHE_FAIL_INT_CLR_S 4
#define EXTMEM_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x170)
/* EXTMEM_DCACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/
#define EXTMEM_DCACHE_FAIL_INT_RAW (BIT(4))
#define EXTMEM_DCACHE_FAIL_INT_RAW_M (BIT(4))
#define EXTMEM_DCACHE_FAIL_INT_RAW_V 0x1
#define EXTMEM_DCACHE_FAIL_INT_RAW_S 4
#define EXTMEM_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174)
/* EXTMEM_DCACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d
ue to cpu accesses L1-DCache..*/
#define EXTMEM_DCACHE_FAIL_INT_ST (BIT(4))
#define EXTMEM_DCACHE_FAIL_INT_ST_M (BIT(4))
#define EXTMEM_DCACHE_FAIL_INT_ST_V 0x1
#define EXTMEM_DCACHE_FAIL_INT_ST_S 4
#define EXTMEM_CACHE_ACS_CNT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x178)
/* EXTMEM_DBUS1_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */
/*description: The bit is used to clear dbus1 counter in L1-DCache..*/
#define EXTMEM_DBUS1_CNT_CLR (BIT(21))
#define EXTMEM_DBUS1_CNT_CLR_M (BIT(21))
#define EXTMEM_DBUS1_CNT_CLR_V 0x1
#define EXTMEM_DBUS1_CNT_CLR_S 21
/* EXTMEM_DBUS0_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
/*description: The bit is used to clear dbus0 counter in L1-DCache..*/
#define EXTMEM_DBUS0_CNT_CLR (BIT(20))
#define EXTMEM_DBUS0_CNT_CLR_M (BIT(20))
#define EXTMEM_DBUS0_CNT_CLR_V 0x1
#define EXTMEM_DBUS0_CNT_CLR_S 20
/* EXTMEM_DBUS1_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to enable dbus1 counter in L1-DCache..*/
#define EXTMEM_DBUS1_CNT_ENA (BIT(5))
#define EXTMEM_DBUS1_CNT_ENA_M (BIT(5))
#define EXTMEM_DBUS1_CNT_ENA_V 0x1
#define EXTMEM_DBUS1_CNT_ENA_S 5
/* EXTMEM_DBUS0_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable dbus0 counter in L1-DCache..*/
#define EXTMEM_DBUS0_CNT_ENA (BIT(4))
#define EXTMEM_DBUS0_CNT_ENA_M (BIT(4))
#define EXTMEM_DBUS0_CNT_ENA_V 0x1
#define EXTMEM_DBUS0_CNT_ENA_S 4
#define EXTMEM_DBUS0_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1BC)
/* EXTMEM_DBUS0_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of hits when bus0 accesses L1-DCache..*/
#define EXTMEM_DBUS0_HIT_CNT 0xFFFFFFFF
#define EXTMEM_DBUS0_HIT_CNT_M ((EXTMEM_DBUS0_HIT_CNT_V)<<(EXTMEM_DBUS0_HIT_CNT_S))
#define EXTMEM_DBUS0_HIT_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS0_HIT_CNT_S 0
#define EXTMEM_DBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C0)
/* EXTMEM_DBUS0_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of missing when bus0 accesses L1-DCache..*/
#define EXTMEM_DBUS0_MISS_CNT 0xFFFFFFFF
#define EXTMEM_DBUS0_MISS_CNT_M ((EXTMEM_DBUS0_MISS_CNT_V)<<(EXTMEM_DBUS0_MISS_CNT_S))
#define EXTMEM_DBUS0_MISS_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS0_MISS_CNT_S 0
#define EXTMEM_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C4)
/* EXTMEM_DBUS0_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of access-conflicts when bus0 accesses L1-DCache
..*/
#define EXTMEM_DBUS0_CONFLICT_CNT 0xFFFFFFFF
#define EXTMEM_DBUS0_CONFLICT_CNT_M ((EXTMEM_DBUS0_CONFLICT_CNT_V)<<(EXTMEM_DBUS0_CONFLICT_CNT_S))
#define EXTMEM_DBUS0_CONFLICT_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS0_CONFLICT_CNT_S 0
#define EXTMEM_DBUS0_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C8)
/* EXTMEM_DBUS0_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of times that L1-DCache accesses L2-Cache due to
bus0 accessing L1-DCache..*/
#define EXTMEM_DBUS0_NXTLVL_CNT 0xFFFFFFFF
#define EXTMEM_DBUS0_NXTLVL_CNT_M ((EXTMEM_DBUS0_NXTLVL_CNT_V)<<(EXTMEM_DBUS0_NXTLVL_CNT_S))
#define EXTMEM_DBUS0_NXTLVL_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS0_NXTLVL_CNT_S 0
#define EXTMEM_DBUS1_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1CC)
/* EXTMEM_DBUS1_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of hits when bus1 accesses L1-DCache..*/
#define EXTMEM_DBUS1_HIT_CNT 0xFFFFFFFF
#define EXTMEM_DBUS1_HIT_CNT_M ((EXTMEM_DBUS1_HIT_CNT_V)<<(EXTMEM_DBUS1_HIT_CNT_S))
#define EXTMEM_DBUS1_HIT_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS1_HIT_CNT_S 0
#define EXTMEM_DBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D0)
/* EXTMEM_DBUS1_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of missing when bus1 accesses L1-DCache..*/
#define EXTMEM_DBUS1_MISS_CNT 0xFFFFFFFF
#define EXTMEM_DBUS1_MISS_CNT_M ((EXTMEM_DBUS1_MISS_CNT_V)<<(EXTMEM_DBUS1_MISS_CNT_S))
#define EXTMEM_DBUS1_MISS_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS1_MISS_CNT_S 0
#define EXTMEM_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D4)
/* EXTMEM_DBUS1_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of access-conflicts when bus1 accesses L1-DCache
..*/
#define EXTMEM_DBUS1_CONFLICT_CNT 0xFFFFFFFF
#define EXTMEM_DBUS1_CONFLICT_CNT_M ((EXTMEM_DBUS1_CONFLICT_CNT_V)<<(EXTMEM_DBUS1_CONFLICT_CNT_S))
#define EXTMEM_DBUS1_CONFLICT_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS1_CONFLICT_CNT_S 0
#define EXTMEM_DBUS1_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D8)
/* EXTMEM_DBUS1_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of times that L1-DCache accesses L2-Cache due to
bus1 accessing L1-DCache..*/
#define EXTMEM_DBUS1_NXTLVL_CNT 0xFFFFFFFF
#define EXTMEM_DBUS1_NXTLVL_CNT_M ((EXTMEM_DBUS1_NXTLVL_CNT_V)<<(EXTMEM_DBUS1_NXTLVL_CNT_S))
#define EXTMEM_DBUS1_NXTLVL_CNT_V 0xFFFFFFFF
#define EXTMEM_DBUS1_NXTLVL_CNT_S 0
#define EXTMEM_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x1FC)
/* EXTMEM_ICACHE0_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: The register records the attribution of fail-access when cache0 accesses L1-ICac
he..*/
#define EXTMEM_ICACHE0_FAIL_ATTR 0x0000FFFF
#define EXTMEM_ICACHE0_FAIL_ATTR_M ((EXTMEM_ICACHE0_FAIL_ATTR_V)<<(EXTMEM_ICACHE0_FAIL_ATTR_S))
#define EXTMEM_ICACHE0_FAIL_ATTR_V 0xFFFF
#define EXTMEM_ICACHE0_FAIL_ATTR_S 16
/* EXTMEM_ICACHE0_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: The register records the ID of fail-access when cache0 accesses L1-ICache..*/
#define EXTMEM_ICACHE0_FAIL_ID 0x0000FFFF
#define EXTMEM_ICACHE0_FAIL_ID_M ((EXTMEM_ICACHE0_FAIL_ID_V)<<(EXTMEM_ICACHE0_FAIL_ID_S))
#define EXTMEM_ICACHE0_FAIL_ID_V 0xFFFF
#define EXTMEM_ICACHE0_FAIL_ID_S 0
#define EXTMEM_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x200)
/* EXTMEM_ICACHE0_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the address of fail-access when cache0 accesses L1-ICache..*/
#define EXTMEM_ICACHE0_FAIL_ADDR 0xFFFFFFFF
#define EXTMEM_ICACHE0_FAIL_ADDR_M ((EXTMEM_ICACHE0_FAIL_ADDR_V)<<(EXTMEM_ICACHE0_FAIL_ADDR_S))
#define EXTMEM_ICACHE0_FAIL_ADDR_V 0xFFFFFFFF
#define EXTMEM_ICACHE0_FAIL_ADDR_S 0
#define EXTMEM_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x204)
/* EXTMEM_ICACHE1_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: The register records the attribution of fail-access when cache1 accesses L1-ICac
he..*/
#define EXTMEM_ICACHE1_FAIL_ATTR 0x0000FFFF
#define EXTMEM_ICACHE1_FAIL_ATTR_M ((EXTMEM_ICACHE1_FAIL_ATTR_V)<<(EXTMEM_ICACHE1_FAIL_ATTR_S))
#define EXTMEM_ICACHE1_FAIL_ATTR_V 0xFFFF
#define EXTMEM_ICACHE1_FAIL_ATTR_S 16
/* EXTMEM_ICACHE1_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: The register records the ID of fail-access when cache1 accesses L1-ICache..*/
#define EXTMEM_ICACHE1_FAIL_ID 0x0000FFFF
#define EXTMEM_ICACHE1_FAIL_ID_M ((EXTMEM_ICACHE1_FAIL_ID_V)<<(EXTMEM_ICACHE1_FAIL_ID_S))
#define EXTMEM_ICACHE1_FAIL_ID_V 0xFFFF
#define EXTMEM_ICACHE1_FAIL_ID_S 0
#define EXTMEM_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x208)
/* EXTMEM_ICACHE1_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the address of fail-access when cache1 accesses L1-ICache..*/
#define EXTMEM_ICACHE1_FAIL_ADDR 0xFFFFFFFF
#define EXTMEM_ICACHE1_FAIL_ADDR_M ((EXTMEM_ICACHE1_FAIL_ADDR_V)<<(EXTMEM_ICACHE1_FAIL_ADDR_S))
#define EXTMEM_ICACHE1_FAIL_ADDR_V 0xFFFFFFFF
#define EXTMEM_ICACHE1_FAIL_ADDR_S 0
#define EXTMEM_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x21C)
/* EXTMEM_DCACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: The register records the attribution of fail-access when cache accesses L1-DCach
e..*/
#define EXTMEM_DCACHE_FAIL_ATTR 0x0000FFFF
#define EXTMEM_DCACHE_FAIL_ATTR_M ((EXTMEM_DCACHE_FAIL_ATTR_V)<<(EXTMEM_DCACHE_FAIL_ATTR_S))
#define EXTMEM_DCACHE_FAIL_ATTR_V 0xFFFF
#define EXTMEM_DCACHE_FAIL_ATTR_S 16
/* EXTMEM_DCACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: The register records the ID of fail-access when cache accesses L1-DCache..*/
#define EXTMEM_DCACHE_FAIL_ID 0x0000FFFF
#define EXTMEM_DCACHE_FAIL_ID_M ((EXTMEM_DCACHE_FAIL_ID_V)<<(EXTMEM_DCACHE_FAIL_ID_S))
#define EXTMEM_DCACHE_FAIL_ID_V 0xFFFF
#define EXTMEM_DCACHE_FAIL_ID_S 0
#define EXTMEM_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x220)
/* EXTMEM_DCACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the address of fail-access when cache accesses L1-DCache..*/
#define EXTMEM_DCACHE_FAIL_ADDR 0xFFFFFFFF
#define EXTMEM_DCACHE_FAIL_ADDR_M ((EXTMEM_DCACHE_FAIL_ADDR_V)<<(EXTMEM_DCACHE_FAIL_ADDR_S))
#define EXTMEM_DCACHE_FAIL_ADDR_V 0xFFFFFFFF
#define EXTMEM_DCACHE_FAIL_ADDR_S 0
#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x224)
/* EXTMEM_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of Cache sync-operation error..*/
#define EXTMEM_CACHE_SYNC_ERR_INT_ENA (BIT(13))
#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_M (BIT(13))
#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_V 0x1
#define EXTMEM_CACHE_SYNC_ERR_INT_ENA_S 13
/* EXTMEM_DCACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of L1-DCache preload-operation error..*/
#define EXTMEM_DCACHE_PLD_ERR_INT_ENA (BIT(11))
#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_M (BIT(11))
#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_V 0x1
#define EXTMEM_DCACHE_PLD_ERR_INT_ENA_S 11
/* EXTMEM_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of Cache sync-operation done..*/
#define EXTMEM_CACHE_SYNC_DONE_INT_ENA (BIT(6))
#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_M (BIT(6))
#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_V 0x1
#define EXTMEM_CACHE_SYNC_DONE_INT_ENA_S 6
/* EXTMEM_DCACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of L1-DCache preload-operation. If preload o
peration is done, interrupt occurs..*/
#define EXTMEM_DCACHE_PLD_DONE_INT_ENA (BIT(4))
#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_M (BIT(4))
#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_V 0x1
#define EXTMEM_DCACHE_PLD_DONE_INT_ENA_S 4
#define EXTMEM_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x228)
/* EXTMEM_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt of Cache sync-operation error..*/
#define EXTMEM_CACHE_SYNC_ERR_INT_CLR (BIT(13))
#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_M (BIT(13))
#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_V 0x1
#define EXTMEM_CACHE_SYNC_ERR_INT_CLR_S 13
/* EXTMEM_DCACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt of L1-DCache preload-operation error..*/
#define EXTMEM_DCACHE_PLD_ERR_INT_CLR (BIT(11))
#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_M (BIT(11))
#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_V 0x1
#define EXTMEM_DCACHE_PLD_ERR_INT_CLR_S 11
/* EXTMEM_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is
done..*/
#define EXTMEM_CACHE_SYNC_DONE_INT_CLR (BIT(6))
#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_M (BIT(6))
#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_V 0x1
#define EXTMEM_CACHE_SYNC_DONE_INT_CLR_S 6
/* EXTMEM_DCACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt that occurs only when L1-DCache preload-opera
tion is done..*/
#define EXTMEM_DCACHE_PLD_DONE_INT_CLR (BIT(4))
#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_M (BIT(4))
#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_V 0x1
#define EXTMEM_DCACHE_PLD_DONE_INT_CLR_S 4
#define EXTMEM_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x22C)
/* EXTMEM_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc
curs..*/
#define EXTMEM_CACHE_SYNC_ERR_INT_RAW (BIT(13))
#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_M (BIT(13))
#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_V 0x1
#define EXTMEM_CACHE_SYNC_ERR_INT_RAW_S 13
/* EXTMEM_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation e
rror occurs..*/
#define EXTMEM_DCACHE_PLD_ERR_INT_RAW (BIT(11))
#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_M (BIT(11))
#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_V 0x1
#define EXTMEM_DCACHE_PLD_ERR_INT_RAW_S 11
/* EXTMEM_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/
#define EXTMEM_CACHE_SYNC_DONE_INT_RAW (BIT(6))
#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_M (BIT(6))
#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_V 0x1
#define EXTMEM_CACHE_SYNC_DONE_INT_RAW_S 6
/* EXTMEM_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt that occurs only when L1-DCache preload-operation i
s done..*/
#define EXTMEM_DCACHE_PLD_DONE_INT_RAW (BIT(4))
#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_M (BIT(4))
#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_V 0x1
#define EXTMEM_DCACHE_PLD_DONE_INT_RAW_S 4
#define EXTMEM_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x230)
/* EXTMEM_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/
#define EXTMEM_CACHE_SYNC_ERR_INT_ST (BIT(13))
#define EXTMEM_CACHE_SYNC_ERR_INT_ST_M (BIT(13))
#define EXTMEM_CACHE_SYNC_ERR_INT_ST_V 0x1
#define EXTMEM_CACHE_SYNC_ERR_INT_ST_S 13
/* EXTMEM_DCACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The bit indicates the status of the interrupt of L1-DCache preload-operation err
or..*/
#define EXTMEM_DCACHE_PLD_ERR_INT_ST (BIT(11))
#define EXTMEM_DCACHE_PLD_ERR_INT_ST_M (BIT(11))
#define EXTMEM_DCACHE_PLD_ERR_INT_ST_V 0x1
#define EXTMEM_DCACHE_PLD_ERR_INT_ST_S 11
/* EXTMEM_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o
peration is done..*/
#define EXTMEM_CACHE_SYNC_DONE_INT_ST (BIT(6))
#define EXTMEM_CACHE_SYNC_DONE_INT_ST_M (BIT(6))
#define EXTMEM_CACHE_SYNC_DONE_INT_ST_V 0x1
#define EXTMEM_CACHE_SYNC_DONE_INT_ST_S 6
/* EXTMEM_DCACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit indicates the status of the interrupt that occurs only when L1-DCache pr
eload-operation is done..*/
#define EXTMEM_DCACHE_PLD_DONE_INT_ST (BIT(4))
#define EXTMEM_DCACHE_PLD_DONE_INT_ST_M (BIT(4))
#define EXTMEM_DCACHE_PLD_DONE_INT_ST_V 0x1
#define EXTMEM_DCACHE_PLD_DONE_INT_ST_S 4
#define EXTMEM_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_EXTMEM_BASE + 0x234)
/* EXTMEM_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: The values 0-2 are available which means sync map, command conflict and size are
error in Cache System..*/
#define EXTMEM_CACHE_SYNC_ERR_CODE 0x00000003
#define EXTMEM_CACHE_SYNC_ERR_CODE_M ((EXTMEM_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_CACHE_SYNC_ERR_CODE_S))
#define EXTMEM_CACHE_SYNC_ERR_CODE_V 0x3
#define EXTMEM_CACHE_SYNC_ERR_CODE_S 12
/* EXTMEM_DCACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: The value 2 is Only available which means preload size is error in L1-DCache..*/
#define EXTMEM_DCACHE_PLD_ERR_CODE 0x00000003
#define EXTMEM_DCACHE_PLD_ERR_CODE_M ((EXTMEM_DCACHE_PLD_ERR_CODE_V)<<(EXTMEM_DCACHE_PLD_ERR_CODE_S))
#define EXTMEM_DCACHE_PLD_ERR_CODE_V 0x3
#define EXTMEM_DCACHE_PLD_ERR_CODE_S 8
#define EXTMEM_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238)
/* EXTMEM_DCACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: set this bit to reset sync-logic inside L1-DCache. Recommend that this should on
ly be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
#define EXTMEM_DCACHE_SYNC_RST (BIT(4))
#define EXTMEM_DCACHE_SYNC_RST_M (BIT(4))
#define EXTMEM_DCACHE_SYNC_RST_V 0x1
#define EXTMEM_DCACHE_SYNC_RST_S 4
#define EXTMEM_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x23C)
/* EXTMEM_DCACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: set this bit to reset preload-logic inside L1-DCache. Recommend that this should
only be used to initialize preload-logic when some fatal error of preload-logic
occurs..*/
#define EXTMEM_DCACHE_PLD_RST (BIT(4))
#define EXTMEM_DCACHE_PLD_RST_M (BIT(4))
#define EXTMEM_DCACHE_PLD_RST_V 0x1
#define EXTMEM_DCACHE_PLD_RST_S 4
#define EXTMEM_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_EXTMEM_BASE + 0x240)
/* EXTMEM_DCACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, a
utoload will not work in L1-DCache. This bit should not be active when autoload
works in L1-DCache..*/
#define EXTMEM_DCACHE_ALD_BUF_CLR (BIT(4))
#define EXTMEM_DCACHE_ALD_BUF_CLR_M (BIT(4))
#define EXTMEM_DCACHE_ALD_BUF_CLR_V 0x1
#define EXTMEM_DCACHE_ALD_BUF_CLR_S 4
#define EXTMEM_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244)
/* EXTMEM_DCACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to clear the unallocate request buffer of l1 dcache where the un
allocate request is responsed but not completed..*/
#define EXTMEM_DCACHE_UNALLOC_CLR (BIT(4))
#define EXTMEM_DCACHE_UNALLOC_CLR_M (BIT(4))
#define EXTMEM_DCACHE_UNALLOC_CLR_V 0x1
#define EXTMEM_DCACHE_UNALLOC_CLR_S 4
#define EXTMEM_CACHE_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x248)
/* EXTMEM_DCACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to set L1-DCache data memory as object. This bit should be onehot w
ith the others fields inside this register..*/
#define EXTMEM_DCACHE_MEM_OBJECT (BIT(10))
#define EXTMEM_DCACHE_MEM_OBJECT_M (BIT(10))
#define EXTMEM_DCACHE_MEM_OBJECT_V 0x1
#define EXTMEM_DCACHE_MEM_OBJECT_S 10
/* EXTMEM_DCACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to set L1-DCache tag memory as object. This bit should be onehot wi
th the others fields inside this register..*/
#define EXTMEM_DCACHE_TAG_OBJECT (BIT(4))
#define EXTMEM_DCACHE_TAG_OBJECT_M (BIT(4))
#define EXTMEM_DCACHE_TAG_OBJECT_V 0x1
#define EXTMEM_DCACHE_TAG_OBJECT_S 4
#define EXTMEM_CACHE_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x24C)
/* EXTMEM_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
: way1, 2: way2, 3: way3, ?, 7: way7..*/
#define EXTMEM_CACHE_WAY_OBJECT 0x00000007
#define EXTMEM_CACHE_WAY_OBJECT_M ((EXTMEM_CACHE_WAY_OBJECT_V)<<(EXTMEM_CACHE_WAY_OBJECT_S))
#define EXTMEM_CACHE_WAY_OBJECT_V 0x7
#define EXTMEM_CACHE_WAY_OBJECT_S 0
#define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250)
/* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
/*description: Those bits stores the virtual address which will decide where inside the specifi
ed tag memory object will be accessed..*/
#define EXTMEM_CACHE_VADDR 0xFFFFFFFF
#define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S))
#define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF
#define EXTMEM_CACHE_VADDR_S 0
#define EXTMEM_CACHE_DEBUG_BUS_REG (DR_REG_EXTMEM_BASE + 0x254)
/* EXTMEM_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */
/*description: This is a constant place where we can write data to or read data from the tag/da
ta memory on the specified cache..*/
#define EXTMEM_CACHE_DEBUG_BUS 0xFFFFFFFF
#define EXTMEM_CACHE_DEBUG_BUS_M ((EXTMEM_CACHE_DEBUG_BUS_V)<<(EXTMEM_CACHE_DEBUG_BUS_S))
#define EXTMEM_CACHE_DEBUG_BUS_V 0xFFFFFFFF
#define EXTMEM_CACHE_DEBUG_BUS_S 0
#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC)
/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */
/*description: version control register. Note that this default value stored is the latest date
when the hardware logic was updated..*/
#define EXTMEM_DATE 0x0FFFFFFF
#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
#define EXTMEM_DATE_V 0xFFFFFFF
#define EXTMEM_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Interrupt Registers */
/** Type of in_int_raw_chn register
* Raw status interrupt of channel 0
*/
typedef union {
struct {
/** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when the last data pointed by one inlink
* descriptor has been received for Rx channel 0.
*/
uint32_t in_done_int_raw:1;
/** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when the last data pointed by one inlink
* descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
* turns to high level when the last data pointed by one inlink descriptor has been
* received and no data error is detected for Rx channel 0.
*/
uint32_t in_suc_eof_int_raw:1;
/** in_err_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when data error is detected only in the
* case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
* interrupt is reserved.
*/
uint32_t in_err_eof_int_raw:1;
/** in_dscr_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt bit turns to high level when detecting inlink descriptor error
* including owner error and the second and third word error of inlink descriptor for
* Rx channel 0.
*/
uint32_t in_dscr_err_int_raw:1;
/** in_dscr_empty_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
* and receiving data is not completed but there is no more inlink for Rx channel 0.
*/
uint32_t in_dscr_empty_int_raw:1;
/** infifo_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
* overflow.
*/
uint32_t infifo_ovf_int_raw:1;
/** infifo_udf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
* underflow.
*/
uint32_t infifo_udf_int_raw:1;
uint32_t reserved_7:25;
};
uint32_t val;
} gdma_in_int_raw_chn_reg_t;
/** Type of in_int_st_chn register
* Masked interrupt of channel 0
*/
typedef union {
struct {
/** in_done_int_st : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
*/
uint32_t in_done_int_st:1;
/** in_suc_eof_int_st : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
*/
uint32_t in_suc_eof_int_st:1;
/** in_err_eof_int_st : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
*/
uint32_t in_err_eof_int_st:1;
/** in_dscr_err_int_st : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
*/
uint32_t in_dscr_err_int_st:1;
/** in_dscr_empty_int_st : RO; bitpos: [4]; default: 0;
* The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
*/
uint32_t in_dscr_empty_int_st:1;
/** infifo_ovf_int_st : RO; bitpos: [5]; default: 0;
* The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
*/
uint32_t infifo_ovf_int_st:1;
/** infifo_udf_int_st : RO; bitpos: [6]; default: 0;
* The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t infifo_udf_int_st:1;
uint32_t reserved_7:25;
};
uint32_t val;
} gdma_in_int_st_chn_reg_t;
/** Type of in_int_ena_chn register
* Interrupt enable bits of channel 0
*/
typedef union {
struct {
/** in_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the IN_DONE_CH_INT interrupt.
*/
uint32_t in_done_int_ena:1;
/** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
*/
uint32_t in_suc_eof_int_ena:1;
/** in_err_eof_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
*/
uint32_t in_err_eof_int_ena:1;
/** in_dscr_err_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
*/
uint32_t in_dscr_err_int_ena:1;
/** in_dscr_empty_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
*/
uint32_t in_dscr_empty_int_ena:1;
/** infifo_ovf_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
*/
uint32_t infifo_ovf_int_ena:1;
/** infifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t infifo_udf_int_ena:1;
uint32_t reserved_7:25;
};
uint32_t val;
} gdma_in_int_ena_chn_reg_t;
/** Type of in_int_clr_chn register
* Interrupt clear bits of channel 0
*/
typedef union {
struct {
/** in_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the IN_DONE_CH_INT interrupt.
*/
uint32_t in_done_int_clr:1;
/** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
*/
uint32_t in_suc_eof_int_clr:1;
/** in_err_eof_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
*/
uint32_t in_err_eof_int_clr:1;
/** in_dscr_err_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
*/
uint32_t in_dscr_err_int_clr:1;
/** in_dscr_empty_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
*/
uint32_t in_dscr_empty_int_clr:1;
/** infifo_ovf_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
*/
uint32_t infifo_ovf_int_clr:1;
/** infifo_udf_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t infifo_udf_int_clr:1;
uint32_t reserved_7:25;
};
uint32_t val;
} gdma_in_int_clr_chn_reg_t;
/** Type of out_int_raw_chn register
* Raw status interrupt of channel 0
*/
typedef union {
struct {
/** out_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when the last data pointed by one outlink
* descriptor has been transmitted to peripherals for Tx channel 0.
*/
uint32_t out_done_int_raw:1;
/** out_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when the last data pointed by one outlink
* descriptor has been read from memory for Tx channel 0.
*/
uint32_t out_eof_int_raw:1;
/** out_dscr_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when detecting outlink descriptor error
* including owner error and the second and third word error of outlink descriptor for
* Tx channel 0.
*/
uint32_t out_dscr_err_int_raw:1;
/** out_total_eof_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt bit turns to high level when data corresponding a outlink
* (includes one link descriptor or few link descriptors) is transmitted out for Tx
* channel 0.
*/
uint32_t out_total_eof_int_raw:1;
/** outfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
* overflow.
*/
uint32_t outfifo_ovf_int_raw:1;
/** outfifo_udf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
* underflow.
*/
uint32_t outfifo_udf_int_raw:1;
uint32_t reserved_6:26;
};
uint32_t val;
} gdma_out_int_raw_chn_reg_t;
/** Type of out_int_st_chn register
* Masked interrupt of channel 0
*/
typedef union {
struct {
/** out_done_int_st : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
*/
uint32_t out_done_int_st:1;
/** out_eof_int_st : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
*/
uint32_t out_eof_int_st:1;
/** out_dscr_err_int_st : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
*/
uint32_t out_dscr_err_int_st:1;
/** out_total_eof_int_st : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
*/
uint32_t out_total_eof_int_st:1;
/** outfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
* The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
*/
uint32_t outfifo_ovf_int_st:1;
/** outfifo_udf_int_st : RO; bitpos: [5]; default: 0;
* The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t outfifo_udf_int_st:1;
uint32_t reserved_6:26;
};
uint32_t val;
} gdma_out_int_st_chn_reg_t;
/** Type of out_int_ena_chn register
* Interrupt enable bits of channel 0
*/
typedef union {
struct {
/** out_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
*/
uint32_t out_done_int_ena:1;
/** out_eof_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
*/
uint32_t out_eof_int_ena:1;
/** out_dscr_err_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
*/
uint32_t out_dscr_err_int_ena:1;
/** out_total_eof_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
*/
uint32_t out_total_eof_int_ena:1;
/** outfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
*/
uint32_t outfifo_ovf_int_ena:1;
/** outfifo_udf_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t outfifo_udf_int_ena:1;
uint32_t reserved_6:26;
};
uint32_t val;
} gdma_out_int_ena_chn_reg_t;
/** Type of out_int_clr_chn register
* Interrupt clear bits of channel 0
*/
typedef union {
struct {
/** out_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the OUT_DONE_CH_INT interrupt.
*/
uint32_t out_done_int_clr:1;
/** out_eof_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the OUT_EOF_CH_INT interrupt.
*/
uint32_t out_eof_int_clr:1;
/** out_dscr_err_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
*/
uint32_t out_dscr_err_int_clr:1;
/** out_total_eof_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
*/
uint32_t out_total_eof_int_clr:1;
/** outfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
*/
uint32_t outfifo_ovf_int_clr:1;
/** outfifo_udf_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t outfifo_udf_int_clr:1;
uint32_t reserved_6:26;
};
uint32_t val;
} gdma_out_int_clr_chn_reg_t;
/** Group: Debug Registers */
/** Type of ahb_test register
* reserved
*/
typedef union {
struct {
/** ahb_testmode : R/W; bitpos: [2:0]; default: 0;
* reserved
*/
uint32_t ahb_testmode:3;
uint32_t reserved_3:1;
/** ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
* reserved
*/
uint32_t ahb_testaddr:2;
uint32_t reserved_6:26;
};
uint32_t val;
} gdma_ahb_test_reg_t;
/** Group: Configuration Registers */
/** Type of misc_conf register
* MISC register
*/
typedef union {
struct {
/** ahbm_rst_inter : R/W; bitpos: [0]; default: 0;
* Set this bit then clear this bit to reset the internal ahb FSM.
*/
uint32_t ahbm_rst_inter:1;
uint32_t reserved_1:1;
/** arb_pri_dis : R/W; bitpos: [2]; default: 0;
* Set this bit to disable priority arbitration function.
*/
uint32_t arb_pri_dis:1;
/** clk_en : R/W; bitpos: [3]; default: 0;
* 1'h1: Force clock on for register. 1'h0: Support clock only when application writes
* registers.
*/
uint32_t clk_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} gdma_misc_conf_reg_t;
/** Type of in_conf0_chn register
* Configure 0 register of Rx channel 0
*/
typedef union {
struct {
/** in_rst : R/W; bitpos: [0]; default: 0;
* This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
*/
uint32_t in_rst:1;
/** in_loop_test : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t in_loop_test:1;
/** indscr_burst_en : R/W; bitpos: [2]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
* descriptor when accessing internal SRAM.
*/
uint32_t indscr_burst_en:1;
/** in_data_burst_en : R/W; bitpos: [3]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
* when accessing internal SRAM.
*/
uint32_t in_data_burst_en:1;
/** mem_trans_en : R/W; bitpos: [4]; default: 0;
* Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
*/
uint32_t mem_trans_en:1;
/** in_etm_en : R/W; bitpos: [5]; default: 0;
* Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
* task.
*/
uint32_t in_etm_en:1;
uint32_t reserved_6:26;
};
uint32_t val;
} gdma_in_conf0_chn_reg_t;
/** Type of in_conf1_chn register
* Configure 1 register of Rx channel 0
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** in_check_owner : R/W; bitpos: [12]; default: 0;
* Set this bit to enable checking the owner attribute of the link descriptor.
*/
uint32_t in_check_owner:1;
uint32_t reserved_13:19;
};
uint32_t val;
} gdma_in_conf1_chn_reg_t;
/** Type of in_pop_chn register
* Pop control register of Rx channel 0
*/
typedef union {
struct {
/** infifo_rdata : RO; bitpos: [11:0]; default: 2048;
* This register stores the data popping from DMA FIFO.
*/
uint32_t infifo_rdata:12;
/** infifo_pop : WT; bitpos: [12]; default: 0;
* Set this bit to pop data from DMA FIFO.
*/
uint32_t infifo_pop:1;
uint32_t reserved_13:19;
};
uint32_t val;
} gdma_in_pop_chn_reg_t;
/** Type of in_link_chn register
* Link descriptor configure and control register of Rx channel 0
*/
typedef union {
struct {
/** inlink_addr : R/W; bitpos: [19:0]; default: 0;
* This register stores the 20 least significant bits of the first inlink descriptor's
* address.
*/
uint32_t inlink_addr:20;
/** inlink_auto_ret : R/W; bitpos: [20]; default: 1;
* Set this bit to return to current inlink descriptor's address when there are some
* errors in current receiving data.
*/
uint32_t inlink_auto_ret:1;
/** inlink_stop : WT; bitpos: [21]; default: 0;
* Set this bit to stop dealing with the inlink descriptors.
*/
uint32_t inlink_stop:1;
/** inlink_start : WT; bitpos: [22]; default: 0;
* Set this bit to start dealing with the inlink descriptors.
*/
uint32_t inlink_start:1;
/** inlink_restart : WT; bitpos: [23]; default: 0;
* Set this bit to mount a new inlink descriptor.
*/
uint32_t inlink_restart:1;
/** inlink_park : RO; bitpos: [24]; default: 1;
* 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is
* working.
*/
uint32_t inlink_park:1;
uint32_t reserved_25:7;
};
uint32_t val;
} gdma_in_link_chn_reg_t;
/** Type of out_conf0_chn register
* Configure 0 register of Tx channel 0
*/
typedef union {
struct {
/** out_rst : R/W; bitpos: [0]; default: 0;
* This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
*/
uint32_t out_rst:1;
/** out_loop_test : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t out_loop_test:1;
/** out_auto_wrback : R/W; bitpos: [2]; default: 0;
* Set this bit to enable automatic outlink-writeback when all the data in tx buffer
* has been transmitted.
*/
uint32_t out_auto_wrback:1;
/** out_eof_mode : R/W; bitpos: [3]; default: 1;
* EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is
* generated when data need to transmit has been popped from FIFO in DMA
*/
uint32_t out_eof_mode:1;
/** outdscr_burst_en : R/W; bitpos: [4]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
* descriptor when accessing internal SRAM.
*/
uint32_t outdscr_burst_en:1;
/** out_data_burst_en : R/W; bitpos: [5]; default: 0;
* Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data
* when accessing internal SRAM.
*/
uint32_t out_data_burst_en:1;
/** out_etm_en : R/W; bitpos: [6]; default: 0;
* Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm
* task.
*/
uint32_t out_etm_en:1;
uint32_t reserved_7:25;
};
uint32_t val;
} gdma_out_conf0_chn_reg_t;
/** Type of out_conf1_chn register
* Configure 1 register of Tx channel 0
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** out_check_owner : R/W; bitpos: [12]; default: 0;
* Set this bit to enable checking the owner attribute of the link descriptor.
*/
uint32_t out_check_owner:1;
uint32_t reserved_13:19;
};
uint32_t val;
} gdma_out_conf1_chn_reg_t;
/** Type of out_push_chn register
* Push control register of Rx channel 0
*/
typedef union {
struct {
/** outfifo_wdata : R/W; bitpos: [8:0]; default: 0;
* This register stores the data that need to be pushed into DMA FIFO.
*/
uint32_t outfifo_wdata:9;
/** outfifo_push : WT; bitpos: [9]; default: 0;
* Set this bit to push data into DMA FIFO.
*/
uint32_t outfifo_push:1;
uint32_t reserved_10:22;
};
uint32_t val;
} gdma_out_push_chn_reg_t;
/** Type of out_link_chn register
* Link descriptor configure and control register of Tx channel 0
*/
typedef union {
struct {
/** outlink_addr : R/W; bitpos: [19:0]; default: 0;
* This register stores the 20 least significant bits of the first outlink
* descriptor's address.
*/
uint32_t outlink_addr:20;
/** outlink_stop : WT; bitpos: [20]; default: 0;
* Set this bit to stop dealing with the outlink descriptors.
*/
uint32_t outlink_stop:1;
/** outlink_start : WT; bitpos: [21]; default: 0;
* Set this bit to start dealing with the outlink descriptors.
*/
uint32_t outlink_start:1;
/** outlink_restart : WT; bitpos: [22]; default: 0;
* Set this bit to restart a new outlink from the last address.
*/
uint32_t outlink_restart:1;
/** outlink_park : RO; bitpos: [23]; default: 1;
* 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM
* is working.
*/
uint32_t outlink_park:1;
uint32_t reserved_24:8;
};
uint32_t val;
} gdma_out_link_chn_reg_t;
/** Group: Version Registers */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 35660368;
* register version.
*/
uint32_t date:32;
};
uint32_t val;
} gdma_date_reg_t;
/** Group: Status Registers */
/** Type of infifo_status_chn register
* Receive FIFO status of Rx channel 0
*/
typedef union {
struct {
/** infifo_full : RO; bitpos: [0]; default: 1;
* L1 Rx FIFO full signal for Rx channel 0.
*/
uint32_t infifo_full:1;
/** infifo_empty : RO; bitpos: [1]; default: 1;
* L1 Rx FIFO empty signal for Rx channel 0.
*/
uint32_t infifo_empty:1;
/** infifo_cnt : RO; bitpos: [7:2]; default: 0;
* The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
*/
uint32_t infifo_cnt:6;
uint32_t reserved_8:15;
/** in_remain_under_1b : RO; bitpos: [23]; default: 1;
* reserved
*/
uint32_t in_remain_under_1b:1;
/** in_remain_under_2b : RO; bitpos: [24]; default: 1;
* reserved
*/
uint32_t in_remain_under_2b:1;
/** in_remain_under_3b : RO; bitpos: [25]; default: 1;
* reserved
*/
uint32_t in_remain_under_3b:1;
/** in_remain_under_4b : RO; bitpos: [26]; default: 1;
* reserved
*/
uint32_t in_remain_under_4b:1;
/** in_buf_hungry : RO; bitpos: [27]; default: 0;
* reserved
*/
uint32_t in_buf_hungry:1;
uint32_t reserved_28:4;
};
uint32_t val;
} gdma_infifo_status_chn_reg_t;
/** Type of in_state_chn register
* Receive status of Rx channel 0
*/
typedef union {
struct {
/** inlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
* This register stores the current inlink descriptor's address.
*/
uint32_t inlink_dscr_addr:18;
/** in_dscr_state : RO; bitpos: [19:18]; default: 0;
* reserved
*/
uint32_t in_dscr_state:2;
/** in_state : RO; bitpos: [22:20]; default: 0;
* reserved
*/
uint32_t in_state:3;
uint32_t reserved_23:9;
};
uint32_t val;
} gdma_in_state_chn_reg_t;
/** Type of in_suc_eof_des_addr_chn register
* Inlink descriptor address when EOF occurs of Rx channel 0
*/
typedef union {
struct {
/** in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
* This register stores the address of the inlink descriptor when the EOF bit in this
* descriptor is 1.
*/
uint32_t in_suc_eof_des_addr:32;
};
uint32_t val;
} gdma_in_suc_eof_des_addr_chn_reg_t;
/** Type of in_err_eof_des_addr_chn register
* Inlink descriptor address when errors occur of Rx channel 0
*/
typedef union {
struct {
/** in_err_eof_des_addr : RO; bitpos: [31:0]; default: 0;
* This register stores the address of the inlink descriptor when there are some
* errors in current receiving data. Only used when peripheral is UHCI0.
*/
uint32_t in_err_eof_des_addr:32;
};
uint32_t val;
} gdma_in_err_eof_des_addr_chn_reg_t;
/** Type of in_dscr_chn register
* Current inlink descriptor address of Rx channel 0
*/
typedef union {
struct {
/** inlink_dscr : RO; bitpos: [31:0]; default: 0;
* The address of the current inlink descriptor x.
*/
uint32_t inlink_dscr:32;
};
uint32_t val;
} gdma_in_dscr_chn_reg_t;
/** Type of in_dscr_bf0_chn register
* The last inlink descriptor address of Rx channel 0
*/
typedef union {
struct {
/** inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
* The address of the last inlink descriptor x-1.
*/
uint32_t inlink_dscr_bf0:32;
};
uint32_t val;
} gdma_in_dscr_bf0_chn_reg_t;
/** Type of in_dscr_bf1_chn register
* The second-to-last inlink descriptor address of Rx channel 0
*/
typedef union {
struct {
/** inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
* The address of the second-to-last inlink descriptor x-2.
*/
uint32_t inlink_dscr_bf1:32;
};
uint32_t val;
} gdma_in_dscr_bf1_chn_reg_t;
/** Type of outfifo_status_chn register
* Transmit FIFO status of Tx channel 0
*/
typedef union {
struct {
/** outfifo_full : RO; bitpos: [0]; default: 0;
* L1 Tx FIFO full signal for Tx channel 0.
*/
uint32_t outfifo_full:1;
/** outfifo_empty : RO; bitpos: [1]; default: 1;
* L1 Tx FIFO empty signal for Tx channel 0.
*/
uint32_t outfifo_empty:1;
/** outfifo_cnt : RO; bitpos: [7:2]; default: 0;
* The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
*/
uint32_t outfifo_cnt:6;
uint32_t reserved_8:15;
/** out_remain_under_1b : RO; bitpos: [23]; default: 1;
* reserved
*/
uint32_t out_remain_under_1b:1;
/** out_remain_under_2b : RO; bitpos: [24]; default: 1;
* reserved
*/
uint32_t out_remain_under_2b:1;
/** out_remain_under_3b : RO; bitpos: [25]; default: 1;
* reserved
*/
uint32_t out_remain_under_3b:1;
/** out_remain_under_4b : RO; bitpos: [26]; default: 1;
* reserved
*/
uint32_t out_remain_under_4b:1;
uint32_t reserved_27:5;
};
uint32_t val;
} gdma_outfifo_status_chn_reg_t;
/** Type of out_state_chn register
* Transmit status of Tx channel 0
*/
typedef union {
struct {
/** outlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
* This register stores the current outlink descriptor's address.
*/
uint32_t outlink_dscr_addr:18;
/** out_dscr_state : RO; bitpos: [19:18]; default: 0;
* reserved
*/
uint32_t out_dscr_state:2;
/** out_state : RO; bitpos: [22:20]; default: 0;
* reserved
*/
uint32_t out_state:3;
uint32_t reserved_23:9;
};
uint32_t val;
} gdma_out_state_chn_reg_t;
/** Type of out_eof_des_addr_chn register
* Outlink descriptor address when EOF occurs of Tx channel 0
*/
typedef union {
struct {
/** out_eof_des_addr : RO; bitpos: [31:0]; default: 0;
* This register stores the address of the outlink descriptor when the EOF bit in this
* descriptor is 1.
*/
uint32_t out_eof_des_addr:32;
};
uint32_t val;
} gdma_out_eof_des_addr_chn_reg_t;
/** Type of out_eof_bfr_des_addr_chn register
* The last outlink descriptor address when EOF occurs of Tx channel 0
*/
typedef union {
struct {
/** out_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
* This register stores the address of the outlink descriptor before the last outlink
* descriptor.
*/
uint32_t out_eof_bfr_des_addr:32;
};
uint32_t val;
} gdma_out_eof_bfr_des_addr_chn_reg_t;
/** Type of out_dscr_chn register
* Current inlink descriptor address of Tx channel 0
*/
typedef union {
struct {
/** outlink_dscr : RO; bitpos: [31:0]; default: 0;
* The address of the current outlink descriptor y.
*/
uint32_t outlink_dscr:32;
};
uint32_t val;
} gdma_out_dscr_chn_reg_t;
/** Type of out_dscr_bf0_chn register
* The last inlink descriptor address of Tx channel 0
*/
typedef union {
struct {
/** outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
* The address of the last outlink descriptor y-1.
*/
uint32_t outlink_dscr_bf0:32;
};
uint32_t val;
} gdma_out_dscr_bf0_chn_reg_t;
/** Type of out_dscr_bf1_chn register
* The second-to-last inlink descriptor address of Tx channel 0
*/
typedef union {
struct {
/** outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
* The address of the second-to-last inlink descriptor x-2.
*/
uint32_t outlink_dscr_bf1:32;
};
uint32_t val;
} gdma_out_dscr_bf1_chn_reg_t;
/** Group: Priority Registers */
/** Type of in_pri_chn register
* Priority register of Rx channel 0
*/
typedef union {
struct {
/** rx_pri : R/W; bitpos: [3:0]; default: 0;
* The priority of Rx channel 0. The larger of the value the higher of the priority.
*/
uint32_t rx_pri:4;
uint32_t reserved_4:28;
};
uint32_t val;
} gdma_in_pri_chn_reg_t;
/** Type of out_pri_chn register
* Priority register of Tx channel 0.
*/
typedef union {
struct {
/** tx_pri : R/W; bitpos: [3:0]; default: 0;
* The priority of Tx channel 0. The larger of the value the higher of the priority.
*/
uint32_t tx_pri:4;
uint32_t reserved_4:28;
};
uint32_t val;
} gdma_out_pri_chn_reg_t;
/** Group: Peripheral Select Registers */
/** Type of in_peri_sel_chn register
* Peripheral selection of Rx channel 0
*/
typedef union {
struct {
/** peri_in_sel : R/W; bitpos: [5:0]; default: 63;
* This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved.
* 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9:
* Parallel_IO.
*/
uint32_t peri_in_sel:6;
uint32_t reserved_6:26;
};
uint32_t val;
} gdma_in_peri_sel_chn_reg_t;
/** Type of out_peri_sel_chn register
* Peripheral selection of Tx channel 0
*/
typedef union {
struct {
/** peri_out_sel : R/W; bitpos: [5:0]; default: 63;
* This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved.
* 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 9:
* Parallel_IO.
*/
uint32_t peri_out_sel:6;
uint32_t reserved_6:26;
};
uint32_t val;
} gdma_out_peri_sel_chn_reg_t;
typedef struct {
volatile gdma_in_int_raw_chn_reg_t raw;
volatile gdma_in_int_st_chn_reg_t st;
volatile gdma_in_int_ena_chn_reg_t ena;
volatile gdma_in_int_clr_chn_reg_t clr;
} gdma_in_int_chn_reg_t;
typedef struct {
volatile gdma_out_int_raw_chn_reg_t raw;
volatile gdma_out_int_st_chn_reg_t st;
volatile gdma_out_int_ena_chn_reg_t ena;
volatile gdma_out_int_clr_chn_reg_t clr;
} gdma_out_int_chn_reg_t;
typedef struct {
volatile gdma_in_conf0_chn_reg_t in_conf0;
volatile gdma_in_conf1_chn_reg_t in_conf1;
volatile gdma_infifo_status_chn_reg_t infifo_status;
volatile gdma_in_pop_chn_reg_t in_pop;
volatile gdma_in_link_chn_reg_t in_link;
volatile gdma_in_state_chn_reg_t in_state;
volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
volatile gdma_in_dscr_chn_reg_t in_dscr;
volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
volatile gdma_in_pri_chn_reg_t in_pri;
volatile gdma_in_peri_sel_chn_reg_t in_peri_sel;
} gdma_in_chn_reg_t;
typedef struct {
volatile gdma_out_conf0_chn_reg_t out_conf0;
volatile gdma_out_conf1_chn_reg_t out_conf1;
volatile gdma_outfifo_status_chn_reg_t outfifo_status;
volatile gdma_out_push_chn_reg_t out_push;
volatile gdma_out_link_chn_reg_t out_link;
volatile gdma_out_state_chn_reg_t out_state;
volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
volatile gdma_out_dscr_chn_reg_t out_dscr;
volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
volatile gdma_out_pri_chn_reg_t out_pri;
volatile gdma_out_peri_sel_chn_reg_t out_peri_sel;
} gdma_out_chn_reg_t;
typedef struct {
volatile gdma_in_chn_reg_t in;
uint32_t reserved_in[11];
volatile gdma_out_chn_reg_t out;
uint32_t reserved_out[11];
} gdma_chn_reg_t;
typedef struct gdma_dev_s {
volatile gdma_in_int_chn_reg_t in_intr[3];
volatile gdma_out_int_chn_reg_t out_intr[3];
volatile gdma_ahb_test_reg_t ahb_test;
volatile gdma_misc_conf_reg_t misc_conf;
volatile gdma_date_reg_t date;
uint32_t reserved_06c;
volatile gdma_chn_reg_t channel[3];
} gdma_dev_t;
extern gdma_dev_t GDMA;
#ifndef __cplusplus
_Static_assert(sizeof(gdma_dev_t) == 0x2B0, "Invalid size of gdma_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadelta_chn register
* Duty Cycle Configure Register of SDMn
*/
typedef union {
struct {
/** duty : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t duty:8;
/** prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t prescale:8;
uint32_t reserved_16:16;
};
uint32_t val;
} gpio_sigmadelta_chn_reg_t;
/** Type of sigmadelta_misc register
* MISC Register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** function_clk_en : R/W; bitpos: [30]; default: 0;
* Clock enable bit of sigma delta modulation.
*/
uint32_t function_clk_en:1;
/** spi_swap : R/W; bitpos: [31]; default: 0;
* Reserved.
*/
uint32_t spi_swap:1;
};
uint32_t val;
} gpio_sigmadelta_misc_reg_t;
/** Group: Clock gate Register */
/** Type of clock_gate register
* Clock Gating Configure Register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Clock enable bit of configuration registers for sigma delta modulation.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} gpio_sigmadelta_clock_gate_reg_t;
/** Group: Glitch filter Configure Registers */
/** Type of glitch_filter_chn register
* Glitch Filter Configure Register of Channeln
*/
typedef union {
struct {
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t filter_ch0_en:1;
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t filter_ch0_input_io_num:6;
/** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t filter_ch0_window_thres:6;
/** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
* Glitch Filter window width.
*/
uint32_t filter_ch0_window_width:6;
uint32_t reserved_19:13;
};
uint32_t val;
} gpio_glitch_filter_chn_reg_t;
/** Group: Etm Configure Registers */
/** Type of etm_event_chn_cfg register
* Etm Config register of Channeln
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_ch0_event_sel:5;
uint32_t reserved_5:2;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_ch0_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_etm_event_chn_cfg_reg_t;
/** Type of etm_task_p0_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio0_en:1;
/** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio0_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio1_en:1;
/** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio1_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio2_en:1;
/** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio2_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio3_en:1;
/** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio3_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_etm_task_p0_cfg_reg_t;
/** Type of etm_task_p1_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio4_en:1;
/** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio4_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio5_en:1;
/** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio5_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio6_en:1;
/** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio6_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio7_en:1;
/** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio7_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_etm_task_p1_cfg_reg_t;
/** Type of etm_task_p2_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio8_en:1;
/** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio8_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio9_en:1;
/** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio9_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio10_en:1;
/** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio10_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio11_en:1;
/** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio11_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_etm_task_p2_cfg_reg_t;
/** Type of etm_task_p3_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio12_en:1;
/** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio12_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio13_en:1;
/** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio13_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio14_en:1;
/** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio14_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio15_en:1;
/** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio15_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_etm_task_p3_cfg_reg_t;
/** Type of etm_task_p4_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio16_en:1;
/** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio16_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio17_en:1;
/** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio17_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio18_en:1;
/** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio18_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio19_en:1;
/** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio19_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_etm_task_p4_cfg_reg_t;
/** Type of etm_task_p5_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio20_en:1;
/** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio20_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio21_en:1;
/** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio21_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio22_en:1;
/** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio22_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio23_en:1;
/** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio23_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_etm_task_p5_cfg_reg_t;
/** Type of etm_task_p6_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio24_en:1;
/** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio24_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio25_en:1;
/** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio25_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio26_en:1;
/** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio26_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio27_en:1;
/** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio27_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_etm_task_p6_cfg_reg_t;
/** Type of etm_task_p7_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio28_en:1;
/** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio28_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio29_en:1;
/** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio29_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio30_en:1;
/** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio30_sel:3;
uint32_t reserved_20:12;
};
uint32_t val;
} gpio_etm_task_p7_cfg_reg_t;
/** Group: Version Register */
/** Type of version register
* Version Control Register
*/
typedef union {
struct {
/** gpio_ext_date : R/W; bitpos: [27:0]; default: 35663952;
* Version control register.
*/
uint32_t gpio_ext_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_ext_version_reg_t;
typedef struct gpio_sd_dev_t {
volatile gpio_sigmadelta_chn_reg_t channel[4];
uint32_t reserved_010[4];
volatile gpio_sigmadelta_clock_gate_reg_t clock_gate;
volatile gpio_sigmadelta_misc_reg_t misc;
} gpio_sd_dev_t;
typedef struct {
volatile gpio_glitch_filter_chn_reg_t glitch_filter_chn[8];
} gpio_glitch_filter_dev_t;
typedef struct {
volatile gpio_etm_event_chn_cfg_reg_t event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpio_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
volatile gpio_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
volatile gpio_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
volatile gpio_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
volatile gpio_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
volatile gpio_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
volatile gpio_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
volatile gpio_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
} gpio_etm_dev_t;
typedef struct gpio_ext_dev_t {
volatile gpio_sd_dev_t sigma_delta;
uint32_t reserved_028[2];
volatile gpio_glitch_filter_dev_t glitch_filter;
uint32_t reserved_050[4];
volatile gpio_etm_dev_t etm;
uint32_t reserved_0c0[15];
volatile gpio_ext_version_reg_t version;
} gpio_ext_dev_t;
extern gpio_sd_dev_t SDM;
extern gpio_glitch_filter_dev_t GLITCH_FILTER;
extern gpio_etm_dev_t GPIO_ETM;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define EXT_ADC_START_IDX 0
#define LEDC_LS_SIG_OUT0_IDX 0
#define LEDC_LS_SIG_OUT1_IDX 1
#define LEDC_LS_SIG_OUT2_IDX 2
#define LEDC_LS_SIG_OUT3_IDX 3
#define LEDC_LS_SIG_OUT4_IDX 4
#define LEDC_LS_SIG_OUT5_IDX 5
#define U0RXD_IN_IDX 6
#define U0TXD_OUT_IDX 6
#define U0CTS_IN_IDX 7
#define U0RTS_OUT_IDX 7
#define U0DSR_IN_IDX 8
#define U0DTR_OUT_IDX 8
#define U1RXD_IN_IDX 9
#define U1TXD_OUT_IDX 9
#define U1CTS_IN_IDX 10
#define U1RTS_OUT_IDX 10
#define U1DSR_IN_IDX 11
#define U1DTR_OUT_IDX 11
#define I2S_MCLK_IN_IDX 12
#define I2S_MCLK_OUT_IDX 12
#define I2SO_BCK_IN_IDX 13
#define I2SO_BCK_OUT_IDX 13
#define I2SO_WS_IN_IDX 14
#define I2SO_WS_OUT_IDX 14
#define I2SI_SD_IN_IDX 15
#define I2SO_SD_OUT_IDX 15
#define I2SI_BCK_IN_IDX 16
#define I2SI_BCK_OUT_IDX 16
#define I2SI_WS_IN_IDX 17
#define I2SI_WS_OUT_IDX 17
#define I2SO_SD1_OUT_IDX 18
#define USB_JTAG_TDO_BRIDGE_IDX 19
#define USB_JTAG_TRST_IDX 19
#define CPU_TESTBUS0_IDX 20
#define CPU_TESTBUS1_IDX 21
#define CPU_TESTBUS2_IDX 22
#define CPU_TESTBUS3_IDX 23
#define CPU_TESTBUS4_IDX 24
#define CPU_TESTBUS5_IDX 25
#define CPU_TESTBUS6_IDX 26
#define CPU_TESTBUS7_IDX 27
#define CPU_GPIO_IN0_IDX 28
#define CPU_GPIO_OUT0_IDX 28
#define CPU_GPIO_IN1_IDX 29
#define CPU_GPIO_OUT1_IDX 29
#define CPU_GPIO_IN2_IDX 30
#define CPU_GPIO_OUT2_IDX 30
#define CPU_GPIO_IN3_IDX 31
#define CPU_GPIO_OUT3_IDX 31
#define CPU_GPIO_IN4_IDX 32
#define CPU_GPIO_OUT4_IDX 32
#define CPU_GPIO_IN5_IDX 33
#define CPU_GPIO_OUT5_IDX 33
#define CPU_GPIO_IN6_IDX 34
#define CPU_GPIO_OUT6_IDX 34
#define CPU_GPIO_IN7_IDX 35
#define CPU_GPIO_OUT7_IDX 35
#define USB_JTAG_TCK_IDX 36
#define USB_JTAG_TMS_IDX 37
#define USB_JTAG_TDI_IDX 38
#define USB_JTAG_TDO_IDX 39
#define USB_EXTPHY_VP_IDX 40
#define USB_EXTPHY_OEN_IDX 40
#define USB_EXTPHY_VM_IDX 41
#define USB_EXTPHY_SPEED_IDX 41
#define USB_EXTPHY_RCV_IDX 42
#define USB_EXTPHY_VPO_IDX 42
#define USB_EXTPHY_VMO_IDX 43
#define USB_EXTPHY_SUSPND_IDX 44
#define I2CEXT0_SCL_IN_IDX 45
#define I2CEXT0_SCL_OUT_IDX 45
#define I2CEXT0_SDA_IN_IDX 46
#define I2CEXT0_SDA_OUT_IDX 46
#define PARL_RX_DATA0_IDX 47
#define PARL_TX_DATA0_IDX 47
#define PARL_RX_DATA1_IDX 48
#define PARL_TX_DATA1_IDX 48
#define PARL_RX_DATA2_IDX 49
#define PARL_TX_DATA2_IDX 49
#define PARL_RX_DATA3_IDX 50
#define PARL_TX_DATA3_IDX 50
#define PARL_RX_DATA4_IDX 51
#define PARL_TX_DATA4_IDX 51
#define PARL_RX_DATA5_IDX 52
#define PARL_TX_DATA5_IDX 52
#define PARL_RX_DATA6_IDX 53
#define PARL_TX_DATA6_IDX 53
#define PARL_RX_DATA7_IDX 54
#define PARL_TX_DATA7_IDX 54
#define PARL_RX_DATA8_IDX 55
#define PARL_TX_DATA8_IDX 55
#define PARL_RX_DATA9_IDX 56
#define PARL_TX_DATA9_IDX 56
#define PARL_RX_DATA10_IDX 57
#define PARL_TX_DATA10_IDX 57
#define PARL_RX_DATA11_IDX 58
#define PARL_TX_DATA11_IDX 58
#define PARL_RX_DATA12_IDX 59
#define PARL_TX_DATA12_IDX 59
#define PARL_RX_DATA13_IDX 60
#define PARL_TX_DATA13_IDX 60
#define PARL_RX_DATA14_IDX 61
#define PARL_TX_DATA14_IDX 61
#define PARL_RX_DATA15_IDX 62
#define PARL_TX_DATA15_IDX 62
#define FSPICLK_IN_IDX 63
#define FSPICLK_OUT_IDX 63
#define FSPIQ_IN_IDX 64
#define FSPIQ_OUT_IDX 64
#define FSPID_IN_IDX 65
#define FSPID_OUT_IDX 65
#define FSPIHD_IN_IDX 66
#define FSPIHD_OUT_IDX 66
#define FSPIWP_IN_IDX 67
#define FSPIWP_OUT_IDX 67
#define FSPICS0_IN_IDX 68
#define FSPICS0_OUT_IDX 68
#define PARL_RX_CLK_IN_IDX 69
#define SDIO_TOHOST_INT_OUT_IDX 69
#define PARL_TX_CLK_IN_IDX 70
#define PARL_TX_CLK_OUT_IDX 70
#define RMT_SIG_IN0_IDX 71
#define RMT_SIG_OUT0_IDX 71
#define MODEM_DIAG0_IDX 71
#define RMT_SIG_IN1_IDX 72
#define RMT_SIG_OUT1_IDX 72
#define MODEM_DIAG1_IDX 72
#define TWAI0_RX_IDX 73
#define TWAI0_TX_IDX 73
#define MODEM_DIAG2_IDX 73
#define TWAI0_BUS_OFF_ON_IDX 74
#define MODEM_DIAG3_IDX 74
#define TWAI0_CLKOUT_IDX 75
#define MODEM_DIAG4_IDX 75
#define TWAI0_STANDBY_IDX 76
#define MODEM_DIAG5_IDX 76
#define TWAI1_RX_IDX 77
#define TWAI1_TX_IDX 77
#define MODEM_DIAG6_IDX 77
#define TWAI1_BUS_OFF_ON_IDX 78
#define MODEM_DIAG7_IDX 78
#define TWAI1_CLKOUT_IDX 79
#define MODEM_DIAG8_IDX 79
#define TWAI1_STANDBY_IDX 80
#define MODEM_DIAG9_IDX 80
#define EXTERN_PRIORITY_I_IDX 81
#define EXTERN_PRIORITY_O_IDX 81
#define EXTERN_ACTIVE_I_IDX 82
#define EXTERN_ACTIVE_O_IDX 82
#define GPIO_SD0_OUT_IDX 83
#define GPIO_SD1_OUT_IDX 84
#define GPIO_SD2_OUT_IDX 85
#define GPIO_SD3_OUT_IDX 86
#define PWM0_SYNC0_IN_IDX 87
#define PWM0_OUT0A_IDX 87
#define MODEM_DIAG10_IDX 87
#define PWM0_SYNC1_IN_IDX 88
#define PWM0_OUT0B_IDX 88
#define MODEM_DIAG11_IDX 88
#define PWM0_SYNC2_IN_IDX 89
#define PWM0_OUT1A_IDX 89
#define MODEM_DIAG12_IDX 89
#define PWM0_F0_IN_IDX 90
#define PWM0_OUT1B_IDX 90
#define MODEM_DIAG13_IDX 90
#define PWM0_F1_IN_IDX 91
#define PWM0_OUT2A_IDX 91
#define MODEM_DIAG14_IDX 91
#define PWM0_F2_IN_IDX 92
#define PWM0_OUT2B_IDX 92
#define MODEM_DIAG15_IDX 92
#define PWM0_CAP0_IN_IDX 93
#define ANT_SEL0_IDX 93
#define PWM0_CAP1_IN_IDX 94
#define ANT_SEL1_IDX 94
#define PWM0_CAP2_IN_IDX 95
#define ANT_SEL2_IDX 95
#define ANT_SEL3_IDX 96
#define SIG_IN_FUNC_97_IDX 97
#define SIG_IN_FUNC97_IDX 97
#define SIG_IN_FUNC_98_IDX 98
#define SIG_IN_FUNC98_IDX 98
#define SIG_IN_FUNC_99_IDX 99
#define SIG_IN_FUNC99_IDX 99
#define SIG_IN_FUNC_100_IDX 100
#define SIG_IN_FUNC100_IDX 100
#define PCNT_SIG_CH0_IN0_IDX 101
#define FSPICS1_OUT_IDX 101
#define MODEM_DIAG16_IDX 101
#define PCNT_SIG_CH1_IN0_IDX 102
#define FSPICS2_OUT_IDX 102
#define MODEM_DIAG17_IDX 102
#define PCNT_CTRL_CH0_IN0_IDX 103
#define FSPICS3_OUT_IDX 103
#define MODEM_DIAG18_IDX 103
#define PCNT_CTRL_CH1_IN0_IDX 104
#define FSPICS4_OUT_IDX 104
#define MODEM_DIAG19_IDX 104
#define PCNT_SIG_CH0_IN1_IDX 105
#define FSPICS5_OUT_IDX 105
#define MODEM_DIAG20_IDX 105
#define PCNT_SIG_CH1_IN1_IDX 106
#define MODEM_DIAG21_IDX 106
#define PCNT_CTRL_CH0_IN1_IDX 107
#define MODEM_DIAG22_IDX 107
#define PCNT_CTRL_CH1_IN1_IDX 108
#define MODEM_DIAG23_IDX 108
#define PCNT_SIG_CH0_IN2_IDX 109
#define MODEM_DIAG24_IDX 109
#define PCNT_SIG_CH1_IN2_IDX 110
#define MODEM_DIAG25_IDX 110
#define PCNT_CTRL_CH0_IN2_IDX 111
#define MODEM_DIAG26_IDX 111
#define PCNT_CTRL_CH1_IN2_IDX 112
#define MODEM_DIAG27_IDX 112
#define PCNT_SIG_CH0_IN3_IDX 113
#define MODEM_DIAG28_IDX 113
#define PCNT_SIG_CH1_IN3_IDX 114
#define SPICLK_OUT_IDX 114
#define MODEM_DIAG29_IDX 114
#define PCNT_CTRL_CH0_IN3_IDX 115
#define SPICS0_OUT_IDX 115
#define MODEM_DIAG30_IDX 115
#define PCNT_CTRL_CH1_IN3_IDX 116
#define SPICS1_OUT_IDX 116
#define MODEM_DIAG31_IDX 116
#define GPIO_EVENT_MATRIX_IN0_IDX 117
#define GPIO_TASK_MATRIX_OUT0_IDX 117
#define GPIO_EVENT_MATRIX_IN1_IDX 118
#define GPIO_TASK_MATRIX_OUT1_IDX 118
#define GPIO_EVENT_MATRIX_IN2_IDX 119
#define GPIO_TASK_MATRIX_OUT2_IDX 119
#define GPIO_EVENT_MATRIX_IN3_IDX 120
#define GPIO_TASK_MATRIX_OUT3_IDX 120
#define SPIQ_IN_IDX 121
#define SPIQ_OUT_IDX 121
#define SPID_IN_IDX 122
#define SPID_OUT_IDX 122
#define SPIHD_IN_IDX 123
#define SPIHD_OUT_IDX 123
#define SPIWP_IN_IDX 124
#define SPIWP_OUT_IDX 124
#define CLK_OUT_OUT1_IDX 125
#define CLK_OUT_OUT2_IDX 126
#define CLK_OUT_OUT3_IDX 127
#define SIG_GPIO_OUT_IDX 128
#define GPIO_MAP_DATE_IDX 0x2201120
#endif /* _SOC_GPIO_SIG_MAP_H_ */

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration register */
/** Type of bt_select register
* GPIO bit select register
*/
typedef union {
struct {
/** bt_sel : R/W; bitpos: [31:0]; default: 0;
* GPIO bit select register
*/
uint32_t bt_sel:32;
};
uint32_t val;
} gpio_bt_select_reg_t;
/** Type of out register
* GPIO output register for GPIO0-31
*/
typedef union {
struct {
/** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
* GPIO output register for GPIO0-31
*/
uint32_t out_data_orig:32;
};
uint32_t val;
} gpio_out_reg_t;
/** Type of out_w1ts register
* GPIO output set register for GPIO0-31
*/
typedef union {
struct {
/** out_w1ts : WT; bitpos: [31:0]; default: 0;
* GPIO output set register for GPIO0-31
*/
uint32_t out_w1ts:32;
};
uint32_t val;
} gpio_out_w1ts_reg_t;
/** Type of out_w1tc register
* GPIO output clear register for GPIO0-31
*/
typedef union {
struct {
/** out_w1tc : WT; bitpos: [31:0]; default: 0;
* GPIO output clear register for GPIO0-31
*/
uint32_t out_w1tc:32;
};
uint32_t val;
} gpio_out_w1tc_reg_t;
/** Type of out1 register
* GPIO output register for GPIO32-34
*/
typedef union {
struct {
/** out1_data_orig : R/W/SC/WTC; bitpos: [2:0]; default: 0;
* GPIO output register for GPIO32-34
*/
uint32_t out1_data_orig:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_out1_reg_t;
/** Type of out1_w1ts register
* GPIO output set register for GPIO32-34
*/
typedef union {
struct {
/** out1_w1ts : WT; bitpos: [2:0]; default: 0;
* GPIO output set register for GPIO32-34
*/
uint32_t out1_w1ts:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_out1_w1ts_reg_t;
/** Type of out1_w1tc register
* GPIO output clear register for GPIO32-34
*/
typedef union {
struct {
/** out1_w1tc : WT; bitpos: [2:0]; default: 0;
* GPIO output clear register for GPIO32-34
*/
uint32_t out1_w1tc:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_out1_w1tc_reg_t;
/** Type of sdio_select register
* GPIO sdio select register
*/
typedef union {
struct {
/** sdio_sel : R/W; bitpos: [7:0]; default: 0;
* GPIO sdio select register
*/
uint32_t sdio_sel:8;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_sdio_select_reg_t;
/** Type of enable register
* GPIO output enable register for GPIO0-31
*/
typedef union {
struct {
/** enable_data : R/W/WTC; bitpos: [31:0]; default: 0;
* GPIO output enable register for GPIO0-31
*/
uint32_t enable_data:32;
};
uint32_t val;
} gpio_enable_reg_t;
/** Type of enable_w1ts register
* GPIO output enable set register for GPIO0-31
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [31:0]; default: 0;
* GPIO output enable set register for GPIO0-31
*/
uint32_t enable_w1ts:32;
};
uint32_t val;
} gpio_enable_w1ts_reg_t;
/** Type of enable_w1tc register
* GPIO output enable clear register for GPIO0-31
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [31:0]; default: 0;
* GPIO output enable clear register for GPIO0-31
*/
uint32_t enable_w1tc:32;
};
uint32_t val;
} gpio_enable_w1tc_reg_t;
/** Type of enable1 register
* GPIO output enable register for GPIO32-34
*/
typedef union {
struct {
/** enable1_data : R/W/WTC; bitpos: [2:0]; default: 0;
* GPIO output enable register for GPIO32-34
*/
uint32_t enable1_data:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_enable1_reg_t;
/** Type of enable1_w1ts register
* GPIO output enable set register for GPIO32-34
*/
typedef union {
struct {
/** enable1_w1ts : WT; bitpos: [2:0]; default: 0;
* GPIO output enable set register for GPIO32-34
*/
uint32_t enable1_w1ts:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_enable1_w1ts_reg_t;
/** Type of enable1_w1tc register
* GPIO output enable clear register for GPIO32-34
*/
typedef union {
struct {
/** enable1_w1tc : WT; bitpos: [2:0]; default: 0;
* GPIO output enable clear register for GPIO32-34
*/
uint32_t enable1_w1tc:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_enable1_w1tc_reg_t;
/** Type of strap register
* pad strapping register
*/
typedef union {
struct {
/** strapping : RO; bitpos: [15:0]; default: 0;
* pad strapping register
*/
uint32_t strapping:16;
uint32_t reserved_16:16;
};
uint32_t val;
} gpio_strap_reg_t;
/** Type of in register
* GPIO input register for GPIO0-31
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [31:0]; default: 0;
* GPIO input register for GPIO0-31
*/
uint32_t in_data_next:32;
};
uint32_t val;
} gpio_in_reg_t;
/** Type of in1 register
* GPIO input register for GPIO32-34
*/
typedef union {
struct {
/** in1_data_next : RO; bitpos: [2:0]; default: 0;
* GPIO input register for GPIO32-34
*/
uint32_t in1_data_next:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_in1_reg_t;
/** Type of status register
* GPIO interrupt status register for GPIO0-31
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
* GPIO interrupt status register for GPIO0-31
*/
uint32_t status_interrupt:32;
};
uint32_t val;
} gpio_status_reg_t;
/** Type of status_w1ts register
* GPIO interrupt status set register for GPIO0-31
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [31:0]; default: 0;
* GPIO interrupt status set register for GPIO0-31
*/
uint32_t status_w1ts:32;
};
uint32_t val;
} gpio_status_w1ts_reg_t;
/** Type of status_w1tc register
* GPIO interrupt status clear register for GPIO0-31
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [31:0]; default: 0;
* GPIO interrupt status clear register for GPIO0-31
*/
uint32_t status_w1tc:32;
};
uint32_t val;
} gpio_status_w1tc_reg_t;
/** Type of status1 register
* GPIO interrupt status register for GPIO32-34
*/
typedef union {
struct {
/** status1_interrupt : R/W/WTC; bitpos: [2:0]; default: 0;
* GPIO interrupt status register for GPIO32-34
*/
uint32_t status1_interrupt:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_status1_reg_t;
/** Type of status1_w1ts register
* GPIO interrupt status set register for GPIO32-34
*/
typedef union {
struct {
/** status1_w1ts : WT; bitpos: [2:0]; default: 0;
* GPIO interrupt status set register for GPIO32-34
*/
uint32_t status1_w1ts:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_status1_w1ts_reg_t;
/** Type of status1_w1tc register
* GPIO interrupt status clear register for GPIO32-34
*/
typedef union {
struct {
/** status1_w1tc : WT; bitpos: [2:0]; default: 0;
* GPIO interrupt status clear register for GPIO32-34
*/
uint32_t status1_w1tc:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_status1_w1tc_reg_t;
/** Type of pcpu_int register
* GPIO PRO_CPU interrupt status register for GPIO0-31
*/
typedef union {
struct {
/** procpu_int : RO; bitpos: [31:0]; default: 0;
* GPIO PRO_CPU interrupt status register for GPIO0-31
*/
uint32_t procpu_int:32;
};
uint32_t val;
} gpio_pcpu_int_reg_t;
/** Type of pcpu_nmi_int register
* GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31
*/
typedef union {
struct {
/** procpu_nmi_int : RO; bitpos: [31:0]; default: 0;
* GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31
*/
uint32_t procpu_nmi_int:32;
};
uint32_t val;
} gpio_pcpu_nmi_int_reg_t;
/** Type of cpusdio_int register
* GPIO CPUSDIO interrupt status register for GPIO0-31
*/
typedef union {
struct {
/** sdio_int : RO; bitpos: [31:0]; default: 0;
* GPIO CPUSDIO interrupt status register for GPIO0-31
*/
uint32_t sdio_int:32;
};
uint32_t val;
} gpio_cpusdio_int_reg_t;
/** Type of pcpu_int1 register
* GPIO PRO_CPU interrupt status register for GPIO32-34
*/
typedef union {
struct {
/** procpu_int1 : RO; bitpos: [2:0]; default: 0;
* GPIO PRO_CPU interrupt status register for GPIO32-34
*/
uint32_t procpu_int1:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_pcpu_int1_reg_t;
/** Type of pcpu_nmi_int1 register
* GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34
*/
typedef union {
struct {
/** procpu_nmi_int1 : RO; bitpos: [2:0]; default: 0;
* GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34
*/
uint32_t procpu_nmi_int1:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_pcpu_nmi_int1_reg_t;
/** Type of cpusdio_int1 register
* GPIO CPUSDIO interrupt status register for GPIO32-34
*/
typedef union {
struct {
/** sdio_int1 : RO; bitpos: [2:0]; default: 0;
* GPIO CPUSDIO interrupt status register for GPIO32-34
*/
uint32_t sdio_int1:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_cpusdio_int1_reg_t;
/** Type of pin register
* GPIO pin configuration register
*/
typedef union {
struct {
/** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t sync2_bypass:2;
/** pad_driver : R/W; bitpos: [2]; default: 0;
* set this bit to select pad driver. 1:open-drain. 0:normal.
*/
uint32_t pad_driver:1;
/** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t sync1_bypass:2;
uint32_t reserved_5:2;
/** int_type : R/W; bitpos: [9:7]; default: 0;
* set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
* posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
* at high level
*/
uint32_t int_type:3;
/** wakeup_enable : R/W; bitpos: [10]; default: 0;
* set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
*/
uint32_t wakeup_enable:1;
/** config : R/W; bitpos: [12:11]; default: 0;
* reserved
*/
uint32_t config:2;
/** int_ena : R/W; bitpos: [17:13]; default: 0;
* set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
* interrupt.
*/
uint32_t int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin_reg_t;
/** Type of status_next register
* GPIO interrupt source register for GPIO0-31
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
* GPIO interrupt source register for GPIO0-31
*/
uint32_t status_interrupt_next:32;
};
uint32_t val;
} gpio_status_next_reg_t;
/** Type of status_next1 register
* GPIO interrupt source register for GPIO32-34
*/
typedef union {
struct {
/** status_interrupt_next1 : RO; bitpos: [2:0]; default: 0;
* GPIO interrupt source register for GPIO32-34
*/
uint32_t status_interrupt_next1:3;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_status_next1_reg_t;
/** Type of func_in_sel_cfg register
* GPIO input function configuration register
*/
typedef union {
struct {
/** in_sel : R/W; bitpos: [5:0]; default: 60;
* set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
* high level. s=0x3C: set this port always low level.
*/
uint32_t in_sel:6;
/** in_inv_sel : R/W; bitpos: [6]; default: 0;
* set this bit to invert input signal. 1:invert. 0:not invert.
*/
uint32_t in_inv_sel:1;
/** sig_in_sel : R/W; bitpos: [7]; default: 0;
* set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
*/
uint32_t sig_in_sel:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_func_in_sel_cfg_reg_t;
/** Type of func_out_sel_cfg register
* GPIO output function select register
*/
typedef union {
struct {
/** out_sel : R/W/SC; bitpos: [7:0]; default: 128;
* The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
* output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
* GPIO_OUT_REG[n].
*/
uint32_t out_sel:8;
/** out_inv_sel : R/W/SC; bitpos: [8]; default: 0;
* set this bit to invert output signal.1:invert.0:not invert.
*/
uint32_t out_inv_sel:1;
/** oen_sel : R/W; bitpos: [9]; default: 0;
* set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
* enable signal.0:use peripheral output enable signal.
*/
uint32_t oen_sel:1;
/** oen_inv_sel : R/W; bitpos: [10]; default: 0;
* set this bit to invert output enable signal.1:invert.0:not invert.
*/
uint32_t oen_inv_sel:1;
uint32_t reserved_11:21;
};
uint32_t val;
} gpio_func_out_sel_cfg_reg_t;
/** Type of clock_gate register
* GPIO clock gate register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* set this bit to enable GPIO clock gate
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} gpio_clock_gate_reg_t;
/** Type of date register
* GPIO version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35655968;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_date_reg_t;
typedef struct gpio_dev_t {
volatile gpio_bt_select_reg_t bt_select;
volatile gpio_out_reg_t out;
volatile gpio_out_w1ts_reg_t out_w1ts;
volatile gpio_out_w1tc_reg_t out_w1tc;
volatile gpio_out1_reg_t out1;
volatile gpio_out1_w1ts_reg_t out1_w1ts;
volatile gpio_out1_w1tc_reg_t out1_w1tc;
volatile gpio_sdio_select_reg_t sdio_select;
volatile gpio_enable_reg_t enable;
volatile gpio_enable_w1ts_reg_t enable_w1ts;
volatile gpio_enable_w1tc_reg_t enable_w1tc;
volatile gpio_enable1_reg_t enable1;
volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
volatile gpio_strap_reg_t strap;
volatile gpio_in_reg_t in;
volatile gpio_in1_reg_t in1;
volatile gpio_status_reg_t status;
volatile gpio_status_w1ts_reg_t status_w1ts;
volatile gpio_status_w1tc_reg_t status_w1tc;
volatile gpio_status1_reg_t status1;
volatile gpio_status1_w1ts_reg_t status1_w1ts;
volatile gpio_status1_w1tc_reg_t status1_w1tc;
volatile gpio_pcpu_int_reg_t pcpu_int;
volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int;
volatile gpio_cpusdio_int_reg_t cpusdio_int;
volatile gpio_pcpu_int1_reg_t pcpu_int1;
volatile gpio_pcpu_nmi_int1_reg_t pcpu_nmi_int1;
volatile gpio_cpusdio_int1_reg_t cpusdio_int1;
volatile gpio_pin_reg_t pin[35];
uint32_t reserved_100[19];
volatile gpio_status_next_reg_t status_next;
volatile gpio_status_next1_reg_t status_next1;
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[125];
uint32_t reserved_348[131];
volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[35];
uint32_t reserved_5e0[19];
volatile gpio_clock_gate_reg_t clock_gate;
uint32_t reserved_630[51];
volatile gpio_date_reg_t date;
} gpio_dev_t;
extern gpio_dev_t GPIO;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ATOMIC_ADDR_LOCK_REG register
* hardware lock regsiter
*/
#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
* read to acquire hardware lock, write to release hardware lock
*/
#define ATOMIC_LOCK 0x00000003U
#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATOMIC_LOCK_S)
#define ATOMIC_LOCK_V 0x00000003U
#define ATOMIC_LOCK_S 0
/** ATOMIC_LR_ADDR_REG register
* gloable lr address regsiter
*/
#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
* backup gloable address
*/
#define ATOMIC_GLOABLE_LR_ADDR 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_ADDR_M (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S)
#define ATOMIC_GLOABLE_LR_ADDR_V 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_ADDR_S 0
/** ATOMIC_LR_VALUE_REG register
* gloable lr value regsiter
*/
#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
* backup gloable value
*/
#define ATOMIC_GLOABLE_LR_VALUE 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_VALUE_M (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S)
#define ATOMIC_GLOABLE_LR_VALUE_V 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_VALUE_S 0
/** ATOMIC_LOCK_STATUS_REG register
* lock status regsiter
*/
#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
* read hareware lock status for debug
*/
#define ATOMIC_LOCK_STATUS 0x00000003U
#define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
#define ATOMIC_LOCK_STATUS_V 0x00000003U
#define ATOMIC_LOCK_STATUS_S 0
/** ATOMIC_COUNTER_REG register
* wait counter register
*/
#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10)
/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0;
* delay counter
*/
#define ATOMIC_WAIT_COUNTER 0x0000FFFFU
#define ATOMIC_WAIT_COUNTER_M (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S)
#define ATOMIC_WAIT_COUNTER_V 0x0000FFFFU
#define ATOMIC_WAIT_COUNTER_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of addr_lock register
* hardware lock regsiter
*/
typedef union {
struct {
/** lock : R/W; bitpos: [1:0]; default: 0;
* read to acquire hardware lock, write to release hardware lock
*/
uint32_t lock:2;
uint32_t reserved_2:30;
};
uint32_t val;
} atomic_addr_lock_reg_t;
/** Type of lr_addr register
* gloable lr address regsiter
*/
typedef union {
struct {
/** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0;
* backup gloable address
*/
uint32_t gloable_lr_addr:32;
};
uint32_t val;
} atomic_lr_addr_reg_t;
/** Type of lr_value register
* gloable lr value regsiter
*/
typedef union {
struct {
/** gloable_lr_value : R/W; bitpos: [31:0]; default: 0;
* backup gloable value
*/
uint32_t gloable_lr_value:32;
};
uint32_t val;
} atomic_lr_value_reg_t;
/** Type of lock_status register
* lock status regsiter
*/
typedef union {
struct {
/** lock_status : RO; bitpos: [1:0]; default: 0;
* read hareware lock status for debug
*/
uint32_t lock_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} atomic_lock_status_reg_t;
/** Type of counter register
* wait counter register
*/
typedef union {
struct {
/** wait_counter : R/W; bitpos: [15:0]; default: 0;
* delay counter
*/
uint32_t wait_counter:16;
uint32_t reserved_16:16;
};
uint32_t val;
} atomic_counter_reg_t;
typedef struct atomic_dev_t {
volatile atomic_addr_lock_reg_t addr_lock;
volatile atomic_lr_addr_reg_t lr_addr;
volatile atomic_lr_value_reg_t lr_value;
volatile atomic_lock_status_reg_t lock_status;
volatile atomic_counter_reg_t counter;
} atomic_dev_t;
extern atomic_dev_t ATOMIC_LOCKER;
#ifndef __cplusplus
_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HINF_CFG_DATA0_REG register
* Configure sdio cis content
*/
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
#define HINF_DEVICE_ID_FN1 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S)
#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_S 0
/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
#define HINF_USER_ID_FN1 0x0000FFFFU
#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S)
#define HINF_USER_ID_FN1_V 0x0000FFFFU
#define HINF_USER_ID_FN1_S 16
/** HINF_CFG_DATA1_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
#define HINF_SDIO_ENABLE (BIT(0))
#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S)
#define HINF_SDIO_ENABLE_V 0x00000001U
#define HINF_SDIO_ENABLE_S 0
/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY1 (BIT(1))
#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S)
#define HINF_SDIO_IOREADY1_V 0x00000001U
#define HINF_SDIO_IOREADY1_S 1
/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
#define HINF_HIGHSPEED_ENABLE (BIT(2))
#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S)
#define HINF_HIGHSPEED_ENABLE_V 0x00000001U
#define HINF_HIGHSPEED_ENABLE_S 2
/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
#define HINF_HIGHSPEED_MODE (BIT(3))
#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S)
#define HINF_HIGHSPEED_MODE_V 0x00000001U
#define HINF_HIGHSPEED_MODE_S 3
/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
#define HINF_SDIO_CD_ENABLE (BIT(4))
#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S)
#define HINF_SDIO_CD_ENABLE_V 0x00000001U
#define HINF_SDIO_CD_ENABLE_S 4
/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY2 (BIT(5))
#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S)
#define HINF_SDIO_IOREADY2_V 0x00000001U
#define HINF_SDIO_IOREADY2_S 5
/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
#define HINF_SDIO_INT_MASK (BIT(6))
#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S)
#define HINF_SDIO_INT_MASK_V 0x00000001U
#define HINF_SDIO_INT_MASK_S 6
/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
#define HINF_IOENABLE2 (BIT(7))
#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S)
#define HINF_IOENABLE2_V 0x00000001U
#define HINF_IOENABLE2_S 7
/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
#define HINF_CD_DISABLE (BIT(8))
#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S)
#define HINF_CD_DISABLE_V 0x00000001U
#define HINF_CD_DISABLE_S 8
/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
#define HINF_FUNC1_EPS (BIT(9))
#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S)
#define HINF_FUNC1_EPS_V 0x00000001U
#define HINF_FUNC1_EPS_S 9
/** HINF_EMP : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
#define HINF_EMP (BIT(10))
#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S)
#define HINF_EMP_V 0x00000001U
#define HINF_EMP_S 10
/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
#define HINF_IOENABLE1 (BIT(11))
#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S)
#define HINF_IOENABLE1_V 0x00000001U
#define HINF_IOENABLE1_S 11
/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
#define HINF_SDIO_VER 0x00000FFFU
#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S)
#define HINF_SDIO_VER_V 0x00000FFFU
#define HINF_SDIO_VER_S 12
/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
#define HINF_FUNC2_EPS (BIT(24))
#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S)
#define HINF_FUNC2_EPS_V 0x00000001U
#define HINF_FUNC2_EPS_S 24
/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
#define HINF_SDIO20_CONF 0x0000007FU
#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S)
#define HINF_SDIO20_CONF_V 0x0000007FU
#define HINF_SDIO20_CONF_S 25
/** HINF_CFG_TIMING_REG register
* Timing configuration registers
*/
#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
#define HINF_NCRC 0x00000007U
#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S)
#define HINF_NCRC_V 0x00000007U
#define HINF_NCRC_S 0
/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S)
#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_S 3
/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S)
#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_S 10
/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
#define HINF_SDCLK_STOP_THRES 0x000007FFU
#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S)
#define HINF_SDCLK_STOP_THRES_V 0x000007FFU
#define HINF_SDCLK_STOP_THRES_S 16
/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S)
#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_S 28
/** HINF_CFG_UPDATE_REG register
* update sdio configurations
*/
#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
#define HINF_CONF_UPDATE (BIT(0))
#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S)
#define HINF_CONF_UPDATE_V 0x00000001U
#define HINF_CONF_UPDATE_S 0
/** HINF_CFG_DATA7_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
#define HINF_PIN_STATE 0x000000FFU
#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S)
#define HINF_PIN_STATE_V 0x000000FFU
#define HINF_PIN_STATE_S 0
/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
#define HINF_CHIP_STATE 0x000000FFU
#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S)
#define HINF_CHIP_STATE_V 0x000000FFU
#define HINF_CHIP_STATE_S 8
/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
#define HINF_SDIO_RST (BIT(16))
#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S)
#define HINF_SDIO_RST_V 0x00000001U
#define HINF_SDIO_RST_S 16
/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
#define HINF_SDIO_IOREADY0 (BIT(17))
#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S)
#define HINF_SDIO_IOREADY0_V 0x00000001U
#define HINF_SDIO_IOREADY0_S 17
/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
#define HINF_SDIO_MEM_PD (BIT(18))
#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S)
#define HINF_SDIO_MEM_PD_V 0x00000001U
#define HINF_SDIO_MEM_PD_S 18
/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
#define HINF_ESDIO_DATA1_INT_EN (BIT(19))
#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S)
#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U
#define HINF_ESDIO_DATA1_INT_EN_S 19
/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20))
#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S)
#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_SW_S 20
/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21))
#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S)
#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U
#define HINF_DDR50_BLK_LEN_FIX_EN_S 21
/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
#define HINF_CLK_EN (BIT(22))
#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S)
#define HINF_CLK_EN_V 0x00000001U
#define HINF_CLK_EN_S 22
/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
#define HINF_SDDR50 (BIT(23))
#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S)
#define HINF_SDDR50_V 0x00000001U
#define HINF_SDDR50_S 23
/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
#define HINF_SSDR104 (BIT(24))
#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S)
#define HINF_SSDR104_V 0x00000001U
#define HINF_SSDR104_S 24
/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
#define HINF_SSDR50 (BIT(25))
#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S)
#define HINF_SSDR50_V 0x00000001U
#define HINF_SSDR50_S 25
/** HINF_SDTD : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
#define HINF_SDTD (BIT(26))
#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S)
#define HINF_SDTD_V 0x00000001U
#define HINF_SDTD_S 26
/** HINF_SDTA : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
#define HINF_SDTA (BIT(27))
#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S)
#define HINF_SDTA_V 0x00000001U
#define HINF_SDTA_S 27
/** HINF_SDTC : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
#define HINF_SDTC (BIT(28))
#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S)
#define HINF_SDTC_V 0x00000001U
#define HINF_SDTC_S 28
/** HINF_SAI : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
#define HINF_SAI (BIT(29))
#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S)
#define HINF_SAI_V 0x00000001U
#define HINF_SAI_S 29
/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
#define HINF_SDIO_WAKEUP_CLR (BIT(30))
#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S)
#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U
#define HINF_SDIO_WAKEUP_CLR_S 30
/** HINF_CIS_CONF_W0_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
#define HINF_CIS_CONF_W0 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S)
#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_S 0
/** HINF_CIS_CONF_W1_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
#define HINF_CIS_CONF_W1 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S)
#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_S 0
/** HINF_CIS_CONF_W2_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
#define HINF_CIS_CONF_W2 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S)
#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_S 0
/** HINF_CIS_CONF_W3_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
#define HINF_CIS_CONF_W3 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S)
#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_S 0
/** HINF_CIS_CONF_W4_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
#define HINF_CIS_CONF_W4 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S)
#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_S 0
/** HINF_CIS_CONF_W5_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34)
/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
#define HINF_CIS_CONF_W5 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S)
#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_S 0
/** HINF_CIS_CONF_W6_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38)
/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
#define HINF_CIS_CONF_W6 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S)
#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_S 0
/** HINF_CIS_CONF_W7_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c)
/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
#define HINF_CIS_CONF_W7 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S)
#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_S 0
/** HINF_CFG_DATA16_REG register
* SDIO cis configuration register
*/
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
#define HINF_DEVICE_ID_FN2 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S)
#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_S 0
/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
#define HINF_USER_ID_FN2 0x0000FFFFU
#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S)
#define HINF_USER_ID_FN2_V 0x0000FFFFU
#define HINF_USER_ID_FN2_S 16
/** HINF_CFG_UHS1_INT_MODE_REG register
* configure int to start and end ahead of time in uhs1 mode
*/
#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44)
/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_END_AHEAD_MODE 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S)
#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_S 0
/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_END_AHEAD_MODE 0x00000003U
#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S)
#define HINF_INT_END_AHEAD_MODE_V 0x00000003U
#define HINF_INT_END_AHEAD_MODE_S 2
/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S)
#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_S 4
/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_ST_AHEAD_MODE 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S)
#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_S 6
/** HINF_CONF_STATUS_REG register
* func0 config0 status
*/
#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54)
/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
#define HINF_FUNC0_CONFIG0 0x000000FFU
#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S)
#define HINF_FUNC0_CONFIG0_V 0x000000FFU
#define HINF_FUNC0_CONFIG0_S 0
/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
#define HINF_SDR25_ST (BIT(8))
#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S)
#define HINF_SDR25_ST_V 0x00000001U
#define HINF_SDR25_ST_S 8
/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
#define HINF_SDR50_ST (BIT(9))
#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S)
#define HINF_SDR50_ST_V 0x00000001U
#define HINF_SDR50_ST_S 9
/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
#define HINF_SDR104_ST (BIT(10))
#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S)
#define HINF_SDR104_ST_V 0x00000001U
#define HINF_SDR104_ST_S 10
/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
#define HINF_DDR50_ST (BIT(11))
#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S)
#define HINF_DDR50_ST_V 0x00000001U
#define HINF_DDR50_ST_S 11
/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
#define HINF_TUNE_ST 0x00000007U
#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S)
#define HINF_TUNE_ST_V 0x00000007U
#define HINF_TUNE_ST_S 12
/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15))
#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S)
#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_ST_S 15
/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
#define HINF_SDIO_SWITCH_END (BIT(16))
#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S)
#define HINF_SDIO_SWITCH_END_V 0x00000001U
#define HINF_SDIO_SWITCH_END_S 16
/** HINF_SDIO_SLAVE_ECO_LOW_REG register
* sdio_slave redundant control registers
*/
#define HINF_SDIO_SLAVE_ECO_LOW_REG (DR_REG_HINF_BASE + 0xa4)
/** HINF_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_RDN_ECO_LOW 0xFFFFFFFFU
#define HINF_RDN_ECO_LOW_M (HINF_RDN_ECO_LOW_V << HINF_RDN_ECO_LOW_S)
#define HINF_RDN_ECO_LOW_V 0xFFFFFFFFU
#define HINF_RDN_ECO_LOW_S 0
/** HINF_SDIO_SLAVE_ECO_HIGH_REG register
* sdio_slave redundant control registers
*/
#define HINF_SDIO_SLAVE_ECO_HIGH_REG (DR_REG_HINF_BASE + 0xa8)
/** HINF_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* redundant registers for sdio_slave
*/
#define HINF_RDN_ECO_HIGH 0xFFFFFFFFU
#define HINF_RDN_ECO_HIGH_M (HINF_RDN_ECO_HIGH_V << HINF_RDN_ECO_HIGH_S)
#define HINF_RDN_ECO_HIGH_V 0xFFFFFFFFU
#define HINF_RDN_ECO_HIGH_S 0
/** HINF_SDIO_SLAVE_ECO_CONF_REG register
* sdio_slave redundant control registers
*/
#define HINF_SDIO_SLAVE_ECO_CONF_REG (DR_REG_HINF_BASE + 0xac)
/** HINF_SDIO_SLAVE_RDN_RESULT : RO; bitpos: [0]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_RDN_RESULT (BIT(0))
#define HINF_SDIO_SLAVE_RDN_RESULT_M (HINF_SDIO_SLAVE_RDN_RESULT_V << HINF_SDIO_SLAVE_RDN_RESULT_S)
#define HINF_SDIO_SLAVE_RDN_RESULT_V 0x00000001U
#define HINF_SDIO_SLAVE_RDN_RESULT_S 0
/** HINF_SDIO_SLAVE_RDN_ENA : R/W; bitpos: [1]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_RDN_ENA (BIT(1))
#define HINF_SDIO_SLAVE_RDN_ENA_M (HINF_SDIO_SLAVE_RDN_ENA_V << HINF_SDIO_SLAVE_RDN_ENA_S)
#define HINF_SDIO_SLAVE_RDN_ENA_V 0x00000001U
#define HINF_SDIO_SLAVE_RDN_ENA_S 1
/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT : RO; bitpos: [2]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT (BIT(2))
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_M (HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S)
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V 0x00000001U
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S 2
/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA : R/W; bitpos: [3]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA (BIT(3))
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_M (HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S)
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V 0x00000001U
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S 3
/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT : RO; bitpos: [4]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT (BIT(4))
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_M (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S)
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V 0x00000001U
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S 4
/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA : R/W; bitpos: [5]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA (BIT(5))
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_M (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S)
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V 0x00000001U
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S 5
/** HINF_SDIO_SLAVE_LDO_CONF_REG register
* sdio slave ldo control register
*/
#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0)
/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
#define HINF_LDO_READY_CTL_IN_EN (BIT(0))
#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S)
#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U
#define HINF_LDO_READY_CTL_IN_EN_S 0
/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
#define HINF_LDO_READY_THRES 0x0000001FU
#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S)
#define HINF_LDO_READY_THRES_V 0x0000001FU
#define HINF_LDO_READY_THRES_S 1
/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
#define HINF_LDO_READY_IGNORE_EN (BIT(6))
#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S)
#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U
#define HINF_LDO_READY_IGNORE_EN_S 6
/** HINF_SDIO_DATE_REG register
* ******* Description ***********
*/
#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc)
/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208;
* sdio version date.
*/
#define HINF_SDIO_DATE 0xFFFFFFFFU
#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S)
#define HINF_SDIO_DATE_V 0xFFFFFFFFU
#define HINF_SDIO_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/hinf_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration registers */
/** Type of cfg_data0 register
* Configure sdio cis content
*/
typedef union {
struct {
/** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
uint32_t device_id_fn1:16;
/** user_id_fn1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
uint32_t user_id_fn1:16;
};
uint32_t val;
} hinf_cfg_data0_reg_t;
/** Type of cfg_data1 register
* SDIO configuration register
*/
typedef union {
struct {
/** sdio_enable : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
uint32_t sdio_enable:1;
/** sdio_ioready1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready1:1;
/** highspeed_enable : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
uint32_t highspeed_enable:1;
/** highspeed_mode : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
uint32_t highspeed_mode:1;
/** sdio_cd_enable : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
uint32_t sdio_cd_enable:1;
/** sdio_ioready2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready2:1;
/** sdio_int_mask : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
uint32_t sdio_int_mask:1;
/** ioenable2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
uint32_t ioenable2:1;
/** cd_disable : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
uint32_t cd_disable:1;
/** func1_eps : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
uint32_t func1_eps:1;
/** emp : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
uint32_t emp:1;
/** ioenable1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
uint32_t ioenable1:1;
/** sdio_ver : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
uint32_t sdio_ver:12;
/** func2_eps : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
uint32_t func2_eps:1;
/** sdio20_conf : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
uint32_t sdio20_conf:7;
};
uint32_t val;
} hinf_cfg_data1_reg_t;
/** Type of cfg_timing register
* Timing configuration registers
*/
typedef union {
struct {
/** ncrc : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
uint32_t ncrc:3;
/** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
uint32_t pst_end_cmd_low_value:7;
/** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
uint32_t pst_end_data_low_value:6;
/** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
uint32_t sdclk_stop_thres:11;
uint32_t reserved_27:1;
/** sample_clk_divider : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
uint32_t sample_clk_divider:4;
};
uint32_t val;
} hinf_cfg_timing_reg_t;
/** Type of cfg_update register
* update sdio configurations
*/
typedef union {
struct {
/** conf_update : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
uint32_t conf_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hinf_cfg_update_reg_t;
/** Type of cfg_data7 register
* SDIO configuration register
*/
typedef union {
struct {
/** pin_state : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
uint32_t pin_state:8;
/** chip_state : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
uint32_t chip_state:8;
/** sdio_rst : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
uint32_t sdio_rst:1;
/** sdio_ioready0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
uint32_t sdio_ioready0:1;
/** sdio_mem_pd : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
uint32_t sdio_mem_pd:1;
/** esdio_data1_int_en : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
uint32_t esdio_data1_int_en:1;
/** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
uint32_t sdio_switch_volt_sw:1;
/** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
uint32_t ddr50_blk_len_fix_en:1;
/** clk_en : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
uint32_t clk_en:1;
/** sddr50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
uint32_t sddr50:1;
/** ssdr104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
uint32_t ssdr104:1;
/** ssdr50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
uint32_t ssdr50:1;
/** sdtd : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
uint32_t sdtd:1;
/** sdta : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
uint32_t sdta:1;
/** sdtc : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
uint32_t sdtc:1;
/** sai : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
uint32_t sai:1;
/** sdio_wakeup_clr : WT; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
uint32_t sdio_wakeup_clr:1;
uint32_t reserved_31:1;
};
uint32_t val;
} hinf_cfg_data7_reg_t;
/** Type of cis_conf_w0 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
uint32_t cis_conf_w0:32;
};
uint32_t val;
} hinf_cis_conf_w0_reg_t;
/** Type of cis_conf_w1 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
uint32_t cis_conf_w1:32;
};
uint32_t val;
} hinf_cis_conf_w1_reg_t;
/** Type of cis_conf_w2 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
uint32_t cis_conf_w2:32;
};
uint32_t val;
} hinf_cis_conf_w2_reg_t;
/** Type of cis_conf_w3 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
uint32_t cis_conf_w3:32;
};
uint32_t val;
} hinf_cis_conf_w3_reg_t;
/** Type of cis_conf_w4 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
uint32_t cis_conf_w4:32;
};
uint32_t val;
} hinf_cis_conf_w4_reg_t;
/** Type of cis_conf_w5 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
uint32_t cis_conf_w5:32;
};
uint32_t val;
} hinf_cis_conf_w5_reg_t;
/** Type of cis_conf_w6 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
uint32_t cis_conf_w6:32;
};
uint32_t val;
} hinf_cis_conf_w6_reg_t;
/** Type of cis_conf_w7 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
uint32_t cis_conf_w7:32;
};
uint32_t val;
} hinf_cis_conf_w7_reg_t;
/** Type of cfg_data16 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
uint32_t device_id_fn2:16;
/** user_id_fn2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
uint32_t user_id_fn2:16;
};
uint32_t val;
} hinf_cfg_data16_reg_t;
/** Type of cfg_uhs1_int_mode register
* configure int to start and end ahead of time in uhs1 mode
*/
typedef union {
struct {
/** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_end_ahead_mode:2;
/** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_end_ahead_mode:2;
/** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_st_ahead_mode:2;
/** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_st_ahead_mode:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hinf_cfg_uhs1_int_mode_reg_t;
/** Type of sdio_slave_eco_low register
* sdio_slave redundant control registers
*/
typedef union {
struct {
/** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t rdn_eco_low:32;
};
uint32_t val;
} hinf_sdio_slave_eco_low_reg_t;
/** Type of sdio_slave_eco_high register
* sdio_slave redundant control registers
*/
typedef union {
struct {
/** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* redundant registers for sdio_slave
*/
uint32_t rdn_eco_high:32;
};
uint32_t val;
} hinf_sdio_slave_eco_high_reg_t;
/** Type of sdio_slave_eco_conf register
* sdio_slave redundant control registers
*/
typedef union {
struct {
/** sdio_slave_rdn_result : RO; bitpos: [0]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_rdn_result:1;
/** sdio_slave_rdn_ena : R/W; bitpos: [1]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_rdn_ena:1;
/** sdio_slave_sdio_clk_rdn_result : RO; bitpos: [2]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_sdio_clk_rdn_result:1;
/** sdio_slave_sdio_clk_rdn_ena : R/W; bitpos: [3]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_sdio_clk_rdn_ena:1;
/** sdio_slave_sdclk_pad_rdn_result : RO; bitpos: [4]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_sdclk_pad_rdn_result:1;
/** sdio_slave_sdclk_pad_rdn_ena : R/W; bitpos: [5]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_sdclk_pad_rdn_ena:1;
uint32_t reserved_6:26;
};
uint32_t val;
} hinf_sdio_slave_eco_conf_reg_t;
/** Type of sdio_slave_ldo_conf register
* sdio slave ldo control register
*/
typedef union {
struct {
/** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
uint32_t ldo_ready_ctl_in_en:1;
/** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
uint32_t ldo_ready_thres:5;
/** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
uint32_t ldo_ready_ignore_en:1;
uint32_t reserved_7:25;
};
uint32_t val;
} hinf_sdio_slave_ldo_conf_reg_t;
/** Group: Status registers */
/** Type of conf_status register
* func0 config0 status
*/
typedef union {
struct {
/** func0_config0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
uint32_t func0_config0:8;
/** sdr25_st : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
uint32_t sdr25_st:1;
/** sdr50_st : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
uint32_t sdr50_st:1;
/** sdr104_st : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
uint32_t sdr104_st:1;
/** ddr50_st : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
uint32_t ddr50_st:1;
/** tune_st : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
uint32_t tune_st:3;
/** sdio_switch_volt_st : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
uint32_t sdio_switch_volt_st:1;
/** sdio_switch_end : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
uint32_t sdio_switch_end:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hinf_conf_status_reg_t;
/** Group: Version register */
/** Type of sdio_date register
* ******* Description ***********
*/
typedef union {
struct {
/** sdio_date : R/W; bitpos: [31:0]; default: 35664208;
* sdio version date.
*/
uint32_t sdio_date:32;
};
uint32_t val;
} hinf_sdio_date_reg_t;
typedef struct hinf_dev_t {
volatile hinf_cfg_data0_reg_t cfg_data0;
volatile hinf_cfg_data1_reg_t cfg_data1;
volatile hinf_cfg_timing_reg_t cfg_timing;
volatile hinf_cfg_update_reg_t cfg_update;
uint32_t reserved_010[3];
volatile hinf_cfg_data7_reg_t cfg_data7;
volatile hinf_cis_conf_w0_reg_t cis_conf_w0;
volatile hinf_cis_conf_w1_reg_t cis_conf_w1;
volatile hinf_cis_conf_w2_reg_t cis_conf_w2;
volatile hinf_cis_conf_w3_reg_t cis_conf_w3;
volatile hinf_cis_conf_w4_reg_t cis_conf_w4;
volatile hinf_cis_conf_w5_reg_t cis_conf_w5;
volatile hinf_cis_conf_w6_reg_t cis_conf_w6;
volatile hinf_cis_conf_w7_reg_t cis_conf_w7;
volatile hinf_cfg_data16_reg_t cfg_data16;
volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode;
uint32_t reserved_048[3];
volatile hinf_conf_status_reg_t conf_status;
uint32_t reserved_058[19];
volatile hinf_sdio_slave_eco_low_reg_t sdio_slave_eco_low;
volatile hinf_sdio_slave_eco_high_reg_t sdio_slave_eco_high;
volatile hinf_sdio_slave_eco_conf_reg_t sdio_slave_eco_conf;
volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf;
uint32_t reserved_0b4[18];
volatile hinf_sdio_date_reg_t sdio_date;
} hinf_dev_t;
extern hinf_dev_t HINF;
#ifndef __cplusplus
_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
* Process control register 0.
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S)
#define HMAC_SET_START_V 0x00000001U
#define HMAC_SET_START_S 0
/** HMAC_SET_PARA_PURPOSE_REG register
* Configure purpose.
*/
#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
#define HMAC_PURPOSE_SET 0x0000000FU
#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
#define HMAC_PURPOSE_SET_V 0x0000000FU
#define HMAC_PURPOSE_SET_S 0
/** HMAC_SET_PARA_KEY_REG register
* Configure key.
*/
#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
#define HMAC_KEY_SET 0x00000007U
#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
#define HMAC_KEY_SET_V 0x00000007U
#define HMAC_KEY_SET_S 0
/** HMAC_SET_PARA_FINISH_REG register
* Finish initial configuration.
*/
#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
#define HMAC_SET_PARA_END (BIT(0))
#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
#define HMAC_SET_PARA_END_V 0x00000001U
#define HMAC_SET_PARA_END_S 0
/** HMAC_SET_MESSAGE_ONE_REG register
* Process control register 1.
*/
#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
#define HMAC_SET_TEXT_ONE (BIT(0))
#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
#define HMAC_SET_TEXT_ONE_V 0x00000001U
#define HMAC_SET_TEXT_ONE_S 0
/** HMAC_SET_MESSAGE_ING_REG register
* Process control register 2.
*/
#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
#define HMAC_SET_TEXT_ING (BIT(0))
#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
#define HMAC_SET_TEXT_ING_V 0x00000001U
#define HMAC_SET_TEXT_ING_S 0
/** HMAC_SET_MESSAGE_END_REG register
* Process control register 3.
*/
#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
#define HMAC_SET_TEXT_END (BIT(0))
#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
#define HMAC_SET_TEXT_END_V 0x00000001U
#define HMAC_SET_TEXT_END_S 0
/** HMAC_SET_RESULT_FINISH_REG register
* Process control register 4.
*/
#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
#define HMAC_SET_RESULT_END (BIT(0))
#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
#define HMAC_SET_RESULT_END_V 0x00000001U
#define HMAC_SET_RESULT_END_S 0
/** HMAC_SET_INVALIDATE_JTAG_REG register
* Invalidate register 0.
*/
#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
#define HMAC_SET_INVALIDATE_JTAG (BIT(0))
#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U
#define HMAC_SET_INVALIDATE_JTAG_S 0
/** HMAC_SET_INVALIDATE_DS_REG register
* Invalidate register 1.
*/
#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
#define HMAC_SET_INVALIDATE_DS (BIT(0))
#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
#define HMAC_SET_INVALIDATE_DS_V 0x00000001U
#define HMAC_SET_INVALIDATE_DS_S 0
/** HMAC_QUERY_ERROR_REG register
* Error register.
*/
#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
#define HMAC_QUREY_CHECK (BIT(0))
#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
#define HMAC_QUREY_CHECK_V 0x00000001U
#define HMAC_QUREY_CHECK_S 0
/** HMAC_QUERY_BUSY_REG register
* Busy register.
*/
#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
#define HMAC_BUSY_STATE (BIT(0))
#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
#define HMAC_BUSY_STATE_V 0x00000001U
#define HMAC_BUSY_STATE_S 0
/** HMAC_WR_MESSAGE_MEM register
* Message block memory.
*/
#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
/** HMAC_RD_RESULT_MEM register
* Result from upstream.
*/
#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
/** HMAC_SET_MESSAGE_PAD_REG register
* Process control register 5.
*/
#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
#define HMAC_SET_TEXT_PAD (BIT(0))
#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
#define HMAC_SET_TEXT_PAD_V 0x00000001U
#define HMAC_SET_TEXT_PAD_S 0
/** HMAC_ONE_BLOCK_REG register
* Process control register 6.
*/
#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
#define HMAC_SET_ONE_BLOCK (BIT(0))
#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
#define HMAC_SET_ONE_BLOCK_V 0x00000001U
#define HMAC_SET_ONE_BLOCK_S 0
/** HMAC_SOFT_JTAG_CTRL_REG register
* Jtag register 0.
*/
#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
#define HMAC_SOFT_JTAG_CTRL (BIT(0))
#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U
#define HMAC_SOFT_JTAG_CTRL_S 0
/** HMAC_WR_JTAG_REG register
* Jtag register 1.
*/
#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
#define HMAC_WR_JTAG 0xFFFFFFFFU
#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
#define HMAC_WR_JTAG_V 0xFFFFFFFFU
#define HMAC_WR_JTAG_S 0
/** HMAC_DATE_REG register
* Date register.
*/
#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
#define HMAC_DATE 0x3FFFFFFFU
#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S)
#define HMAC_DATE_V 0x3FFFFFFFU
#define HMAC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of set_start register
* Process control register 0.
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_start_reg_t;
/** Type of set_para_purpose register
* Configure purpose.
*/
typedef union {
struct {
/** purpose_set : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
uint32_t purpose_set:4;
uint32_t reserved_4:28;
};
uint32_t val;
} hmac_set_para_purpose_reg_t;
/** Type of set_para_key register
* Configure key.
*/
typedef union {
struct {
/** key_set : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
uint32_t key_set:3;
uint32_t reserved_3:29;
};
uint32_t val;
} hmac_set_para_key_reg_t;
/** Type of set_para_finish register
* Finish initial configuration.
*/
typedef union {
struct {
/** set_para_end : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
uint32_t set_para_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_para_finish_reg_t;
/** Type of set_message_one register
* Process control register 1.
*/
typedef union {
struct {
/** set_text_one : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
uint32_t set_text_one:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_one_reg_t;
/** Type of set_message_ing register
* Process control register 2.
*/
typedef union {
struct {
/** set_text_ing : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
uint32_t set_text_ing:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_ing_reg_t;
/** Type of set_message_end register
* Process control register 3.
*/
typedef union {
struct {
/** set_text_end : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
uint32_t set_text_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_end_reg_t;
/** Type of set_result_finish register
* Process control register 4.
*/
typedef union {
struct {
/** set_result_end : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
uint32_t set_result_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_result_finish_reg_t;
/** Type of set_invalidate_jtag register
* Invalidate register 0.
*/
typedef union {
struct {
/** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
uint32_t set_invalidate_jtag:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_jtag_reg_t;
/** Type of set_invalidate_ds register
* Invalidate register 1.
*/
typedef union {
struct {
/** set_invalidate_ds : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
uint32_t set_invalidate_ds:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_ds_reg_t;
/** Type of set_message_pad register
* Process control register 5.
*/
typedef union {
struct {
/** set_text_pad : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
uint32_t set_text_pad:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_pad_reg_t;
/** Type of one_block register
* Process control register 6.
*/
typedef union {
struct {
/** set_one_block : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
uint32_t set_one_block:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_one_block_reg_t;
/** Type of soft_jtag_ctrl register
* Jtag register 0.
*/
typedef union {
struct {
/** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
uint32_t soft_jtag_ctrl:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_soft_jtag_ctrl_reg_t;
/** Type of wr_jtag register
* Jtag register 1.
*/
typedef union {
struct {
/** wr_jtag : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
uint32_t wr_jtag:32;
};
uint32_t val;
} hmac_wr_jtag_reg_t;
/** Group: Status Register */
/** Type of query_error register
* Error register.
*/
typedef union {
struct {
/** qurey_check : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
uint32_t qurey_check:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_error_reg_t;
/** Type of query_busy register
* Busy register.
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_busy_reg_t;
/** Group: Memory Type */
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} hmac_date_reg_t;
typedef struct hmac_dev_t {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;
volatile hmac_set_para_key_reg_t set_para_key;
volatile hmac_set_para_finish_reg_t set_para_finish;
volatile hmac_set_message_one_reg_t set_message_one;
volatile hmac_set_message_ing_reg_t set_message_ing;
volatile hmac_set_message_end_reg_t set_message_end;
volatile hmac_set_result_finish_reg_t set_result_finish;
volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
volatile hmac_query_error_reg_t query_error;
volatile hmac_query_busy_reg_t query_busy;
uint32_t reserved_070[4];
volatile uint32_t wr_message[16];
volatile uint32_t rd_result[8];
uint32_t reserved_0e0[4];
volatile hmac_set_message_pad_reg_t set_message_pad;
volatile hmac_one_block_reg_t one_block;
volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
volatile hmac_wr_jtag_reg_t wr_jtag;
uint32_t reserved_100[63];
volatile hmac_date_reg_t date;
} hmac_dev_t;
extern hmac_dev_t HMAC;
#ifndef __cplusplus
_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
* EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
*/
#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
*/
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
* Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
*/
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
/** HP_SYSTEM_SRAM_USAGE_CONF_REG register
* HP memory usage configuration register
*/
#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYSTEM_CACHE_USAGE (BIT(0))
#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S)
#define HP_SYSTEM_CACHE_USAGE_V 0x00000001U
#define HP_SYSTEM_CACHE_USAGE_S 0
/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
#define HP_SYSTEM_SRAM_USAGE 0x0000000FU
#define HP_SYSTEM_SRAM_USAGE_M (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S)
#define HP_SYSTEM_SRAM_USAGE_V 0x0000000FU
#define HP_SYSTEM_SRAM_USAGE_S 8
/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0;
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
*/
#define HP_SYSTEM_MAC_DUMP_ALLOC (BIT(16))
#define HP_SYSTEM_MAC_DUMP_ALLOC_M (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S)
#define HP_SYSTEM_MAC_DUMP_ALLOC_V 0x00000001U
#define HP_SYSTEM_MAC_DUMP_ALLOC_S 16
/** HP_SYSTEM_SEC_DPA_CONF_REG register
* HP anti-DPA security configuration register
*/
#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
*/
#define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U
#define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
#define HP_SYSTEM_SEC_DPA_LEVEL_V 0x00000003U
#define HP_SYSTEM_SEC_DPA_LEVEL_S 0
/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
* This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
* (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL.
*/
#define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2))
#define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
#define HP_SYSTEM_SEC_DPA_CFG_SEL_V 0x00000001U
#define HP_SYSTEM_SEC_DPA_CFG_SEL_S 2
/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register
* CPU_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing cpu peripheral
* registers
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register
* CPU_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register
* CPU_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14)
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register
* HP_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18)
/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register
* HP_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c)
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register
* HP_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20)
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register
* MODEM_PERI_TIMEOUT configuration register
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register
* MODEM_PERI_TIMEOUT_ADDR register
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S 0
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register
* MODEM_PERI_TIMEOUT_UID register
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c)
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S)
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S 0
/** HP_SYSTEM_SDIO_CTRL_REG register
* SDIO Control configuration register
*/
#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x30)
/** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
#define HP_SYSTEM_DIS_SDIO_PROB (BIT(0))
#define HP_SYSTEM_DIS_SDIO_PROB_M (HP_SYSTEM_DIS_SDIO_PROB_V << HP_SYSTEM_DIS_SDIO_PROB_S)
#define HP_SYSTEM_DIS_SDIO_PROB_V 0x00000001U
#define HP_SYSTEM_DIS_SDIO_PROB_S 0
/** HP_SYSTEM_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN (BIT(1))
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_M (HP_SYSTEM_SDIO_WIN_ACCESS_EN_V << HP_SYSTEM_SDIO_WIN_ACCESS_EN_S)
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_V 0x00000001U
#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_S 1
/** HP_SYSTEM_RETENTION_CONF_REG register
* Retention configuration register
*/
#define HP_SYSTEM_RETENTION_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x34)
/** HP_SYSTEM_RETENTION_DISABLE : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to disable retention function. Not disable by default.
*/
#define HP_SYSTEM_RETENTION_DISABLE (BIT(0))
#define HP_SYSTEM_RETENTION_DISABLE_M (HP_SYSTEM_RETENTION_DISABLE_V << HP_SYSTEM_RETENTION_DISABLE_S)
#define HP_SYSTEM_RETENTION_DISABLE_V 0x00000001U
#define HP_SYSTEM_RETENTION_DISABLE_S 0
/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
* Rom-Table lock register
*/
#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x38)
/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
* XXXX
*/
#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0))
#define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
#define HP_SYSTEM_ROM_TABLE_LOCK_V 0x00000001U
#define HP_SYSTEM_ROM_TABLE_LOCK_S 0
/** HP_SYSTEM_ROM_TABLE_REG register
* Rom-Table register
*/
#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x3c)
/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
* XXXX
*/
#define HP_SYSTEM_ROM_TABLE 0xFFFFFFFFU
#define HP_SYSTEM_ROM_TABLE_M (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S)
#define HP_SYSTEM_ROM_TABLE_V 0xFFFFFFFFU
#define HP_SYSTEM_ROM_TABLE_S 0
/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
* Core Debug runstall configure register
*/
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x40)
/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
* Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
*/
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0))
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V 0x00000001U
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S 0
/** HP_SYSTEM_MEM_TEST_CONF_REG register
* MEM_TEST configuration register
*/
#define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x44)
/** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
*/
#define HP_SYSTEM_HP_MEM_WPULSE 0x00000007U
#define HP_SYSTEM_HP_MEM_WPULSE_M (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S)
#define HP_SYSTEM_HP_MEM_WPULSE_V 0x00000007U
#define HP_SYSTEM_HP_MEM_WPULSE_S 0
/** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
*/
#define HP_SYSTEM_HP_MEM_WA 0x00000007U
#define HP_SYSTEM_HP_MEM_WA_M (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S)
#define HP_SYSTEM_HP_MEM_WA_V 0x00000007U
#define HP_SYSTEM_HP_MEM_WA_S 3
/** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
*/
#define HP_SYSTEM_HP_MEM_RA 0x00000003U
#define HP_SYSTEM_HP_MEM_RA_M (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S)
#define HP_SYSTEM_HP_MEM_RA_V 0x00000003U
#define HP_SYSTEM_HP_MEM_RA_S 6
/** HP_SYSTEM_RND_ECO_REG register
* redcy eco register.
*/
#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0)
/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_ENA (BIT(0))
#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S)
#define HP_SYSTEM_REDCY_ENA_V 0x00000001U
#define HP_SYSTEM_REDCY_ENA_S 0
/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_RESULT (BIT(1))
#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S)
#define HP_SYSTEM_REDCY_RESULT_V 0x00000001U
#define HP_SYSTEM_REDCY_RESULT_S 1
/** HP_SYSTEM_RND_ECO_LOW_REG register
* redcy eco low register.
*/
#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4)
/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S)
#define HP_SYSTEM_REDCY_LOW_V 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_LOW_S 0
/** HP_SYSTEM_RND_ECO_HIGH_REG register
* redcy eco high register.
*/
#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8)
/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S)
#define HP_SYSTEM_REDCY_HIGH_V 0xFFFFFFFFU
#define HP_SYSTEM_REDCY_HIGH_S 0
/** HP_SYSTEM_CLOCK_GATE_REG register
* HP-SYSTEM clock gating configure register
*/
#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8)
/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
*/
#define HP_SYSTEM_CLK_EN (BIT(0))
#define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S)
#define HP_SYSTEM_CLK_EN_V 0x00000001U
#define HP_SYSTEM_CLK_EN_S 0
/** HP_SYSTEM_DATE_REG register
* Date register.
*/
#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 35676432;
* HP-SYSTEM date information/ HP-SYSTEM version information.
*/
#define HP_SYSTEM_DATE 0x0FFFFFFFU
#define HP_SYSTEM_DATE_M (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S)
#define HP_SYSTEM_DATE_V 0x0FFFFFFFU
#define HP_SYSTEM_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/hp_system_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of external_device_encrypt_decrypt_control register
* EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
*/
typedef union {
struct {
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
*/
uint32_t enable_spi_manual_encrypt:1;
/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t enable_download_db_encrypt:1;
/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
*/
uint32_t enable_download_g0cb_decrypt:1;
/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
*/
uint32_t enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_system_external_device_encrypt_decrypt_control_reg_t;
/** Type of sram_usage_conf register
* HP memory usage configuration register
*/
typedef union {
struct {
/** cache_usage : HRO; bitpos: [0]; default: 0;
* reserved
*/
uint32_t cache_usage:1;
uint32_t reserved_1:7;
/** sram_usage : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
uint32_t sram_usage:4;
uint32_t reserved_12:4;
/** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
*/
uint32_t mac_dump_alloc:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hp_system_sram_usage_conf_reg_t;
/** Type of sec_dpa_conf register
* HP anti-DPA security configuration register
*/
typedef union {
struct {
/** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
*/
uint32_t sec_dpa_level:2;
/** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
* This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
* (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL.
*/
uint32_t sec_dpa_cfg_sel:1;
uint32_t reserved_3:29;
};
uint32_t val;
} hp_system_sec_dpa_conf_reg_t;
/** Type of sdio_ctrl register
* SDIO Control configuration register
*/
typedef union {
struct {
/** dis_sdio_prob : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
uint32_t dis_sdio_prob:1;
/** sdio_win_access_en : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
uint32_t sdio_win_access_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_sdio_ctrl_reg_t;
/** Type of retention_conf register
* Retention configuration register
*/
typedef union {
struct {
/** retention_disable : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to disable retention function. Not disable by default.
*/
uint32_t retention_disable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_retention_conf_reg_t;
/** Type of rom_table_lock register
* Rom-Table lock register
*/
typedef union {
struct {
/** rom_table_lock : R/W; bitpos: [0]; default: 0;
* XXXX
*/
uint32_t rom_table_lock:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_rom_table_lock_reg_t;
/** Type of rom_table register
* Rom-Table register
*/
typedef union {
struct {
/** rom_table : R/W; bitpos: [31:0]; default: 0;
* XXXX
*/
uint32_t rom_table:32;
};
uint32_t val;
} hp_system_rom_table_reg_t;
/** Type of core_debug_runstall_conf register
* Core Debug runstall configure register
*/
typedef union {
struct {
/** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
* Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
*/
uint32_t core_debug_runstall_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_core_debug_runstall_conf_reg_t;
/** Type of mem_test_conf register
* MEM_TEST configuration register
*/
typedef union {
struct {
/** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
*/
uint32_t hp_mem_wpulse:3;
/** hp_mem_wa : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
*/
uint32_t hp_mem_wa:3;
/** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
*/
uint32_t hp_mem_ra:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_system_mem_test_conf_reg_t;
/** Type of clock_gate register
* HP-SYSTEM clock gating configure register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_system_clock_gate_reg_t;
/** Group: Timeout Register */
/** Type of cpu_peri_timeout_conf register
* CPU_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t cpu_peri_timeout_thres:16;
/** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t cpu_peri_timeout_int_clear:1;
/** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing cpu peripheral
* registers
*/
uint32_t cpu_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_cpu_peri_timeout_conf_reg_t;
/** Type of cpu_peri_timeout_addr register
* CPU_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t cpu_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_cpu_peri_timeout_addr_reg_t;
/** Type of cpu_peri_timeout_uid register
* CPU_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t cpu_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_cpu_peri_timeout_uid_reg_t;
/** Type of hp_peri_timeout_conf register
* HP_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t hp_peri_timeout_thres:16;
/** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t hp_peri_timeout_int_clear:1;
/** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
*/
uint32_t hp_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_hp_peri_timeout_conf_reg_t;
/** Type of hp_peri_timeout_addr register
* HP_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t hp_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_hp_peri_timeout_addr_reg_t;
/** Type of hp_peri_timeout_uid register
* HP_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t hp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_hp_peri_timeout_uid_reg_t;
/** Type of modem_peri_timeout_conf register
* MODEM_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t modem_peri_timeout_thres:16;
/** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t modem_peri_timeout_int_clear:1;
/** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
uint32_t modem_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_system_modem_peri_timeout_conf_reg_t;
/** Type of modem_peri_timeout_addr register
* MODEM_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t modem_peri_timeout_addr:32;
};
uint32_t val;
} hp_system_modem_peri_timeout_addr_reg_t;
/** Type of modem_peri_timeout_uid register
* MODEM_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t modem_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_system_modem_peri_timeout_uid_reg_t;
/** Group: Redcy ECO Registers */
/** Type of rnd_eco register
* redcy eco register.
*/
typedef union {
struct {
/** redcy_ena : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_ena:1;
/** redcy_result : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_system_rnd_eco_reg_t;
/** Type of rnd_eco_low register
* redcy eco low register.
*/
typedef union {
struct {
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_low:32;
};
uint32_t val;
} hp_system_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* redcy eco high register.
*/
typedef union {
struct {
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
uint32_t redcy_high:32;
};
uint32_t val;
} hp_system_rnd_eco_high_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35676432;
* HP-SYSTEM date information/ HP-SYSTEM version information.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_system_date_reg_t;
typedef struct hp_system_dev_t {
volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
volatile hp_system_sram_usage_conf_reg_t sram_usage_conf;
volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf;
volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
volatile hp_system_sdio_ctrl_reg_t sdio_ctrl;
volatile hp_system_retention_conf_reg_t retention_conf;
volatile hp_system_rom_table_lock_reg_t rom_table_lock;
volatile hp_system_rom_table_reg_t rom_table;
volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
volatile hp_system_mem_test_conf_reg_t mem_test_conf;
uint32_t reserved_048[230];
volatile hp_system_rnd_eco_reg_t rnd_eco;
volatile hp_system_rnd_eco_low_reg_t rnd_eco_low;
volatile hp_system_rnd_eco_high_reg_t rnd_eco_high;
uint32_t reserved_3ec[3];
volatile hp_system_clock_gate_reg_t clock_gate;
volatile hp_system_date_reg_t date;
} hp_system_dev_t;
extern hp_system_dev_t HP_SYSTEM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
/** INTMTX_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_M (INTMTX_CORE0_WIFI_MAC_INTR_MAP_V << INTMTX_CORE0_WIFI_MAC_INTR_MAP_S)
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_S 0
/** INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
/** INTMTX_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP 0x0000001FU
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_M (INTMTX_CORE0_WIFI_MAC_NMI_MAP_V << INTMTX_CORE0_WIFI_MAC_NMI_MAP_S)
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_V 0x0000001FU
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_S 0
/** INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
/** INTMTX_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_M (INTMTX_CORE0_WIFI_PWR_INTR_MAP_V << INTMTX_CORE0_WIFI_PWR_INTR_MAP_S)
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_S 0
/** INTMTX_CORE0_WIFI_BB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
/** INTMTX_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_WIFI_BB_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_WIFI_BB_INTR_MAP_M (INTMTX_CORE0_WIFI_BB_INTR_MAP_V << INTMTX_CORE0_WIFI_BB_INTR_MAP_S)
#define INTMTX_CORE0_WIFI_BB_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_WIFI_BB_INTR_MAP_S 0
/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BT_MAC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BT_MAC_INTR_MAP_M (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S)
#define INTMTX_CORE0_BT_MAC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BT_MAC_INTR_MAP_S 0
/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BT_BB_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BT_BB_INTR_MAP_M (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S)
#define INTMTX_CORE0_BT_BB_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BT_BB_INTR_MAP_S 0
/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BT_BB_NMI_MAP 0x0000001FU
#define INTMTX_CORE0_BT_BB_NMI_MAP_M (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S)
#define INTMTX_CORE0_BT_BB_NMI_MAP_V 0x0000001FU
#define INTMTX_CORE0_BT_BB_NMI_MAP_S 0
/** INTMTX_CORE0_LP_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
/** INTMTX_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_TIMER_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_TIMER_INTR_MAP_S)
#define INTMTX_CORE0_LP_TIMER_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_TIMER_INTR_MAP_S 0
/** INTMTX_CORE0_COEX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_COEX_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_COEX_INTR_MAP_M (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S)
#define INTMTX_CORE0_COEX_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_COEX_INTR_MAP_S 0
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S)
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S 0
/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BLE_SEC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S)
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S 0
/** INTMTX_CORE0_I2C_MST_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
/** INTMTX_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_I2C_MST_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2C_MST_INTR_MAP_M (INTMTX_CORE0_I2C_MST_INTR_MAP_V << INTMTX_CORE0_I2C_MST_INTR_MAP_S)
#define INTMTX_CORE0_I2C_MST_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2C_MST_INTR_MAP_S 0
/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_ZB_MAC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S)
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S 0
/** INTMTX_CORE0_PMU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PMU_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PMU_INTR_MAP_M (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S)
#define INTMTX_CORE0_PMU_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PMU_INTR_MAP_S 0
/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_EFUSE_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_EFUSE_INTR_MAP_M (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S)
#define INTMTX_CORE0_EFUSE_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_EFUSE_INTR_MAP_S 0
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S)
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S 0
/** INTMTX_CORE0_LP_UART_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
/** INTMTX_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_UART_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_UART_INTR_MAP_M (INTMTX_CORE0_LP_UART_INTR_MAP_V << INTMTX_CORE0_LP_UART_INTR_MAP_S)
#define INTMTX_CORE0_LP_UART_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_UART_INTR_MAP_S 0
/** INTMTX_CORE0_LP_I2C_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
/** INTMTX_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_I2C_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_I2C_INTR_MAP_M (INTMTX_CORE0_LP_I2C_INTR_MAP_V << INTMTX_CORE0_LP_I2C_INTR_MAP_S)
#define INTMTX_CORE0_LP_I2C_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_I2C_INTR_MAP_S 0
/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_WDT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_WDT_INTR_MAP_M (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S)
#define INTMTX_CORE0_LP_WDT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_WDT_INTR_MAP_S 0
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S)
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S 0
/** INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
/** INTMTX_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_M (INTMTX_CORE0_LP_APM_M1_INTR_MAP_V << INTMTX_CORE0_LP_APM_M1_INTR_MAP_S)
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S)
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TRACE_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TRACE_INTR_MAP_M (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S)
#define INTMTX_CORE0_TRACE_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TRACE_INTR_MAP_S 0
/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CACHE_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CACHE_INTR_MAP_M (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S)
#define INTMTX_CORE0_CACHE_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CACHE_INTR_MAP_S 0
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
/** INTMTX_CORE0_PAU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PAU_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PAU_INTR_MAP_M (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S)
#define INTMTX_CORE0_PAU_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PAU_INTR_MAP_S 0
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S 0
/** INTMTX_CORE0_LP_APM0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
/** INTMTX_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_APM0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_APM0_INTR_MAP_M (INTMTX_CORE0_LP_APM0_INTR_MAP_V << INTMTX_CORE0_LP_APM0_INTR_MAP_S)
#define INTMTX_CORE0_LP_APM0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_APM0_INTR_MAP_S 0
/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_MSPI_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_MSPI_INTR_MAP_M (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S)
#define INTMTX_CORE0_MSPI_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_MSPI_INTR_MAP_S 0
/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_I2S1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_M (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S)
#define INTMTX_CORE0_I2S1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_S 0
/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_UHCI0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_UHCI0_INTR_MAP_M (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S)
#define INTMTX_CORE0_UHCI0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_UHCI0_INTR_MAP_S 0
/** INTMTX_CORE0_UART0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_UART0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_UART0_INTR_MAP_M (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S)
#define INTMTX_CORE0_UART0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_UART0_INTR_MAP_S 0
/** INTMTX_CORE0_UART1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_UART1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_UART1_INTR_MAP_M (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S)
#define INTMTX_CORE0_UART1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_UART1_INTR_MAP_S 0
/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LEDC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LEDC_INTR_MAP_M (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S)
#define INTMTX_CORE0_LEDC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LEDC_INTR_MAP_S 0
/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CAN0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CAN0_INTR_MAP_M (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S)
#define INTMTX_CORE0_CAN0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CAN0_INTR_MAP_S 0
/** INTMTX_CORE0_CAN1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
/** INTMTX_CORE0_CAN1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CAN1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CAN1_INTR_MAP_M (INTMTX_CORE0_CAN1_INTR_MAP_V << INTMTX_CORE0_CAN1_INTR_MAP_S)
#define INTMTX_CORE0_CAN1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CAN1_INTR_MAP_S 0
/** INTMTX_CORE0_USB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_USB_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_USB_INTR_MAP_M (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S)
#define INTMTX_CORE0_USB_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_USB_INTR_MAP_S 0
/** INTMTX_CORE0_RMT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_RMT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_RMT_INTR_MAP_M (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S)
#define INTMTX_CORE0_RMT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_RMT_INTR_MAP_S 0
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S)
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S 0
/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG0_T0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG0_T0_INTR_MAP_M (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S)
#define INTMTX_CORE0_TG0_T0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG0_T0_INTR_MAP_S 0
/** INTMTX_CORE0_TG0_T1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
/** INTMTX_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG0_T1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG0_T1_INTR_MAP_M (INTMTX_CORE0_TG0_T1_INTR_MAP_V << INTMTX_CORE0_TG0_T1_INTR_MAP_S)
#define INTMTX_CORE0_TG0_T1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG0_T1_INTR_MAP_S 0
/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG0_WDT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S)
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S 0
/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG1_T0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG1_T0_INTR_MAP_M (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S)
#define INTMTX_CORE0_TG1_T0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG1_T0_INTR_MAP_S 0
/** INTMTX_CORE0_TG1_T1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
/** INTMTX_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG1_T1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG1_T1_INTR_MAP_M (INTMTX_CORE0_TG1_T1_INTR_MAP_V << INTMTX_CORE0_TG1_T1_INTR_MAP_S)
#define INTMTX_CORE0_TG1_T1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG1_T1_INTR_MAP_S 0
/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG1_WDT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S)
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S 0
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0
/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_APB_ADC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_APB_ADC_INTR_MAP_M (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S)
#define INTMTX_CORE0_APB_ADC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_APB_ADC_INTR_MAP_S 0
/** INTMTX_CORE0_PWM_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PWM_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PWM_INTR_MAP_M (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S)
#define INTMTX_CORE0_PWM_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PWM_INTR_MAP_S 0
/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PCNT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PCNT_INTR_MAP_M (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S)
#define INTMTX_CORE0_PCNT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PCNT_INTR_MAP_S 0
/** INTMTX_CORE0_PARL_IO_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
/** INTMTX_CORE0_PARL_IO_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PARL_IO_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PARL_IO_INTR_MAP_M (INTMTX_CORE0_PARL_IO_INTR_MAP_V << INTMTX_CORE0_PARL_IO_INTR_MAP_S)
#define INTMTX_CORE0_PARL_IO_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PARL_IO_INTR_MAP_S 0
/** INTMTX_CORE0_SLC0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
/** INTMTX_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SLC0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SLC0_INTR_MAP_M (INTMTX_CORE0_SLC0_INTR_MAP_V << INTMTX_CORE0_SLC0_INTR_MAP_S)
#define INTMTX_CORE0_SLC0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SLC0_INTR_MAP_S 0
/** INTMTX_CORE0_SLC1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
/** INTMTX_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SLC1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SLC1_INTR_MAP_M (INTMTX_CORE0_SLC1_INTR_MAP_V << INTMTX_CORE0_SLC1_INTR_MAP_S)
#define INTMTX_CORE0_SLC1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SLC1_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S)
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S)
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S)
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x114)
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S)
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x118)
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S)
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x11c)
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S)
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S 0
/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x120)
/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_GPSPI2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_GPSPI2_INTR_MAP_M (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S)
#define INTMTX_CORE0_GPSPI2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_GPSPI2_INTR_MAP_S 0
/** INTMTX_CORE0_AES_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x124)
/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_AES_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_AES_INTR_MAP_M (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S)
#define INTMTX_CORE0_AES_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_AES_INTR_MAP_S 0
/** INTMTX_CORE0_SHA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x128)
/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SHA_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SHA_INTR_MAP_M (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S)
#define INTMTX_CORE0_SHA_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SHA_INTR_MAP_S 0
/** INTMTX_CORE0_RSA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x12c)
/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_RSA_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_RSA_INTR_MAP_M (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S)
#define INTMTX_CORE0_RSA_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_RSA_INTR_MAP_S 0
/** INTMTX_CORE0_ECC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x130)
/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_ECC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ECC_INTR_MAP_M (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S)
#define INTMTX_CORE0_ECC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ECC_INTR_MAP_S 0
/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x134)
/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_INT_STATUS_0 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_0_M (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S)
#define INTMTX_CORE0_INT_STATUS_0_V 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_0_S 0
/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x138)
/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_INT_STATUS_1 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_1_M (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S)
#define INTMTX_CORE0_INT_STATUS_1_V 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_1_S 0
/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x13c)
/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_INT_STATUS_2 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_2_M (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S)
#define INTMTX_CORE0_INT_STATUS_2_V 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_2_S 0
/** INTMTX_CORE0_CLOCK_GATE_REG register
* register description
*/
#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x140)
/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define INTMTX_CORE0_REG_CLK_EN (BIT(0))
#define INTMTX_CORE0_REG_CLK_EN_M (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S)
#define INTMTX_CORE0_REG_CLK_EN_V 0x00000001U
#define INTMTX_CORE0_REG_CLK_EN_S 0
/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
* register description
*/
#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35664144;
* Need add description
*/
#define INTMTX_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU
#define INTMTX_CORE0_INTERRUPT_REG_DATE_M (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S)
#define INTMTX_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU
#define INTMTX_CORE0_INTERRUPT_REG_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CORE0_CPU_INT_ENABLE_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTPRI_BASE + 0x0)
/** INTPRI_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_ENABLE 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_ENABLE_M (INTPRI_CORE0_CPU_INT_ENABLE_V << INTPRI_CORE0_CPU_INT_ENABLE_S)
#define INTPRI_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_ENABLE_S 0
/** INTPRI_CORE0_CPU_INT_TYPE_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_TYPE_REG (DR_REG_INTPRI_BASE + 0x4)
/** INTPRI_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_TYPE 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_TYPE_M (INTPRI_CORE0_CPU_INT_TYPE_V << INTPRI_CORE0_CPU_INT_TYPE_S)
#define INTPRI_CORE0_CPU_INT_TYPE_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_TYPE_S 0
/** INTPRI_CORE0_CPU_INT_EIP_STATUS_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTPRI_BASE + 0x8)
/** INTPRI_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_M (INTPRI_CORE0_CPU_INT_EIP_STATUS_V << INTPRI_CORE0_CPU_INT_EIP_STATUS_S)
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_S 0
/** INTPRI_CORE0_CPU_INT_PRI_0_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTPRI_BASE + 0xc)
/** INTPRI_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_0_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_0_MAP_M (INTPRI_CORE0_CPU_PRI_0_MAP_V << INTPRI_CORE0_CPU_PRI_0_MAP_S)
#define INTPRI_CORE0_CPU_PRI_0_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_0_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_1_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTPRI_BASE + 0x10)
/** INTPRI_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_1_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_1_MAP_M (INTPRI_CORE0_CPU_PRI_1_MAP_V << INTPRI_CORE0_CPU_PRI_1_MAP_S)
#define INTPRI_CORE0_CPU_PRI_1_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_1_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_2_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTPRI_BASE + 0x14)
/** INTPRI_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_2_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_2_MAP_M (INTPRI_CORE0_CPU_PRI_2_MAP_V << INTPRI_CORE0_CPU_PRI_2_MAP_S)
#define INTPRI_CORE0_CPU_PRI_2_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_2_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_3_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTPRI_BASE + 0x18)
/** INTPRI_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_3_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_3_MAP_M (INTPRI_CORE0_CPU_PRI_3_MAP_V << INTPRI_CORE0_CPU_PRI_3_MAP_S)
#define INTPRI_CORE0_CPU_PRI_3_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_3_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_4_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTPRI_BASE + 0x1c)
/** INTPRI_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_4_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_4_MAP_M (INTPRI_CORE0_CPU_PRI_4_MAP_V << INTPRI_CORE0_CPU_PRI_4_MAP_S)
#define INTPRI_CORE0_CPU_PRI_4_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_4_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_5_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTPRI_BASE + 0x20)
/** INTPRI_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_5_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_5_MAP_M (INTPRI_CORE0_CPU_PRI_5_MAP_V << INTPRI_CORE0_CPU_PRI_5_MAP_S)
#define INTPRI_CORE0_CPU_PRI_5_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_5_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_6_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTPRI_BASE + 0x24)
/** INTPRI_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_6_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_6_MAP_M (INTPRI_CORE0_CPU_PRI_6_MAP_V << INTPRI_CORE0_CPU_PRI_6_MAP_S)
#define INTPRI_CORE0_CPU_PRI_6_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_6_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_7_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTPRI_BASE + 0x28)
/** INTPRI_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_7_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_7_MAP_M (INTPRI_CORE0_CPU_PRI_7_MAP_V << INTPRI_CORE0_CPU_PRI_7_MAP_S)
#define INTPRI_CORE0_CPU_PRI_7_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_7_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_8_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTPRI_BASE + 0x2c)
/** INTPRI_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_8_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_8_MAP_M (INTPRI_CORE0_CPU_PRI_8_MAP_V << INTPRI_CORE0_CPU_PRI_8_MAP_S)
#define INTPRI_CORE0_CPU_PRI_8_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_8_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_9_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTPRI_BASE + 0x30)
/** INTPRI_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_9_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_9_MAP_M (INTPRI_CORE0_CPU_PRI_9_MAP_V << INTPRI_CORE0_CPU_PRI_9_MAP_S)
#define INTPRI_CORE0_CPU_PRI_9_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_9_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_10_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTPRI_BASE + 0x34)
/** INTPRI_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_10_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_10_MAP_M (INTPRI_CORE0_CPU_PRI_10_MAP_V << INTPRI_CORE0_CPU_PRI_10_MAP_S)
#define INTPRI_CORE0_CPU_PRI_10_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_10_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_11_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTPRI_BASE + 0x38)
/** INTPRI_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_11_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_11_MAP_M (INTPRI_CORE0_CPU_PRI_11_MAP_V << INTPRI_CORE0_CPU_PRI_11_MAP_S)
#define INTPRI_CORE0_CPU_PRI_11_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_11_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_12_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTPRI_BASE + 0x3c)
/** INTPRI_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_12_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_12_MAP_M (INTPRI_CORE0_CPU_PRI_12_MAP_V << INTPRI_CORE0_CPU_PRI_12_MAP_S)
#define INTPRI_CORE0_CPU_PRI_12_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_12_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_13_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTPRI_BASE + 0x40)
/** INTPRI_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_13_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_13_MAP_M (INTPRI_CORE0_CPU_PRI_13_MAP_V << INTPRI_CORE0_CPU_PRI_13_MAP_S)
#define INTPRI_CORE0_CPU_PRI_13_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_13_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_14_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTPRI_BASE + 0x44)
/** INTPRI_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_14_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_14_MAP_M (INTPRI_CORE0_CPU_PRI_14_MAP_V << INTPRI_CORE0_CPU_PRI_14_MAP_S)
#define INTPRI_CORE0_CPU_PRI_14_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_14_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_15_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTPRI_BASE + 0x48)
/** INTPRI_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_15_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_15_MAP_M (INTPRI_CORE0_CPU_PRI_15_MAP_V << INTPRI_CORE0_CPU_PRI_15_MAP_S)
#define INTPRI_CORE0_CPU_PRI_15_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_15_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_16_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTPRI_BASE + 0x4c)
/** INTPRI_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_16_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_16_MAP_M (INTPRI_CORE0_CPU_PRI_16_MAP_V << INTPRI_CORE0_CPU_PRI_16_MAP_S)
#define INTPRI_CORE0_CPU_PRI_16_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_16_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_17_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTPRI_BASE + 0x50)
/** INTPRI_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_17_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_17_MAP_M (INTPRI_CORE0_CPU_PRI_17_MAP_V << INTPRI_CORE0_CPU_PRI_17_MAP_S)
#define INTPRI_CORE0_CPU_PRI_17_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_17_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_18_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTPRI_BASE + 0x54)
/** INTPRI_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_18_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_18_MAP_M (INTPRI_CORE0_CPU_PRI_18_MAP_V << INTPRI_CORE0_CPU_PRI_18_MAP_S)
#define INTPRI_CORE0_CPU_PRI_18_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_18_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_19_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTPRI_BASE + 0x58)
/** INTPRI_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_19_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_19_MAP_M (INTPRI_CORE0_CPU_PRI_19_MAP_V << INTPRI_CORE0_CPU_PRI_19_MAP_S)
#define INTPRI_CORE0_CPU_PRI_19_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_19_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_20_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTPRI_BASE + 0x5c)
/** INTPRI_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_20_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_20_MAP_M (INTPRI_CORE0_CPU_PRI_20_MAP_V << INTPRI_CORE0_CPU_PRI_20_MAP_S)
#define INTPRI_CORE0_CPU_PRI_20_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_20_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_21_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTPRI_BASE + 0x60)
/** INTPRI_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_21_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_21_MAP_M (INTPRI_CORE0_CPU_PRI_21_MAP_V << INTPRI_CORE0_CPU_PRI_21_MAP_S)
#define INTPRI_CORE0_CPU_PRI_21_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_21_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_22_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTPRI_BASE + 0x64)
/** INTPRI_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_22_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_22_MAP_M (INTPRI_CORE0_CPU_PRI_22_MAP_V << INTPRI_CORE0_CPU_PRI_22_MAP_S)
#define INTPRI_CORE0_CPU_PRI_22_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_22_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_23_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTPRI_BASE + 0x68)
/** INTPRI_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_23_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_23_MAP_M (INTPRI_CORE0_CPU_PRI_23_MAP_V << INTPRI_CORE0_CPU_PRI_23_MAP_S)
#define INTPRI_CORE0_CPU_PRI_23_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_23_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_24_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTPRI_BASE + 0x6c)
/** INTPRI_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_24_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_24_MAP_M (INTPRI_CORE0_CPU_PRI_24_MAP_V << INTPRI_CORE0_CPU_PRI_24_MAP_S)
#define INTPRI_CORE0_CPU_PRI_24_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_24_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_25_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTPRI_BASE + 0x70)
/** INTPRI_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_25_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_25_MAP_M (INTPRI_CORE0_CPU_PRI_25_MAP_V << INTPRI_CORE0_CPU_PRI_25_MAP_S)
#define INTPRI_CORE0_CPU_PRI_25_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_25_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_26_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTPRI_BASE + 0x74)
/** INTPRI_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_26_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_26_MAP_M (INTPRI_CORE0_CPU_PRI_26_MAP_V << INTPRI_CORE0_CPU_PRI_26_MAP_S)
#define INTPRI_CORE0_CPU_PRI_26_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_26_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_27_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTPRI_BASE + 0x78)
/** INTPRI_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_27_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_27_MAP_M (INTPRI_CORE0_CPU_PRI_27_MAP_V << INTPRI_CORE0_CPU_PRI_27_MAP_S)
#define INTPRI_CORE0_CPU_PRI_27_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_27_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_28_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTPRI_BASE + 0x7c)
/** INTPRI_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_28_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_28_MAP_M (INTPRI_CORE0_CPU_PRI_28_MAP_V << INTPRI_CORE0_CPU_PRI_28_MAP_S)
#define INTPRI_CORE0_CPU_PRI_28_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_28_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_29_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTPRI_BASE + 0x80)
/** INTPRI_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_29_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_29_MAP_M (INTPRI_CORE0_CPU_PRI_29_MAP_V << INTPRI_CORE0_CPU_PRI_29_MAP_S)
#define INTPRI_CORE0_CPU_PRI_29_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_29_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_30_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTPRI_BASE + 0x84)
/** INTPRI_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_30_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_30_MAP_M (INTPRI_CORE0_CPU_PRI_30_MAP_V << INTPRI_CORE0_CPU_PRI_30_MAP_S)
#define INTPRI_CORE0_CPU_PRI_30_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_30_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_31_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTPRI_BASE + 0x88)
/** INTPRI_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_31_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_31_MAP_M (INTPRI_CORE0_CPU_PRI_31_MAP_V << INTPRI_CORE0_CPU_PRI_31_MAP_S)
#define INTPRI_CORE0_CPU_PRI_31_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_31_MAP_S 0
/** INTPRI_CORE0_CPU_INT_THRESH_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_THRESH_REG (DR_REG_INTPRI_BASE + 0x8c)
/** INTPRI_CORE0_CPU_INT_THRESH : R/W; bitpos: [7:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_THRESH 0x000000FFU
#define INTPRI_CORE0_CPU_INT_THRESH_M (INTPRI_CORE0_CPU_INT_THRESH_V << INTPRI_CORE0_CPU_INT_THRESH_S)
#define INTPRI_CORE0_CPU_INT_THRESH_V 0x000000FFU
#define INTPRI_CORE0_CPU_INT_THRESH_S 0
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_0_S 0
/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_1_S 0
/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_2_S 0
/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_3_S 0
/** INTPRI_DATE_REG register
* register description
*/
#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 35655824;
* Need add description
*/
#define INTPRI_DATE 0x0FFFFFFFU
#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S)
#define INTPRI_DATE_V 0x0FFFFFFFU
#define INTPRI_DATE_S 0
/** INTPRI_CLOCK_GATE_REG register
* register description
*/
#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define INTPRI_CLK_EN (BIT(0))
#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
#define INTPRI_CLK_EN_V 0x00000001U
#define INTPRI_CLK_EN_S 0
/** INTPRI_CORE0_CPU_INT_CLEAR_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTPRI_BASE + 0xa8)
/** INTPRI_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_CLEAR 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_CLEAR_M (INTPRI_CORE0_CPU_INT_CLEAR_V << INTPRI_CORE0_CPU_INT_CLEAR_S)
#define INTPRI_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_CLEAR_S 0
/** INTPRI_RND_ECO_REG register
* redcy eco register.
*/
#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac)
/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_ENA (BIT(0))
#define INTPRI_REDCY_ENA_M (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S)
#define INTPRI_REDCY_ENA_V 0x00000001U
#define INTPRI_REDCY_ENA_S 0
/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_RESULT (BIT(1))
#define INTPRI_REDCY_RESULT_M (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S)
#define INTPRI_REDCY_RESULT_V 0x00000001U
#define INTPRI_REDCY_RESULT_S 1
/** INTPRI_RND_ECO_LOW_REG register
* redcy eco low register.
*/
#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0)
/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_LOW 0xFFFFFFFFU
#define INTPRI_REDCY_LOW_M (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S)
#define INTPRI_REDCY_LOW_V 0xFFFFFFFFU
#define INTPRI_REDCY_LOW_S 0
/** INTPRI_RND_ECO_HIGH_REG register
* redcy eco high register.
*/
#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc)
/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_HIGH 0xFFFFFFFFU
#define INTPRI_REDCY_HIGH_M (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S)
#define INTPRI_REDCY_HIGH_V 0xFFFFFFFFU
#define INTPRI_REDCY_HIGH_S 0
#ifdef __cplusplus
}
#endif

256
components/soc/esp32c6/include/soc/intpri_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of core0_cpu_int_enable register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_enable:32;
};
uint32_t val;
} intpri_core0_cpu_int_enable_reg_t;
/** Type of core0_cpu_int_type register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_type : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_type:32;
};
uint32_t val;
} intpri_core0_cpu_int_type_reg_t;
/** Type of core0_cpu_int_eip_status register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_eip_status : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_eip_status:32;
};
uint32_t val;
} intpri_core0_cpu_int_eip_status_reg_t;
/** Type of core0_cpu_int_pri_n register
* register description
*/
typedef union {
struct {
/** map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_n_reg_t;
/** Type of core0_cpu_int_thresh register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_thresh : R/W; bitpos: [7:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_thresh:8;
uint32_t reserved_8:24;
};
uint32_t val;
} intpri_core0_cpu_int_thresh_reg_t;
/** Type of clock_gate register
* register description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_clock_gate_reg_t;
/** Type of core0_cpu_int_clear register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_clear : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_clear:32;
};
uint32_t val;
} intpri_core0_cpu_int_clear_reg_t;
/** Group: Interrupt Registers */
/** Type of cpu_intr_from_cpu_0 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_0:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_0_reg_t;
/** Type of cpu_intr_from_cpu_1 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_1:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_1_reg_t;
/** Type of cpu_intr_from_cpu_2 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_2:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_2_reg_t;
/** Type of cpu_intr_from_cpu_3 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_3:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_3_reg_t;
/** Group: Version Registers */
/** Type of date register
* register description
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35655824;
* Need add description
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} intpri_date_reg_t;
/** Group: Redcy ECO Registers */
/** Type of rnd_eco register
* redcy eco register.
*/
typedef union {
struct {
/** redcy_ena : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_ena:1;
/** redcy_result : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} intpri_rnd_eco_reg_t;
/** Type of rnd_eco_low register
* redcy eco low register.
*/
typedef union {
struct {
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_low:32;
};
uint32_t val;
} intpri_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* redcy eco high register.
*/
typedef union {
struct {
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
uint32_t redcy_high:32;
};
uint32_t val;
} intpri_rnd_eco_high_reg_t;
typedef struct intpri_dev_t {
volatile intpri_core0_cpu_int_enable_reg_t core0_cpu_int_enable;
volatile intpri_core0_cpu_int_type_reg_t core0_cpu_int_type;
volatile intpri_core0_cpu_int_eip_status_reg_t core0_cpu_int_eip_status;
volatile intpri_core0_cpu_int_pri_n_reg_t core0_cpu_int_pri[32];
volatile intpri_core0_cpu_int_thresh_reg_t core0_cpu_int_thresh;
volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
volatile intpri_date_reg_t date;
volatile intpri_clock_gate_reg_t clock_gate;
volatile intpri_core0_cpu_int_clear_reg_t core0_cpu_int_clear;
volatile intpri_rnd_eco_reg_t rnd_eco;
volatile intpri_rnd_eco_low_reg_t rnd_eco_low;
uint32_t reserved_0b4[210];
volatile intpri_rnd_eco_high_reg_t rnd_eco_high;
} intpri_dev_t;
extern intpri_dev_t INTPRI;
#ifndef __cplusplus
_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/io_mux_reg.h Normal file
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_GPIO15_U
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_SDIO_CMD_U
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_SDIO_CLK_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_SDIO_DATA0_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_SDIO_DATA1_U
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_SDIO_DATA2_U
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_SDIO_DATA3_U
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_SPICS0_U
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_SPIQ_U
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPIWP_U
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_VDD_SPI_U
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIHD_U
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICLK_U
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPID_U
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define SPI_HD_GPIO_NUM 28
#define SPI_WP_GPIO_NUM 26
#define SPI_CS0_GPIO_NUM 24
#define SPI_CLK_GPIO_NUM 29
#define SPI_D_GPIO_NUM 30
#define SPI_Q_GPIO_NUM 25
#define SD_CLK_GPIO_NUM 19
#define SD_CMD_GPIO_NUM 18
#define SD_DATA0_GPIO_NUM 20
#define SD_DATA1_GPIO_NUM 21
#define SD_DATA2_GPIO_NUM 22
#define SD_DATA3_GPIO_NUM 23
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 30
#define MAX_GPIO_NUM 34
#define DIG_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0xf
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 4
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0xf
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x4)
#define FUNC_XTAL_32K_P_GPIO0 1
#define FUNC_XTAL_32K_P_GPIO0_0 0
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x8)
#define FUNC_XTAL_32K_N_GPIO1 1
#define FUNC_XTAL_32K_N_GPIO1_0 0
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0xC)
#define FUNC_GPIO2_FSPIQ 2
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE + 0x10)
#define FUNC_GPIO3_GPIO3 1
#define FUNC_GPIO3_GPIO3_0 0
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x14)
#define FUNC_MTMS_FSPIHD 2
#define FUNC_MTMS_GPIO4 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18)
#define FUNC_MTDI_FSPIWP 2
#define FUNC_MTDI_GPIO5 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x1C)
#define FUNC_MTCK_FSPICLK 2
#define FUNC_MTCK_GPIO6 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x20)
#define FUNC_MTDO_FSPID 2
#define FUNC_MTDO_GPIO7 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28)
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2C)
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_GPIO10_0 0
#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE + 0x30)
#define FUNC_GPIO11_GPIO11 1
#define FUNC_GPIO11_GPIO11_0 0
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE + 0x38)
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GPIO13_0 0
#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE + 0x3C)
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_GPIO14_0 0
#define PERIPHS_IO_MUX_GPIO15_U (REG_IO_MUX_BASE + 0x40)
#define FUNC_GPIO15_GPIO15 1
#define FUNC_GPIO15_GPIO15_0 0
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x44)
#define FUNC_U0TXD_FSPICS0 2
#define FUNC_U0TXD_GPIO16 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x48)
#define FUNC_U0RXD_FSPICS1 2
#define FUNC_U0RXD_GPIO17 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_SDIO_CMD_U (REG_IO_MUX_BASE + 0x4C)
#define FUNC_SDIO_CMD_FSPICS2 2
#define FUNC_SDIO_CMD_GPIO18 1
#define FUNC_SDIO_CMD_SDIO_CMD 0
#define PERIPHS_IO_MUX_SDIO_CLK_U (REG_IO_MUX_BASE + 0x50)
#define FUNC_SDIO_CLK_FSPICS3 2
#define FUNC_SDIO_CLK_GPIO19 1
#define FUNC_SDIO_CLK_SDIO_CLK 0
#define PERIPHS_IO_MUX_SDIO_DATA0_U (REG_IO_MUX_BASE + 0x54)
#define FUNC_SDIO_DATA0_FSPICS4 2
#define FUNC_SDIO_DATA0_GPIO20 1
#define FUNC_SDIO_DATA0_SDIO_DATA0 0
#define PERIPHS_IO_MUX_SDIO_DATA1_U (REG_IO_MUX_BASE + 0x58)
#define FUNC_SDIO_DATA1_FSPICS5 2
#define FUNC_SDIO_DATA1_GPIO21 1
#define FUNC_SDIO_DATA1_SDIO_DATA1 0
#define PERIPHS_IO_MUX_SDIO_DATA2_U (REG_IO_MUX_BASE + 0x5C)
#define FUNC_SDIO_DATA2_GPIO22 1
#define FUNC_SDIO_DATA2_SDIO_DATA2 0
#define PERIPHS_IO_MUX_SDIO_DATA3_U (REG_IO_MUX_BASE + 0x60)
#define FUNC_SDIO_DATA3_GPIO23 1
#define FUNC_SDIO_DATA3_SDIO_DATA3 0
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x64)
#define FUNC_SPICS0_GPIO24 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x68)
#define FUNC_SPIQ_GPIO25 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x6C)
#define FUNC_SPIWP_GPIO26 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x70)
#define FUNC_VDD_SPI_GPIO27 1
#define FUNC_VDD_SPI_GPIO27_0 0
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x74)
#define FUNC_SPIHD_GPIO28 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x78)
#define FUNC_SPICLK_GPIO29 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x7C)
#define FUNC_SPID_GPIO30 1
#define FUNC_SPID_SPID 0
/** IO_MUX_PIN_CTRL_REG register
* Clock Output Configuration Register
*/
#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
/** IO_MUX_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
* CLK_OUT_out1 can be found in peripheral output signals.
*/
#define IO_MUX_CLK_OUT1 0x0000001FU
#define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
#define IO_MUX_CLK_OUT1_V 0x0000001FU
#define IO_MUX_CLK_OUT1_S 0
/** IO_MUX_CLK_OUT2 : R/W; bitpos: [9:5]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
* CLK_OUT_out2 can be found in peripheral output signals.
*/
#define IO_MUX_CLK_OUT2 0x0000001FU
#define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
#define IO_MUX_CLK_OUT2_V 0x0000001FU
#define IO_MUX_CLK_OUT2_S 5
/** IO_MUX_CLK_OUT3 : R/W; bitpos: [14:10]; default: 7;
* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
* CLK_OUT_out3 can be found in peripheral output signals.
*/
#define IO_MUX_CLK_OUT3 0x0000001FU
#define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
#define IO_MUX_CLK_OUT3_V 0x0000001FU
#define IO_MUX_CLK_OUT3_S 10
/** IO_MUX_MODEM_DIAG_EN_REG register
* GPIO MATRIX Configure Register for modem diag
*/
#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc)
/** IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [31:0]; default: 0;
* bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio
* matrix. 0:enable other signals into gpio matrix
*/
#define IO_MUX_MODEM_DIAG_EN 0xFFFFFFFFU
#define IO_MUX_MODEM_DIAG_EN_M (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S)
#define IO_MUX_MODEM_DIAG_EN_V 0xFFFFFFFFU
#define IO_MUX_MODEM_DIAG_EN_S 0
/** IO_MUX_DATE_REG register
* IO MUX Version Control Register
*/
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 35655776;
* Version control register
*/
#define IO_MUX_REG_DATE 0x0FFFFFFFU
#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
#define IO_MUX_REG_DATE_V 0x0FFFFFFFU
#define IO_MUX_REG_DATE_S 0

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNTL_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x0)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_PD_RF_ENA_S 7
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_WAIT_S 8
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_WAIT_S 18
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR (BIT(28))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_CNT_CLR_S 28
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA (BIT(29))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INTR_ENA_S 29
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL (BIT(30))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_SEL_S 30
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_RESET_ENA_S 31
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x4)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA_S 31
/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x8)
/** LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA_S 31
/** LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0xc)
/** LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU
#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_M (LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_V << LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU
#define LP_ANALOG_PERI_LP_ANA_ANA_FIB_ENA_S 0
#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
#define LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST BIT(1)
#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
/** LP_ANALOG_PERI_LP_ANA_INT_RAW_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x10)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_RAW_S 31
/** LP_ANALOG_PERI_LP_ANA_INT_ST_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ST_S 31
/** LP_ANALOG_PERI_LP_ANA_INT_ENA_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x18)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_ENA_S 31
/** LP_ANALOG_PERI_LP_ANA_INT_CLR_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_INT_CLR_S 31
/** LP_ANALOG_PERI_LP_ANA_LP_INT_RAW_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x20)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_RAW_S 31
/** LP_ANALOG_PERI_LP_ANA_LP_INT_ST_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x24)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ST_S 31
/** LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x28)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA_S 31
/** LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x2c)
/** LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_S)
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR_S 31
/** LP_ANALOG_PERI_LP_ANA_DATE_REG register
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_DATE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3fc)
/** LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 35660384;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE 0x7FFFFFFFU
#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_M (LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_V << LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_S)
#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_V 0x7FFFFFFFU
#define LP_ANALOG_PERI_LP_ANA_LP_ANALOG_PERI_LP_ANA_DATE_S 0
/** LP_ANALOG_PERI_LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANA_CLK_EN (BIT(31))
#define LP_ANALOG_PERI_LP_ANA_CLK_EN_M (LP_ANALOG_PERI_LP_ANA_CLK_EN_V << LP_ANALOG_PERI_LP_ANA_CLK_EN_S)
#define LP_ANALOG_PERI_LP_ANA_CLK_EN_V 0x00000001U
#define LP_ANALOG_PERI_LP_ANA_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of bod_mode0_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
* need_des
*/
uint32_t bod_mode0_close_flash_ena:1;
/** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
* need_des
*/
uint32_t bod_mode0_pd_rf_ena:1;
/** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
* need_des
*/
uint32_t bod_mode0_intr_wait:10;
/** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
* need_des
*/
uint32_t bod_mode0_reset_wait:10;
/** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t bod_mode0_cnt_clr:1;
/** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t bod_mode0_intr_ena:1;
/** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t bod_mode0_reset_sel:1;
/** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode0_cntl_reg_t;
/** Type of bod_mode1_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode1_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode1_cntl_reg_t;
/** Type of ck_glitch_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_ana_ck_glitch_cntl_reg_t;
/** Type of fib_enable register
* need_des
*/
typedef union {
struct {
/** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
*/
uint32_t ana_fib_ena:32;
};
uint32_t val;
} lp_ana_fib_enable_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0 : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0:1;
};
uint32_t val;
} lp_ana_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0 : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0:1;
};
uint32_t val;
} lp_ana_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0 : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0:1;
};
uint32_t val;
} lp_ana_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0:1;
};
uint32_t val;
} lp_ana_int_clr_reg_t;
/** Type of lp_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0 : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0:1;
};
uint32_t val;
} lp_ana_lp_int_raw_reg_t;
/** Type of lp_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0 : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0:1;
};
uint32_t val;
} lp_ana_lp_int_st_reg_t;
/** Type of lp_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0 : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0:1;
};
uint32_t val;
} lp_ana_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0:1;
};
uint32_t val;
} lp_ana_lp_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lp_ana_date : R/W; bitpos: [30:0]; default: 35660384;
* need_des
*/
uint32_t lp_ana_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_ana_date_reg_t;
typedef struct lp_ana_dev_t {
volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
volatile lp_ana_fib_enable_reg_t fib_enable;
volatile lp_ana_int_raw_reg_t int_raw;
volatile lp_ana_int_st_reg_t int_st;
volatile lp_ana_int_ena_reg_t int_ena;
volatile lp_ana_int_clr_reg_t int_clr;
volatile lp_ana_lp_int_raw_reg_t lp_int_raw;
volatile lp_ana_lp_int_st_reg_t lp_int_st;
volatile lp_ana_lp_int_ena_reg_t lp_int_ena;
volatile lp_ana_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_030[243];
volatile lp_ana_date_reg_t date;
} lp_ana_dev_t;
extern lp_ana_dev_t LP_ANA_PERI;
#ifndef __cplusplus
_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_AON_STORE0_REG register
* need_des
*/
#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
/** LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE0 0xFFFFFFFFU
#define LP_AON_STORE0_M (LP_AON_STORE0_V << LP_AON_STORE0_S)
#define LP_AON_STORE0_V 0xFFFFFFFFU
#define LP_AON_STORE0_S 0
/** LP_AON_STORE1_REG register
* need_des
*/
#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
/** LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE1 0xFFFFFFFFU
#define LP_AON_STORE1_M (LP_AON_STORE1_V << LP_AON_STORE1_S)
#define LP_AON_STORE1_V 0xFFFFFFFFU
#define LP_AON_STORE1_S 0
/** LP_AON_STORE2_REG register
* need_des
*/
#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
/** LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE2 0xFFFFFFFFU
#define LP_AON_STORE2_M (LP_AON_STORE2_V << LP_AON_STORE2_S)
#define LP_AON_STORE2_V 0xFFFFFFFFU
#define LP_AON_STORE2_S 0
/** LP_AON_STORE3_REG register
* need_des
*/
#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
/** LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE3 0xFFFFFFFFU
#define LP_AON_STORE3_M (LP_AON_STORE3_V << LP_AON_STORE3_S)
#define LP_AON_STORE3_V 0xFFFFFFFFU
#define LP_AON_STORE3_S 0
/** LP_AON_STORE4_REG register
* need_des
*/
#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
/** LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE4 0xFFFFFFFFU
#define LP_AON_STORE4_M (LP_AON_STORE4_V << LP_AON_STORE4_S)
#define LP_AON_STORE4_V 0xFFFFFFFFU
#define LP_AON_STORE4_S 0
/** LP_AON_STORE5_REG register
* need_des
*/
#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
/** LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE5 0xFFFFFFFFU
#define LP_AON_STORE5_M (LP_AON_STORE5_V << LP_AON_STORE5_S)
#define LP_AON_STORE5_V 0xFFFFFFFFU
#define LP_AON_STORE5_S 0
/** LP_AON_STORE6_REG register
* need_des
*/
#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
/** LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE6 0xFFFFFFFFU
#define LP_AON_STORE6_M (LP_AON_STORE6_V << LP_AON_STORE6_S)
#define LP_AON_STORE6_V 0xFFFFFFFFU
#define LP_AON_STORE6_S 0
/** LP_AON_STORE7_REG register
* need_des
*/
#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
/** LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE7 0xFFFFFFFFU
#define LP_AON_STORE7_M (LP_AON_STORE7_V << LP_AON_STORE7_S)
#define LP_AON_STORE7_V 0xFFFFFFFFU
#define LP_AON_STORE7_S 0
/** LP_AON_STORE8_REG register
* need_des
*/
#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
/** LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE8 0xFFFFFFFFU
#define LP_AON_STORE8_M (LP_AON_STORE8_V << LP_AON_STORE8_S)
#define LP_AON_STORE8_V 0xFFFFFFFFU
#define LP_AON_STORE8_S 0
/** LP_AON_STORE9_REG register
* need_des
*/
#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
/** LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE9 0xFFFFFFFFU
#define LP_AON_STORE9_M (LP_AON_STORE9_V << LP_AON_STORE9_S)
#define LP_AON_STORE9_V 0xFFFFFFFFU
#define LP_AON_STORE9_S 0
/** LP_AON_GPIO_MUX_REG register
* need_des
*/
#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_MUX_SEL 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_S 0
/** LP_AON_GPIO_HOLD0_REG register
* need_des
*/
#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_S 0
/** LP_AON_GPIO_HOLD1_REG register
* need_des
*/
#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_S 0
/** LP_AON_SYS_CFG_REG register
* need_des
*/
#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30))
#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U
#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30
/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_HPSYS_SW_RESET (BIT(31))
#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
#define LP_AON_HPSYS_SW_RESET_V 0x00000001U
#define LP_AON_HPSYS_SW_RESET_S 31
/** LP_AON_CPUCORE0_CFG_REG register
* need_des
*/
#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_S 0
/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_SW_RESET (BIT(28))
#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_SW_RESET_S 28
/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29))
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29
/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30))
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30
/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31))
#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U
#define LP_AON_CPU_CORE0_DRESET_MASK_S 31
/** LP_AON_IO_MUX_REG register
* need_des
*/
#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31))
#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U
#define LP_AON_IO_MUX_RESET_DISABLE_S 31
/** LP_AON_EXT_WAKEUP_CNTL_REG register
* need_des
*/
#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_S 0
/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14))
#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U
#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14
/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_S 15
/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_LV 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_S 23
/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_FILTER (BIT(31))
#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U
#define LP_AON_EXT_WAKEUP_FILTER_S 31
/** LP_AON_USB_REG register
* need_des
*/
#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44)
/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_USB_RESET_DISABLE (BIT(31))
#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
#define LP_AON_USB_RESET_DISABLE_V 0x00000001U
#define LP_AON_USB_RESET_DISABLE_S 31
/** LP_AON_LPBUS_REG register
* need_des
*/
#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0;
* This field controls fast memory WPULSE parameter.
*/
#define LP_AON_FAST_MEM_WPULSE 0x00000007U
#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S)
#define LP_AON_FAST_MEM_WPULSE_V 0x00000007U
#define LP_AON_FAST_MEM_WPULSE_S 16
/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4;
* This field controls fast memory WA parameter.
*/
#define LP_AON_FAST_MEM_WA 0x00000007U
#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S)
#define LP_AON_FAST_MEM_WA_V 0x00000007U
#define LP_AON_FAST_MEM_WA_S 19
/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0;
* This field controls fast memory RA parameter.
*/
#define LP_AON_FAST_MEM_RA 0x00000003U
#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S)
#define LP_AON_FAST_MEM_RA_V 0x00000003U
#define LP_AON_FAST_MEM_RA_S 22
/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28))
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28
/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29))
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29
/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30))
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30
/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL (BIT(31))
#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_S 31
/** LP_AON_SDIO_ACTIVE_REG register
* need_des
*/
#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
#define LP_AON_SDIO_ACT_DNUM 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_S 22
/** LP_AON_LPCORE_REG register
* need_des
*/
#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50)
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1
/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_DISABLE (BIT(31))
#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S)
#define LP_AON_LPCORE_DISABLE_V 0x00000001U
#define LP_AON_LPCORE_DISABLE_S 31
/** LP_AON_SAR_CCT_REG register
* need_des
*/
#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
#define LP_AON_SAR2_PWDET_CCT 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_S 29
/** LP_AON_DATE_REG register
* need_des
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 35672704;
* need_des
*/
#define LP_AON_DATE 0x7FFFFFFFU
#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S)
#define LP_AON_DATE_V 0x7FFFFFFFU
#define LP_AON_DATE_S 0
/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_CLK_EN (BIT(31))
#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
#define LP_AON_CLK_EN_V 0x00000001U
#define LP_AON_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of store register
* need_des
*/
typedef union {
struct {
/** store : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t store:32;
};
uint32_t val;
} lp_aon_store_reg_t;
/** Type of gpio_mux register
* need_des
*/
typedef union {
struct {
/** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t gpio_mux_sel:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_aon_gpio_mux_reg_t;
/** Type of gpio_hold0 register
* need_des
*/
typedef union {
struct {
/** gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t gpio_hold0:32;
};
uint32_t val;
} lp_aon_gpio_hold0_reg_t;
/** Type of gpio_hold1 register
* need_des
*/
typedef union {
struct {
/** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t gpio_hold1:32;
};
uint32_t val;
} lp_aon_gpio_hold1_reg_t;
/** Type of sys_cfg register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** force_download_boot : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t force_download_boot:1;
/** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t hpsys_sw_reset:1;
};
uint32_t val;
} lp_aon_sys_cfg_reg_t;
/** Type of cpucore0_cfg register
* need_des
*/
typedef union {
struct {
/** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t cpu_core0_sw_stall:8;
uint32_t reserved_8:20;
/** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t cpu_core0_sw_reset:1;
/** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t cpu_core0_ocd_halt_on_reset:1;
/** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t cpu_core0_stat_vector_sel:1;
/** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t cpu_core0_dreset_mask:1;
};
uint32_t val;
} lp_aon_cpucore0_cfg_reg_t;
/** Type of io_mux register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t io_mux_reset_disable:1;
};
uint32_t val;
} lp_aon_io_mux_reg_t;
/** Type of ext_wakeup_cntl register
* need_des
*/
typedef union {
struct {
/** ext_wakeup_status : RO; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t ext_wakeup_status:8;
uint32_t reserved_8:6;
/** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0;
* need_des
*/
uint32_t ext_wakeup_status_clr:1;
/** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0;
* need_des
*/
uint32_t ext_wakeup_sel:8;
/** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
uint32_t ext_wakeup_lv:8;
/** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ext_wakeup_filter:1;
};
uint32_t val;
} lp_aon_ext_wakeup_cntl_reg_t;
/** Type of usb register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** usb_reset_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t usb_reset_disable:1;
};
uint32_t val;
} lp_aon_usb_reg_t;
/** Type of lpbus register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:16;
/** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0;
* This field controls fast memory WPULSE parameter.
*/
uint32_t fast_mem_wpulse:3;
/** fast_mem_wa : R/W; bitpos: [21:19]; default: 4;
* This field controls fast memory WA parameter.
*/
uint32_t fast_mem_wa:3;
/** fast_mem_ra : R/W; bitpos: [23:22]; default: 0;
* This field controls fast memory RA parameter.
*/
uint32_t fast_mem_ra:2;
uint32_t reserved_24:4;
/** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_fsm_idle:1;
/** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_sel_status:1;
/** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t fast_mem_mux_sel_update:1;
/** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_sel:1;
};
uint32_t val;
} lp_aon_lpbus_reg_t;
/** Type of sdio_active register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
uint32_t sdio_act_dnum:10;
};
uint32_t val;
} lp_aon_sdio_active_reg_t;
/** Type of lpcore register
* need_des
*/
typedef union {
struct {
/** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t lpcore_etm_wakeup_flag_clr:1;
/** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t lpcore_etm_wakeup_flag:1;
uint32_t reserved_2:29;
/** lpcore_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lpcore_disable:1;
};
uint32_t val;
} lp_aon_lpcore_reg_t;
/** Type of sar_cct register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
uint32_t sar2_pwdet_cct:3;
};
uint32_t val;
} lp_aon_sar_cct_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 35672704;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_aon_date_reg_t;
typedef struct lp_aon_dev_t {
volatile lp_aon_store_reg_t store[10];
volatile lp_aon_gpio_mux_reg_t gpio_mux;
volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
volatile lp_aon_sys_cfg_reg_t sys_cfg;
volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg;
volatile lp_aon_io_mux_reg_t io_mux;
volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
volatile lp_aon_usb_reg_t usb;
volatile lp_aon_lpbus_reg_t lpbus;
volatile lp_aon_sdio_active_reg_t sdio_active;
volatile lp_aon_lpcore_reg_t lpcore;
volatile lp_aon_sar_cct_reg_t sar_cct;
uint32_t reserved_058[233];
volatile lp_aon_date_reg_t date;
} lp_aon_dev_t;
extern lp_aon_dev_t LP_AON;
#ifndef __cplusplus
_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/lp_apm0_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM0_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
#define LP_APM0_REGION_FILTER_EN 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_S 0
/** LP_APM0_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S)
#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_S 0
/** LP_APM0_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S)
#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_S 0
/** LP_APM0_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_X (BIT(0))
#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S)
#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_X_S 0
/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_W (BIT(1))
#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S)
#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_W_S 1
/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_R (BIT(2))
#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S)
#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_R_S 2
/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_X (BIT(4))
#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S)
#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_X_S 4
/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_W (BIT(5))
#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S)
#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_W_S 5
/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_R (BIT(6))
#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S)
#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_R_S 6
/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_X (BIT(8))
#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S)
#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_X_S 8
/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_W (BIT(9))
#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S)
#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_W_S 9
/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_R (BIT(10))
#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S)
#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_R_S 10
/** LP_APM0_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S)
#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_S 0
/** LP_APM0_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S)
#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_S 0
/** LP_APM0_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_X (BIT(0))
#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S)
#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_X_S 0
/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_W (BIT(1))
#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S)
#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_W_S 1
/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_R (BIT(2))
#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S)
#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_R_S 2
/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_X (BIT(4))
#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S)
#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_X_S 4
/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_W (BIT(5))
#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S)
#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_W_S 5
/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_R (BIT(6))
#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S)
#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_R_S 6
/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_X (BIT(8))
#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S)
#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_X_S 8
/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_W (BIT(9))
#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S)
#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_W_S 9
/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_R (BIT(10))
#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S)
#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_R_S 10
/** LP_APM0_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S)
#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_S 0
/** LP_APM0_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S)
#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_S 0
/** LP_APM0_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_X (BIT(0))
#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S)
#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_X_S 0
/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_W (BIT(1))
#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S)
#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_W_S 1
/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_R (BIT(2))
#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S)
#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_R_S 2
/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_X (BIT(4))
#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S)
#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_X_S 4
/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_W (BIT(5))
#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S)
#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_W_S 5
/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_R (BIT(6))
#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S)
#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_R_S 6
/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_X (BIT(8))
#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S)
#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_X_S 8
/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_W (BIT(9))
#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S)
#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_W_S 9
/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_R (BIT(10))
#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S)
#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_R_S 10
/** LP_APM0_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S)
#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_S 0
/** LP_APM0_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S)
#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_S 0
/** LP_APM0_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_X (BIT(0))
#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S)
#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_X_S 0
/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_W (BIT(1))
#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S)
#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_W_S 1
/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_R (BIT(2))
#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S)
#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_R_S 2
/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_X (BIT(4))
#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S)
#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_X_S 4
/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_W (BIT(5))
#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S)
#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_W_S 5
/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_R (BIT(6))
#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S)
#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_R_S 6
/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_X (BIT(8))
#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S)
#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_X_S 8
/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_W (BIT(9))
#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S)
#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_W_S 9
/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_R (BIT(10))
#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S)
#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_R_S 10
/** LP_APM0_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM0_M0_PMS_FUNC_EN (BIT(0))
#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S)
#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U
#define LP_APM0_M0_PMS_FUNC_EN_S 0
/** LP_APM0_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_S 0
/** LP_APM0_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0))
#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S)
#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM0_M0_REGION_STATUS_CLR_S 0
/** LP_APM0_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_S 0
/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S)
#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_S 16
/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S)
#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_S 18
/** LP_APM0_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S)
#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_S 0
/** LP_APM0_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
#define LP_APM0_M0_APM_INT_EN (BIT(0))
#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
#define LP_APM0_M0_APM_INT_EN_V 0x00000001U
#define LP_APM0_M0_APM_INT_EN_S 0
/** LP_APM0_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_APM0_CLK_EN (BIT(0))
#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)
#define LP_APM0_CLK_EN_V 0x00000001U
#define LP_APM0_CLK_EN_S 0
/** LP_APM0_DATE_REG register
* Version register
*/
#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
#define LP_APM0_DATE 0x0FFFFFFFU
#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S)
#define LP_APM0_DATE_V 0x0FFFFFFFU
#define LP_APM0_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm0_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of region0_addr_start register
* Region address register
*/
typedef union {
struct {
/** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
uint32_t region0_addr_start:32;
};
uint32_t val;
} lp_apm0_region0_addr_start_reg_t;
/** Type of region0_addr_end register
* Region address register
*/
typedef union {
struct {
/** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
uint32_t region0_addr_end:32;
};
uint32_t val;
} lp_apm0_region0_addr_end_reg_t;
/** Type of region1_addr_start register
* Region address register
*/
typedef union {
struct {
/** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
uint32_t region1_addr_start:32;
};
uint32_t val;
} lp_apm0_region1_addr_start_reg_t;
/** Type of region1_addr_end register
* Region address register
*/
typedef union {
struct {
/** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
uint32_t region1_addr_end:32;
};
uint32_t val;
} lp_apm0_region1_addr_end_reg_t;
/** Type of region2_addr_start register
* Region address register
*/
typedef union {
struct {
/** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
uint32_t region2_addr_start:32;
};
uint32_t val;
} lp_apm0_region2_addr_start_reg_t;
/** Type of region2_addr_end register
* Region address register
*/
typedef union {
struct {
/** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
uint32_t region2_addr_end:32;
};
uint32_t val;
} lp_apm0_region2_addr_end_reg_t;
/** Type of region3_addr_start register
* Region address register
*/
typedef union {
struct {
/** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
uint32_t region3_addr_start:32;
};
uint32_t val;
} lp_apm0_region3_addr_start_reg_t;
/** Type of region3_addr_end register
* Region address register
*/
typedef union {
struct {
/** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
uint32_t region3_addr_end:32;
};
uint32_t val;
} lp_apm0_region3_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of region0_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region0_r0_pms_x:1;
/** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region0_r0_pms_w:1;
/** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region0_r0_pms_r:1;
uint32_t reserved_3:1;
/** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region0_r1_pms_x:1;
/** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region0_r1_pms_w:1;
/** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region0_r1_pms_r:1;
uint32_t reserved_7:1;
/** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region0_r2_pms_x:1;
/** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region0_r2_pms_w:1;
/** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region0_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm0_region0_pms_attr_reg_t;
/** Type of region1_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region1_r0_pms_x:1;
/** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region1_r0_pms_w:1;
/** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region1_r0_pms_r:1;
uint32_t reserved_3:1;
/** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region1_r1_pms_x:1;
/** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region1_r1_pms_w:1;
/** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region1_r1_pms_r:1;
uint32_t reserved_7:1;
/** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region1_r2_pms_x:1;
/** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region1_r2_pms_w:1;
/** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region1_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm0_region1_pms_attr_reg_t;
/** Type of region2_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region2_r0_pms_x:1;
/** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region2_r0_pms_w:1;
/** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region2_r0_pms_r:1;
uint32_t reserved_3:1;
/** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region2_r1_pms_x:1;
/** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region2_r1_pms_w:1;
/** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region2_r1_pms_r:1;
uint32_t reserved_7:1;
/** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region2_r2_pms_x:1;
/** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region2_r2_pms_w:1;
/** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region2_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm0_region2_pms_attr_reg_t;
/** Type of region3_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region3_r0_pms_x:1;
/** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region3_r0_pms_w:1;
/** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region3_r0_pms_r:1;
uint32_t reserved_3:1;
/** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region3_r1_pms_x:1;
/** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region3_r1_pms_w:1;
/** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region3_r1_pms_r:1;
uint32_t reserved_7:1;
/** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region3_r2_pms_x:1;
/** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region3_r2_pms_w:1;
/** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region3_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm0_region3_pms_attr_reg_t;
/** Group: PMS function control register */
/** Type of func_ctrl register
* PMS function control register
*/
typedef union {
struct {
/** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_pms_func_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm0_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m0_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm0_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm0_m0_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
uint32_t m0_apm_int_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm0_date_reg_t;
typedef struct lp_apm0_dev_t {
volatile lp_apm0_region_filter_en_reg_t region_filter_en;
volatile lp_apm0_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm0_region0_addr_end_reg_t region0_addr_end;
volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr;
volatile lp_apm0_region1_addr_start_reg_t region1_addr_start;
volatile lp_apm0_region1_addr_end_reg_t region1_addr_end;
volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr;
volatile lp_apm0_region2_addr_start_reg_t region2_addr_start;
volatile lp_apm0_region2_addr_end_reg_t region2_addr_end;
volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr;
volatile lp_apm0_region3_addr_start_reg_t region3_addr_start;
volatile lp_apm0_region3_addr_end_reg_t region3_addr_end;
volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr;
uint32_t reserved_034[36];
volatile lp_apm0_func_ctrl_reg_t func_ctrl;
volatile lp_apm0_m0_status_reg_t m0_status;
volatile lp_apm0_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm0_int_en_reg_t int_en;
volatile lp_apm0_clock_gate_reg_t clock_gate;
uint32_t reserved_0e0[455];
volatile lp_apm0_date_reg_t date;
} lp_apm0_dev_t;
extern lp_apm0_dev_t LP_APM0;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
#define LP_APM_REGION_FILTER_EN 0x0000000FU
#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
#define LP_APM_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM_REGION_FILTER_EN_S 0
/** LP_APM_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S)
#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_S 0
/** LP_APM_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S)
#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_S 0
/** LP_APM_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_X (BIT(0))
#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S)
#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_X_S 0
/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_W (BIT(1))
#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S)
#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_W_S 1
/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_R (BIT(2))
#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S)
#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_R_S 2
/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_X (BIT(4))
#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S)
#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_X_S 4
/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_W (BIT(5))
#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S)
#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_W_S 5
/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_R (BIT(6))
#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S)
#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_R_S 6
/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_X (BIT(8))
#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S)
#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_X_S 8
/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_W (BIT(9))
#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S)
#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_W_S 9
/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_R (BIT(10))
#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S)
#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_R_S 10
/** LP_APM_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S)
#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_S 0
/** LP_APM_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S)
#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_S 0
/** LP_APM_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_X (BIT(0))
#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S)
#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_X_S 0
/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_W (BIT(1))
#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S)
#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_W_S 1
/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_R (BIT(2))
#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S)
#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_R_S 2
/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_X (BIT(4))
#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S)
#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_X_S 4
/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_W (BIT(5))
#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S)
#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_W_S 5
/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_R (BIT(6))
#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S)
#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_R_S 6
/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_X (BIT(8))
#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S)
#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_X_S 8
/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_W (BIT(9))
#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S)
#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_W_S 9
/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_R (BIT(10))
#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S)
#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_R_S 10
/** LP_APM_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c)
/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S)
#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_S 0
/** LP_APM_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20)
/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S)
#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_S 0
/** LP_APM_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24)
/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_X (BIT(0))
#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S)
#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_X_S 0
/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_W (BIT(1))
#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S)
#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_W_S 1
/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_R (BIT(2))
#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S)
#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_R_S 2
/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_X (BIT(4))
#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S)
#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_X_S 4
/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_W (BIT(5))
#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S)
#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_W_S 5
/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_R (BIT(6))
#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S)
#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_R_S 6
/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_X (BIT(8))
#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S)
#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_X_S 8
/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_W (BIT(9))
#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S)
#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_W_S 9
/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_R (BIT(10))
#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S)
#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_R_S 10
/** LP_APM_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28)
/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S)
#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_S 0
/** LP_APM_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c)
/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S)
#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_S 0
/** LP_APM_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30)
/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_X (BIT(0))
#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S)
#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_X_S 0
/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_W (BIT(1))
#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S)
#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_W_S 1
/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_R (BIT(2))
#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S)
#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_R_S 2
/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_X (BIT(4))
#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S)
#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_X_S 4
/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_W (BIT(5))
#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S)
#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_W_S 5
/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_R (BIT(6))
#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S)
#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_R_S 6
/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_X (BIT(8))
#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S)
#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_X_S 8
/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_W (BIT(9))
#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S)
#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_W_S 9
/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_R (BIT(10))
#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S)
#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_R_S 10
/** LP_APM_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM_M0_PMS_FUNC_EN (BIT(0))
#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S)
#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U
#define LP_APM_M0_PMS_FUNC_EN_S 0
/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
#define LP_APM_M1_PMS_FUNC_EN (BIT(1))
#define LP_APM_M1_PMS_FUNC_EN_M (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S)
#define LP_APM_M1_PMS_FUNC_EN_V 0x00000001U
#define LP_APM_M1_PMS_FUNC_EN_S 1
/** LP_APM_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_S 0
/** LP_APM_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM_M0_REGION_STATUS_CLR (BIT(0))
#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S)
#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM_M0_REGION_STATUS_CLR_S 0
/** LP_APM_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_S 0
/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S)
#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_S 16
/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S)
#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_S 18
/** LP_APM_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S)
#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_S 0
/** LP_APM_M1_STATUS_REG register
* M1 status register
*/
#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8)
/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S)
#define LP_APM_M1_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_S 0
/** LP_APM_M1_STATUS_CLR_REG register
* M1 status clear register
*/
#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc)
/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM_M1_REGION_STATUS_CLR (BIT(0))
#define LP_APM_M1_REGION_STATUS_CLR_M (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S)
#define LP_APM_M1_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM_M1_REGION_STATUS_CLR_S 0
/** LP_APM_M1_EXCEPTION_INFO0_REG register
* M1 exception_info0 register
*/
#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0)
/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S)
#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_S 0
/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM_M1_EXCEPTION_MODE 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S)
#define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_S 16
/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM_M1_EXCEPTION_ID 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S)
#define LP_APM_M1_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_S 18
/** LP_APM_M1_EXCEPTION_INFO1_REG register
* M1 exception_info1 register
*/
#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4)
/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S)
#define LP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_S 0
/** LP_APM_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
#define LP_APM_M0_APM_INT_EN (BIT(0))
#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
#define LP_APM_M0_APM_INT_EN_V 0x00000001U
#define LP_APM_M0_APM_INT_EN_S 0
/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
* APM M1 interrupt enable
*/
#define LP_APM_M1_APM_INT_EN (BIT(1))
#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S)
#define LP_APM_M1_APM_INT_EN_V 0x00000001U
#define LP_APM_M1_APM_INT_EN_S 1
/** LP_APM_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_APM_CLK_EN (BIT(0))
#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)
#define LP_APM_CLK_EN_V 0x00000001U
#define LP_APM_CLK_EN_S 0
/** LP_APM_DATE_REG register
* Version register
*/
#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc)
/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
#define LP_APM_DATE 0x0FFFFFFFU
#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S)
#define LP_APM_DATE_V 0x0FFFFFFFU
#define LP_APM_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of region0_addr_start register
* Region address register
*/
typedef union {
struct {
/** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
uint32_t region0_addr_start:32;
};
uint32_t val;
} lp_apm_region0_addr_start_reg_t;
/** Type of region0_addr_end register
* Region address register
*/
typedef union {
struct {
/** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
uint32_t region0_addr_end:32;
};
uint32_t val;
} lp_apm_region0_addr_end_reg_t;
/** Type of region1_addr_start register
* Region address register
*/
typedef union {
struct {
/** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
uint32_t region1_addr_start:32;
};
uint32_t val;
} lp_apm_region1_addr_start_reg_t;
/** Type of region1_addr_end register
* Region address register
*/
typedef union {
struct {
/** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
uint32_t region1_addr_end:32;
};
uint32_t val;
} lp_apm_region1_addr_end_reg_t;
/** Type of region2_addr_start register
* Region address register
*/
typedef union {
struct {
/** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
uint32_t region2_addr_start:32;
};
uint32_t val;
} lp_apm_region2_addr_start_reg_t;
/** Type of region2_addr_end register
* Region address register
*/
typedef union {
struct {
/** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
uint32_t region2_addr_end:32;
};
uint32_t val;
} lp_apm_region2_addr_end_reg_t;
/** Type of region3_addr_start register
* Region address register
*/
typedef union {
struct {
/** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
uint32_t region3_addr_start:32;
};
uint32_t val;
} lp_apm_region3_addr_start_reg_t;
/** Type of region3_addr_end register
* Region address register
*/
typedef union {
struct {
/** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
uint32_t region3_addr_end:32;
};
uint32_t val;
} lp_apm_region3_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of region0_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region0_r0_pms_x:1;
/** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region0_r0_pms_w:1;
/** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region0_r0_pms_r:1;
uint32_t reserved_3:1;
/** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region0_r1_pms_x:1;
/** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region0_r1_pms_w:1;
/** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region0_r1_pms_r:1;
uint32_t reserved_7:1;
/** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region0_r2_pms_x:1;
/** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region0_r2_pms_w:1;
/** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region0_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region0_pms_attr_reg_t;
/** Type of region1_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region1_r0_pms_x:1;
/** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region1_r0_pms_w:1;
/** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region1_r0_pms_r:1;
uint32_t reserved_3:1;
/** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region1_r1_pms_x:1;
/** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region1_r1_pms_w:1;
/** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region1_r1_pms_r:1;
uint32_t reserved_7:1;
/** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region1_r2_pms_x:1;
/** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region1_r2_pms_w:1;
/** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region1_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region1_pms_attr_reg_t;
/** Type of region2_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region2_r0_pms_x:1;
/** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region2_r0_pms_w:1;
/** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region2_r0_pms_r:1;
uint32_t reserved_3:1;
/** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region2_r1_pms_x:1;
/** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region2_r1_pms_w:1;
/** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region2_r1_pms_r:1;
uint32_t reserved_7:1;
/** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region2_r2_pms_x:1;
/** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region2_r2_pms_w:1;
/** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region2_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region2_pms_attr_reg_t;
/** Type of region3_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region3_r0_pms_x:1;
/** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region3_r0_pms_w:1;
/** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region3_r0_pms_r:1;
uint32_t reserved_3:1;
/** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region3_r1_pms_x:1;
/** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region3_r1_pms_w:1;
/** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region3_r1_pms_r:1;
uint32_t reserved_7:1;
/** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region3_r2_pms_x:1;
/** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region3_r2_pms_w:1;
/** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region3_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region3_pms_attr_reg_t;
/** Group: PMS function control register */
/** Type of func_ctrl register
* PMS function control register
*/
typedef union {
struct {
/** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_pms_func_en:1;
/** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_pms_func_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m0_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m1_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m1_exception_region:4;
uint32_t reserved_4:12;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} lp_apm_m1_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* APM M1 interrupt enable
*/
uint32_t m1_apm_int_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm_date_reg_t;
typedef struct lp_apm_dev_t {
volatile lp_apm_region_filter_en_reg_t region_filter_en;
volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm_region0_addr_end_reg_t region0_addr_end;
volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr;
volatile lp_apm_region1_addr_start_reg_t region1_addr_start;
volatile lp_apm_region1_addr_end_reg_t region1_addr_end;
volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr;
volatile lp_apm_region2_addr_start_reg_t region2_addr_start;
volatile lp_apm_region2_addr_end_reg_t region2_addr_end;
volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr;
volatile lp_apm_region3_addr_start_reg_t region3_addr_start;
volatile lp_apm_region3_addr_end_reg_t region3_addr_end;
volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr;
uint32_t reserved_034[36];
volatile lp_apm_func_ctrl_reg_t func_ctrl;
volatile lp_apm_m0_status_reg_t m0_status;
volatile lp_apm_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm_m1_status_reg_t m1_status;
volatile lp_apm_m1_status_clr_reg_t m1_status_clr;
volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile lp_apm_int_en_reg_t int_en;
volatile lp_apm_clock_gate_reg_t clock_gate;
uint32_t reserved_0f0[3];
volatile lp_apm_date_reg_t date;
} lp_apm_dev_t;
extern lp_apm_dev_t LP_APM;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/lp_clkrst_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_CLKRST_LP_CLK_CONF_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
* need_des
*/
#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_S 0
/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [2]; default: 1;
* need_des
*/
#define LP_CLKRST_FAST_CLK_SEL (BIT(2))
#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
#define LP_CLKRST_FAST_CLK_SEL_V 0x00000001U
#define LP_CLKRST_FAST_CLK_SEL_S 2
/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_S 3
/** LP_CLKRST_LP_CLK_PO_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
* need_des
*/
#define LP_CLKRST_AON_SLOW_OEN (BIT(0))
#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_AON_SLOW_OEN_S 0
/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
* need_des
*/
#define LP_CLKRST_AON_FAST_OEN (BIT(1))
#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U
#define LP_CLKRST_AON_FAST_OEN_S 1
/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
* need_des
*/
#define LP_CLKRST_SOSC_OEN (BIT(2))
#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
#define LP_CLKRST_SOSC_OEN_V 0x00000001U
#define LP_CLKRST_SOSC_OEN_S 2
/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
* need_des
*/
#define LP_CLKRST_FOSC_OEN (BIT(3))
#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
#define LP_CLKRST_FOSC_OEN_V 0x00000001U
#define LP_CLKRST_FOSC_OEN_S 3
/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
* need_des
*/
#define LP_CLKRST_OSC32K_OEN (BIT(4))
#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
#define LP_CLKRST_OSC32K_OEN_V 0x00000001U
#define LP_CLKRST_OSC32K_OEN_S 4
/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
* need_des
*/
#define LP_CLKRST_XTAL32K_OEN (BIT(5))
#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U
#define LP_CLKRST_XTAL32K_OEN_S 5
/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
* need_des
*/
#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6))
#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U
#define LP_CLKRST_CORE_EFUSE_OEN_S 6
/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
* need_des
*/
#define LP_CLKRST_SLOW_OEN (BIT(7))
#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
#define LP_CLKRST_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_SLOW_OEN_S 7
/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
* need_des
*/
#define LP_CLKRST_FAST_OEN (BIT(8))
#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
#define LP_CLKRST_FAST_OEN_V 0x00000001U
#define LP_CLKRST_FAST_OEN_S 8
/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
* need_des
*/
#define LP_CLKRST_RNG_OEN (BIT(9))
#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
#define LP_CLKRST_RNG_OEN_V 0x00000001U
#define LP_CLKRST_RNG_OEN_S 9
/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
* need_des
*/
#define LP_CLKRST_LPBUS_OEN (BIT(10))
#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
#define LP_CLKRST_LPBUS_OEN_V 0x00000001U
#define LP_CLKRST_LPBUS_OEN_S 10
/** LP_CLKRST_LP_CLK_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_FAST_ORI_GATE (BIT(31))
#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U
#define LP_CLKRST_FAST_ORI_GATE_S 31
/** LP_CLKRST_LP_RST_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28))
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28
/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29))
#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U
#define LP_CLKRST_LP_TIMER_RESET_EN_S 29
/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_WDT_RESET_EN (BIT(30))
#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U
#define LP_CLKRST_WDT_RESET_EN_S 30
/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31))
#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U
#define LP_CLKRST_ANA_PERI_RESET_EN_S 31
/** LP_CLKRST_RESET_CAUSE_REG register
* need_des
*/
#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
* need_des
*/
#define LP_CLKRST_RESET_CAUSE 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_S 0
/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5))
#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_S 5
/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29))
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29
/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30))
#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30
/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31))
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31
/** LP_CLKRST_CPU_RESET_REG register
* need_des
*/
#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
* need_des
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22
/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25))
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25
/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
* need_des
*/
#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_S 26
/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CPU_STALL_EN (BIT(31))
#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U
#define LP_CLKRST_CPU_STALL_EN_S 31
/** LP_CLKRST_FOSC_CNTL_REG register
* need_des
*/
#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
#define LP_CLKRST_FOSC_DFREQ 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_S 22
/** LP_CLKRST_RC32K_CNTL_REG register
* need_des
*/
#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
#define LP_CLKRST_RC32K_DFREQ 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_S 22
/** LP_CLKRST_CLK_TO_HP_REG register
* need_des
*/
#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28))
#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_XTAL32K_S 28
/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_SOSC (BIT(29))
#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_SOSC_S 29
/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_OSC32K (BIT(30))
#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_OSC32K_S 30
/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_FOSC (BIT(31))
#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_FOSC_S 31
/** LP_CLKRST_LPMEM_FORCE_REG register
* need_des
*/
#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31))
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31
/** LP_CLKRST_LPPERI_REG register
* need_des
*/
#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28)
/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30))
#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S)
#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_I2C_CLK_SEL_S 30
/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31))
#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S)
#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_UART_CLK_SEL_S 31
/** LP_CLKRST_XTAL32K_REG register
* need_des
*/
#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
* need_des
*/
#define LP_CLKRST_DRES_XTAL32K 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_S 22
/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
* need_des
*/
#define LP_CLKRST_DGM_XTAL32K 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_S 25
/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_CLKRST_DBUF_XTAL32K (BIT(28))
#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U
#define LP_CLKRST_DBUF_XTAL32K_S 28
/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
* need_des
*/
#define LP_CLKRST_DAC_XTAL32K 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_S 29
/** LP_CLKRST_DATE_REG register
* need_des
*/
#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 35676304;
* need_des
*/
#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_S 0
/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CLK_EN (BIT(31))
#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
#define LP_CLKRST_CLK_EN_V 0x00000001U
#define LP_CLKRST_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/lp_clkrst_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_clk_conf register
* need_des
*/
typedef union {
struct {
/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
* need_des
*/
uint32_t slow_clk_sel:2;
/** fast_clk_sel : R/W; bitpos: [2]; default: 1;
* need_des
*/
uint32_t fast_clk_sel:1;
/** lp_peri_div_num : R/W; bitpos: [10:3]; default: 0;
* need_des
*/
uint32_t lp_peri_div_num:8;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_clkrst_lp_clk_conf_reg_t;
/** Type of lp_clk_po_en register
* need_des
*/
typedef union {
struct {
/** aon_slow_oen : R/W; bitpos: [0]; default: 1;
* need_des
*/
uint32_t aon_slow_oen:1;
/** aon_fast_oen : R/W; bitpos: [1]; default: 1;
* need_des
*/
uint32_t aon_fast_oen:1;
/** sosc_oen : R/W; bitpos: [2]; default: 1;
* need_des
*/
uint32_t sosc_oen:1;
/** fosc_oen : R/W; bitpos: [3]; default: 1;
* need_des
*/
uint32_t fosc_oen:1;
/** osc32k_oen : R/W; bitpos: [4]; default: 1;
* need_des
*/
uint32_t osc32k_oen:1;
/** xtal32k_oen : R/W; bitpos: [5]; default: 1;
* need_des
*/
uint32_t xtal32k_oen:1;
/** core_efuse_oen : R/W; bitpos: [6]; default: 1;
* need_des
*/
uint32_t core_efuse_oen:1;
/** slow_oen : R/W; bitpos: [7]; default: 1;
* need_des
*/
uint32_t slow_oen:1;
/** fast_oen : R/W; bitpos: [8]; default: 1;
* need_des
*/
uint32_t fast_oen:1;
/** rng_oen : R/W; bitpos: [9]; default: 1;
* need_des
*/
uint32_t rng_oen:1;
/** lpbus_oen : R/W; bitpos: [10]; default: 1;
* need_des
*/
uint32_t lpbus_oen:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_clkrst_lp_clk_po_en_reg_t;
/** Type of lp_clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** fast_ori_gate : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t fast_ori_gate:1;
};
uint32_t val;
} lp_clkrst_lp_clk_en_reg_t;
/** Type of lp_rst_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t aon_efuse_core_reset_en:1;
/** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_timer_reset_en:1;
/** wdt_reset_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t wdt_reset_en:1;
/** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_peri_reset_en:1;
};
uint32_t val;
} lp_clkrst_lp_rst_en_reg_t;
/** Type of reset_cause register
* need_des
*/
typedef union {
struct {
/** reset_cause : RO; bitpos: [4:0]; default: 0;
* need_des
*/
uint32_t reset_cause:5;
/** core0_reset_flag : RO; bitpos: [5]; default: 1;
* need_des
*/
uint32_t core0_reset_flag:1;
uint32_t reserved_6:23;
/** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t core0_reset_cause_clr:1;
/** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t core0_reset_flag_set:1;
/** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t core0_reset_flag_clr:1;
};
uint32_t val;
} lp_clkrst_reset_cause_reg_t;
/** Type of cpu_reset register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
* need_des
*/
uint32_t rtc_wdt_cpu_reset_length:3;
/** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t rtc_wdt_cpu_reset_en:1;
/** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
* need_des
*/
uint32_t cpu_stall_wait:5;
/** cpu_stall_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t cpu_stall_en:1;
};
uint32_t val;
} lp_clkrst_cpu_reset_reg_t;
/** Type of fosc_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
uint32_t fosc_dfreq:10;
};
uint32_t val;
} lp_clkrst_fosc_cntl_reg_t;
/** Type of rc32k_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
uint32_t rc32k_dfreq:10;
};
uint32_t val;
} lp_clkrst_rc32k_cntl_reg_t;
/** Type of clk_to_hp register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
* need_des
*/
uint32_t icg_hp_xtal32k:1;
/** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t icg_hp_sosc:1;
/** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t icg_hp_osc32k:1;
/** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t icg_hp_fosc:1;
};
uint32_t val;
} lp_clkrst_clk_to_hp_reg_t;
/** Type of lpmem_force register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lpmem_clk_force_on:1;
};
uint32_t val;
} lp_clkrst_lpmem_force_reg_t;
/** Type of lpperi register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_i2c_clk_sel:1;
/** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_uart_clk_sel:1;
};
uint32_t val;
} lp_clkrst_lpperi_reg_t;
/** Type of xtal32k register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
* need_des
*/
uint32_t dres_xtal32k:3;
/** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
* need_des
*/
uint32_t dgm_xtal32k:3;
/** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t dbuf_xtal32k:1;
/** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
* need_des
*/
uint32_t dac_xtal32k:3;
};
uint32_t val;
} lp_clkrst_xtal32k_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** clkrst_date : R/W; bitpos: [30:0]; default: 35676304;
* need_des
*/
uint32_t clkrst_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_clkrst_date_reg_t;
typedef struct lp_clkrst_dev_t {
volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
volatile lp_clkrst_reset_cause_reg_t reset_cause;
volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
volatile lp_clkrst_lpperi_reg_t lpperi;
volatile lp_clkrst_xtal32k_reg_t xtal32k;
uint32_t reserved_030[243];
volatile lp_clkrst_date_reg_t date;
} lp_clkrst_dev_t;
extern lp_clkrst_dev_t LP_CLKRST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_I2C_ANA_MST_I2C0_CTRL_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0)
/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S)
#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CTRL_S 0
/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25))
#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S)
#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U
#define LP_I2C_ANA_MST_I2C0_BUSY_S 25
/** LP_I2C_ANA_MST_I2C0_CONF_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4)
/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S)
#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CONF_S 0
/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7;
* reserved
*/
#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S)
#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_STATUS_S 24
/** LP_I2C_ANA_MST_I2C0_DATA_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8)
/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S)
#define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_RDATA_S 0
/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S)
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8
/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1;
* need des
*/
#define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11))
#define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S)
#define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U
#define LP_I2C_ANA_MST_I2C_MST_SEL_S 11
/** LP_I2C_ANA_MST_ANA_CONF1_REG register
* need_des
*/
#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc)
/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU
#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S)
#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU
#define LP_I2C_ANA_MST_ANA_CONF1_S 0
/** LP_I2C_ANA_MST_NOUSE_REG register
* need_des
*/
#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10)
/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S)
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0
/** LP_I2C_ANA_MST_DEVICE_EN_REG register
* need_des
*/
#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14)
/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S)
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0
/** LP_I2C_ANA_MST_DATE_REG register
* need_des
*/
#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc)
/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU
#define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S)
#define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU
#define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0
/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28))
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S)
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of i2c0_ctrl register
* need_des
*/
typedef union {
struct {
/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
* need_des
*/
uint32_t i2c0_ctrl:25;
/** i2c0_busy : RO; bitpos: [25]; default: 0;
* need_des
*/
uint32_t i2c0_busy:1;
uint32_t reserved_26:6;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_ctrl_reg_t;
/** Type of i2c0_conf register
* need_des
*/
typedef union {
struct {
/** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
uint32_t i2c0_conf:24;
/** i2c0_status : RO; bitpos: [31:24]; default: 7;
* reserved
*/
uint32_t i2c0_status:8;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_conf_reg_t;
/** Type of i2c0_data register
* need_des
*/
typedef union {
struct {
/** i2c0_rdata : RO; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t i2c0_rdata:8;
/** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1;
* need_des
*/
uint32_t i2c0_clk_sel:3;
/** i2c_mst_sel : R/W; bitpos: [11]; default: 1;
* need des
*/
uint32_t i2c_mst_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_data_reg_t;
/** Type of ana_conf1 register
* need_des
*/
typedef union {
struct {
/** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
uint32_t ana_conf1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} lp_i2c_ana_mst_ana_conf1_reg_t;
/** Type of nouse register
* need_des
*/
typedef union {
struct {
/** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t i2c_mst_nouse:32;
};
uint32_t val;
} lp_i2c_ana_mst_nouse_reg_t;
/** Type of device_en register
* need_des
*/
typedef union {
struct {
/** i2c_device_en : R/W; bitpos: [11:0]; default: 0;
* need_des
*/
uint32_t i2c_device_en:12;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2c_ana_mst_device_en_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873;
* need_des
*/
uint32_t i2c_mat_date:28;
/** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t i2c_mat_clk_en:1;
uint32_t reserved_29:3;
};
uint32_t val;
} lp_i2c_ana_mst_date_reg_t;
typedef struct lp_i2c_ana_mst_dev_t {
volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data;
volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1;
volatile lp_i2c_ana_mst_nouse_reg_t nouse;
volatile lp_i2c_ana_mst_device_en_reg_t device_en;
uint32_t reserved_018[249];
volatile lp_i2c_ana_mst_date_reg_t date;
} lp_i2c_ana_mst_dev_t;
extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of out_data register
* need des
*/
typedef union {
struct {
/** out_data : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t out_data:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_reg_t;
/** Type of out_data_w1ts register
* need des
*/
typedef union {
struct {
/** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t out_data_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_w1ts_reg_t;
/** Type of out_data_w1tc register
* need des
*/
typedef union {
struct {
/** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t out_data_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_w1tc_reg_t;
/** Type of out_enable register
* need des
*/
typedef union {
struct {
/** enable : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t enable:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_reg_t;
/** Type of out_enable_w1ts register
* need des
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t enable_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_w1ts_reg_t;
/** Type of out_enable_w1tc register
* need des
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t enable_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_w1tc_reg_t;
/** Type of status register
* need des
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t status_interrupt:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_reg_t;
/** Type of status_w1ts register
* need des
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t status_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_w1ts_reg_t;
/** Type of status_w1tc register
* need des
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t status_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_w1tc_reg_t;
/** Type of in register
* need des
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [7:0]; default: 0;
* need des
*/
uint32_t in_data_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_in_reg_t;
/** Type of pin register
* need des
*/
typedef union {
struct {
/** sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t sync_bypass:2;
/** pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t pad_driver:1;
/** edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t int_type:3;
/** wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t wakeup_enable:1;
/** filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin_reg_t;
/** Type of gpio register
* need des
*/
typedef union {
struct {
/** mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t mcu_oe:1;
/** slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t slp_sel:1;
/** mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t mcu_wpd:1;
/** mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t mcu_wpu:1;
/** mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t mcu_ie:1;
/** mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t mcu_drv:2;
/** fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t fun_wpd:1;
/** fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t fun_wpu:1;
/** fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t fun_ie:1;
/** fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t fun_drv:2;
/** mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio_reg_t;
/** Type of status_interrupt register
* need des
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
* need des
*/
uint32_t status_interrupt_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_interrupt_reg_t;
/** Type of debug_sel0 register
* need des
*/
typedef union {
struct {
/** debug_sel0 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t debug_sel0:7;
/** debug_sel1 : R/W; bitpos: [13:7]; default: 0;
* need des
*/
uint32_t debug_sel1:7;
/** debug_sel2 : R/W; bitpos: [20:14]; default: 0;
* need des
*/
uint32_t debug_sel2:7;
/** debug_sel3 : R/W; bitpos: [27:21]; default: 0;
* need des
*/
uint32_t debug_sel3:7;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_io_debug_sel0_reg_t;
/** Type of debug_sel1 register
* need des
*/
typedef union {
struct {
/** debug_sel4 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t debug_sel4:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_io_debug_sel1_reg_t;
/** Type of lpi2c register
* need des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1;
* need des
*/
uint32_t lp_i2c_sda_ie:1;
/** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1;
* need des
*/
uint32_t lp_i2c_scl_ie:1;
};
uint32_t val;
} lp_io_lpi2c_reg_t;
/** Type of date register
* need des
*/
typedef union {
struct {
/** lp_io_date : R/W; bitpos: [30:0]; default: 35660032;
* need des
*/
uint32_t lp_io_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_io_date_reg_t;
typedef struct lp_io_dev_t {
volatile lp_io_out_data_reg_t out_data;
volatile lp_io_out_data_w1ts_reg_t out_data_w1ts;
volatile lp_io_out_data_w1tc_reg_t out_data_w1tc;
volatile lp_io_out_enable_reg_t out_enable;
volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts;
volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc;
volatile lp_io_status_reg_t status;
volatile lp_io_status_w1ts_reg_t status_w1ts;
volatile lp_io_status_w1tc_reg_t status_w1tc;
volatile lp_io_in_reg_t in;
volatile lp_io_pin_reg_t pin[8];
volatile lp_io_gpio_reg_t gpio[8];
volatile lp_io_status_interrupt_reg_t status_interrupt;
volatile lp_io_debug_sel0_reg_t debug_sel0;
volatile lp_io_debug_sel1_reg_t debug_sel1;
volatile lp_io_lpi2c_reg_t lpi2c;
uint32_t reserved_078[225];
volatile lp_io_date_reg_t date;
} lp_io_dev_t;
extern lp_io_dev_t LP_IO;
#ifndef __cplusplus
_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TEE_M0_MODE_CTRL_REG register
* Tee mode control register
*/
#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define LP_TEE_M0_MODE 0x00000003U
#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
#define LP_TEE_M0_MODE_V 0x00000003U
#define LP_TEE_M0_MODE_S 0
/** LP_TEE_CLOCK_GATE_REG register
* Clock gating register
*/
#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4)
/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_TEE_CLK_EN (BIT(0))
#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
#define LP_TEE_CLK_EN_V 0x00000001U
#define LP_TEE_CLK_EN_S 0
/** LP_TEE_FORCE_ACC_HP_REG register
* need_des
*/
#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0))
#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U
#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0
/** LP_TEE_DATE_REG register
* Version register
*/
#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672688;
* reg_tee_date
*/
#define LP_TEE_DATE_REG 0x0FFFFFFFU
#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S)
#define LP_TEE_DATE_REG_V 0x0FFFFFFFU
#define LP_TEE_DATE_REG_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 3;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m0_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_tee_m0_mode_ctrl_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_clock_gate_reg_t;
/** Group: configure_register */
/** Type of force_acc_hp register
* need_des
*/
typedef union {
struct {
/** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t force_acc_hpmem_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_force_acc_hp_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date_reg : R/W; bitpos: [27:0]; default: 35672688;
* reg_tee_date
*/
uint32_t date_reg:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_tee_date_reg_t;
typedef struct lp_tee_dev_t {
volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
volatile lp_tee_clock_gate_reg_t clock_gate;
uint32_t reserved_008[34];
volatile lp_tee_force_acc_hp_reg_t force_acc_hp;
uint32_t reserved_094[26];
volatile lp_tee_date_reg_t date;
} lp_tee_dev_t;
extern lp_tee_dev_t LP_TEE;
#ifndef __cplusplus
_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TIMER_TAR0_LOW_REG register
* need_des
*/
#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0
/** LP_TIMER_TAR0_HIGH_REG register
* need_des
*/
#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31
/** LP_TIMER_TAR1_LOW_REG register
* need_des
*/
#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8)
/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0
/** LP_TIMER_TAR1_HIGH_REG register
* need_des
*/
#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31
/** LP_TIMER_UPDATE_REG register
* need_des
*/
#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28))
#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_UPDATE_S 28
/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29
/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30
/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31
/** LP_TIMER_MAIN_BUF0_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0
/** LP_TIMER_MAIN_BUF0_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
/** LP_TIMER_MAIN_BUF1_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0
/** LP_TIMER_MAIN_BUF1_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
/** LP_TIMER_MAIN_OVERFLOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31))
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S)
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31
/** LP_TIMER_INT_RAW_REG register
* need_des
*/
#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_RAW (BIT(30))
#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U
#define LP_TIMER_OVERFLOW_RAW_S 30
/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31
/** LP_TIMER_INT_ST_REG register
* need_des
*/
#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ST (BIT(30))
#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
#define LP_TIMER_OVERFLOW_ST_V 0x00000001U
#define LP_TIMER_OVERFLOW_ST_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31
/** LP_TIMER_INT_ENA_REG register
* need_des
*/
#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30)
/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ENA (BIT(30))
#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U
#define LP_TIMER_OVERFLOW_ENA_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31
/** LP_TIMER_INT_CLR_REG register
* need_des
*/
#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34)
/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_CLR (BIT(30))
#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U
#define LP_TIMER_OVERFLOW_CLR_S 30
/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31
/** LP_TIMER_LP_INT_RAW_REG register
* need_des
*/
#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31
/** LP_TIMER_LP_INT_ST_REG register
* need_des
*/
#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31
/** LP_TIMER_LP_INT_ENA_REG register
* need_des
*/
#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31
/** LP_TIMER_LP_INT_CLR_REG register
* need_des
*/
#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31
/** LP_TIMER_DATE_REG register
* need_des
*/
#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc)
/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
#define LP_TIMER_DATE 0x7FFFFFFFU
#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
#define LP_TIMER_DATE_V 0x7FFFFFFFU
#define LP_TIMER_DATE_S 0
/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_CLK_EN (BIT(31))
#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S)
#define LP_TIMER_CLK_EN_V 0x00000001U
#define LP_TIMER_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of tar0_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low0:32;
};
uint32_t val;
} lp_timer_tar0_low_reg_t;
/** Type of tar0_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high0:16;
uint32_t reserved_16:15;
/** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en0:1;
};
uint32_t val;
} lp_timer_tar0_high_reg_t;
/** Type of tar1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low1:32;
};
uint32_t val;
} lp_timer_tar1_low_reg_t;
/** Type of tar1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high1:16;
uint32_t reserved_16:15;
/** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en1:1;
};
uint32_t val;
} lp_timer_tar1_high_reg_t;
/** Type of update register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** main_timer_update : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t main_timer_update:1;
/** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t main_timer_xtal_off:1;
/** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_sys_stall:1;
/** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_sys_rst:1;
};
uint32_t val;
} lp_timer_update_reg_t;
/** Type of main_buf0_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_low:32;
};
uint32_t val;
} lp_timer_main_buf0_low_reg_t;
/** Type of main_buf0_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf0_high_reg_t;
/** Type of main_buf1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_low:32;
};
uint32_t val;
} lp_timer_main_buf1_low_reg_t;
/** Type of main_buf1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf1_high_reg_t;
/** Type of main_overflow register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_alarm_load:1;
};
uint32_t val;
} lp_timer_main_overflow_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_raw:1;
/** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_raw:1;
};
uint32_t val;
} lp_timer_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_st:1;
/** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_st:1;
};
uint32_t val;
} lp_timer_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_ena:1;
/** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_ena:1;
};
uint32_t val;
} lp_timer_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_clr:1;
/** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_clr:1;
};
uint32_t val;
} lp_timer_int_clr_reg_t;
/** Type of lp_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_raw:1;
/** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_raw:1;
};
uint32_t val;
} lp_timer_lp_int_raw_reg_t;
/** Type of lp_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_st:1;
/** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_st:1;
};
uint32_t val;
} lp_timer_lp_int_st_reg_t;
/** Type of lp_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_ena:1;
/** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_ena:1;
};
uint32_t val;
} lp_timer_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_clr:1;
/** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_clr:1;
};
uint32_t val;
} lp_timer_lp_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_timer_date_reg_t;
typedef struct lp_timer_dev_t {
volatile lp_timer_tar0_low_reg_t tar0_low;
volatile lp_timer_tar0_high_reg_t tar0_high;
volatile lp_timer_tar1_low_reg_t tar1_low;
volatile lp_timer_tar1_high_reg_t tar1_high;
volatile lp_timer_update_reg_t update;
volatile lp_timer_main_buf0_low_reg_t main_buf0_low;
volatile lp_timer_main_buf0_high_reg_t main_buf0_high;
volatile lp_timer_main_buf1_low_reg_t main_buf1_low;
volatile lp_timer_main_buf1_high_reg_t main_buf1_high;
volatile lp_timer_main_overflow_reg_t main_overflow;
volatile lp_timer_int_raw_reg_t int_raw;
volatile lp_timer_int_st_reg_t int_st;
volatile lp_timer_int_ena_reg_t int_ena;
volatile lp_timer_int_clr_reg_t int_clr;
volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
volatile lp_timer_lp_int_st_reg_t lp_int_st;
volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_048[237];
volatile lp_timer_date_reg_t date;
} lp_timer_dev_t;
extern lp_timer_dev_t LP_TIMER;
#ifndef __cplusplus
_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// TODO: IDF-5730 (better to move to wdt_types.h?)
/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
#define RTC_WDT_RESET_LENGTH_100_NS 0
#define RTC_WDT_RESET_LENGTH_200_NS 1
#define RTC_WDT_RESET_LENGTH_300_NS 2
#define RTC_WDT_RESET_LENGTH_400_NS 3
#define RTC_WDT_RESET_LENGTH_500_NS 4
#define RTC_WDT_RESET_LENGTH_800_NS 5
#define RTC_WDT_RESET_LENGTH_1600_NS 6
#define RTC_WDT_RESET_LENGTH_3200_NS 7
/** LP_WDT_CONFIG0_REG register
* need_des
*/
#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
/** LP_WDT_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20;
* need_des
*/
#define LP_WDT_WDT_CHIP_RESET_WIDTH 0x000000FFU
#define LP_WDT_WDT_CHIP_RESET_WIDTH_M (LP_WDT_WDT_CHIP_RESET_WIDTH_V << LP_WDT_WDT_CHIP_RESET_WIDTH_S)
#define LP_WDT_WDT_CHIP_RESET_WIDTH_V 0x000000FFU
#define LP_WDT_WDT_CHIP_RESET_WIDTH_S 0
/** LP_WDT_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0;
* need_des
*/
#define LP_WDT_WDT_CHIP_RESET_EN (BIT(8))
#define LP_WDT_WDT_CHIP_RESET_EN_M (LP_WDT_WDT_CHIP_RESET_EN_V << LP_WDT_WDT_CHIP_RESET_EN_S)
#define LP_WDT_WDT_CHIP_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_CHIP_RESET_EN_S 8
/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
* need_des
*/
#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9))
#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
#define LP_WDT_WDT_PAUSE_IN_SLP_S 9
/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
* need_des
*/
#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10))
#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_APPCPU_RESET_EN_S 10
/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
* need_des
*/
#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11))
#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_PROCPU_RESET_EN_S 11
/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
* need_des
*/
#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12
/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
* need_des
*/
#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
* need_des
*/
#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
* need_des
*/
#define LP_WDT_WDT_STG3 0x00000007U
#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
#define LP_WDT_WDT_STG3_V 0x00000007U
#define LP_WDT_WDT_STG3_S 19
/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
* need_des
*/
#define LP_WDT_WDT_STG2 0x00000007U
#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
#define LP_WDT_WDT_STG2_V 0x00000007U
#define LP_WDT_WDT_STG2_S 22
/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
* need_des
*/
#define LP_WDT_WDT_STG1 0x00000007U
#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
#define LP_WDT_WDT_STG1_V 0x00000007U
#define LP_WDT_WDT_STG1_S 25
/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
#define LP_WDT_WDT_STG0 0x00000007U
#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
#define LP_WDT_WDT_STG0_V 0x00000007U
#define LP_WDT_WDT_STG0_S 28
/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_WDT_EN (BIT(31))
#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
#define LP_WDT_WDT_EN_V 0x00000001U
#define LP_WDT_WDT_EN_S 31
/** LP_WDT_CONFIG1_REG register
* need_des
*/
#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
* need_des
*/
#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG0_HOLD_S 0
/** LP_WDT_CONFIG2_REG register
* need_des
*/
#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
* need_des
*/
#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG1_HOLD_S 0
/** LP_WDT_CONFIG3_REG register
* need_des
*/
#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG2_HOLD_S 0
/** LP_WDT_CONFIG4_REG register
* need_des
*/
#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG3_HOLD_S 0
/** LP_WDT_FEED_REG register
* need_des
*/
#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_RTC_WDT_FEED (BIT(31))
#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S)
#define LP_WDT_RTC_WDT_FEED_V 0x00000001U
#define LP_WDT_RTC_WDT_FEED_S 31
/** LP_WDT_WPROTECT_REG register
* need_des
*/
#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_WDT_WDT_WKEY 0xFFFFFFFFU
#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU
#define LP_WDT_WDT_WKEY_S 0
/** LP_WDT_SWD_CONFIG_REG register
* need_des
*/
#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
* need_des
*/
#define LP_WDT_SWD_RESET_FLAG (BIT(0))
#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U
#define LP_WDT_SWD_RESET_FLAG_S 0
/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
* need_des
*/
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18))
#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
#define LP_WDT_SWD_AUTO_FEED_EN_S 18
/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
* need_des
*/
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19))
#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
#define LP_WDT_SWD_RST_FLAG_CLR_S 19
/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
* need_des
*/
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_S 20
/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SWD_DISABLE (BIT(30))
#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
#define LP_WDT_SWD_DISABLE_V 0x00000001U
#define LP_WDT_SWD_DISABLE_S 30
/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_SWD_FEED (BIT(31))
#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
#define LP_WDT_SWD_FEED_V 0x00000001U
#define LP_WDT_SWD_FEED_S 31
/** LP_WDT_SWD_WPROTECT_REG register
* need_des
*/
#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_WDT_SWD_WKEY 0xFFFFFFFFU
#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU
#define LP_WDT_SWD_WKEY_S 0
/** LP_WDT_INT_RAW_REG register
* need_des
*/
#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30))
#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_RAW_S 30
/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_LP_WDT_INT_RAW (BIT(31))
#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U
#define LP_WDT_LP_WDT_INT_RAW_S 31
/** LP_WDT_INT_ST_REG register
* need_des
*/
#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SUPER_WDT_INT_ST (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ST_S 30
/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_LP_WDT_INT_ST (BIT(31))
#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U
#define LP_WDT_LP_WDT_INT_ST_S 31
/** LP_WDT_INT_ENA_REG register
* need_des
*/
#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ENA_S 30
/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_LP_WDT_INT_ENA (BIT(31))
#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U
#define LP_WDT_LP_WDT_INT_ENA_S 31
/** LP_WDT_INT_CLR_REG register
* need_des
*/
#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30))
#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_CLR_S 30
/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_LP_WDT_INT_CLR (BIT(31))
#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U
#define LP_WDT_LP_WDT_INT_CLR_S 31
/** LP_WDT_DATE_REG register
* need_des
*/
#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
* need_des
*/
#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU
#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
#define LP_WDT_LP_WDT_DATE_S 0
/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_CLK_EN (BIT(31))
#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
#define LP_WDT_CLK_EN_V 0x00000001U
#define LP_WDT_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
* need_des
*/
typedef union {
struct {
/** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
* need_des
*/
uint32_t wdt_chip_reset_width:8;
/** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0;
* need_des
*/
uint32_t wdt_chip_reset_en:1;
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
* need_des
*/
uint32_t wdt_pause_in_slp:1;
/** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
* need_des
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
* need_des
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
* need_des
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
* need_des
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
* need_des
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
* need_des
*/
uint32_t wdt_stg3:3;
/** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
* need_des
*/
uint32_t wdt_stg2:3;
/** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
* need_des
*/
uint32_t wdt_stg1:3;
/** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
uint32_t wdt_stg0:3;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t wdt_en:1;
};
uint32_t val;
} lp_wdt_config0_reg_t;
/** Type of config1 register
* need_des
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
* need_des
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} lp_wdt_config1_reg_t;
/** Type of config2 register
* need_des
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
* need_des
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} lp_wdt_config2_reg_t;
/** Type of config3 register
* need_des
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} lp_wdt_config3_reg_t;
/** Type of config4 register
* need_des
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} lp_wdt_config4_reg_t;
/** Type of feed register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** rtc_wdt_feed : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t rtc_wdt_feed:1;
};
uint32_t val;
} lp_wdt_feed_reg_t;
/** Type of wprotect register
* need_des
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} lp_wdt_wprotect_reg_t;
/** Type of swd_config register
* need_des
*/
typedef union {
struct {
/** swd_reset_flag : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t swd_reset_flag:1;
uint32_t reserved_1:17;
/** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
* need_des
*/
uint32_t swd_auto_feed_en:1;
/** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
* need_des
*/
uint32_t swd_rst_flag_clr:1;
/** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
* need_des
*/
uint32_t swd_signal_width:10;
/** swd_disable : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t swd_disable:1;
/** swd_feed : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t swd_feed:1;
};
uint32_t val;
} lp_wdt_swd_config_reg_t;
/** Type of swd_wprotect register
* need_des
*/
typedef union {
struct {
/** swd_wkey : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t swd_wkey:32;
};
uint32_t val;
} lp_wdt_swd_wprotect_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_raw:1;
/** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_raw:1;
};
uint32_t val;
} lp_wdt_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_st:1;
/** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_st:1;
};
uint32_t val;
} lp_wdt_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_ena:1;
/** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_ena:1;
};
uint32_t val;
} lp_wdt_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_clr:1;
/** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_clr:1;
};
uint32_t val;
} lp_wdt_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
* need_des
*/
uint32_t lp_wdt_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_wdt_date_reg_t;
typedef struct lp_wdt_dev_t {
volatile lp_wdt_config0_reg_t config0;
volatile lp_wdt_config1_reg_t config1;
volatile lp_wdt_config2_reg_t config2;
volatile lp_wdt_config3_reg_t config3;
volatile lp_wdt_config4_reg_t config4;
volatile lp_wdt_feed_reg_t feed;
volatile lp_wdt_wprotect_reg_t wprotect;
volatile lp_wdt_swd_config_reg_t swd_config;
volatile lp_wdt_swd_wprotect_reg_t swd_wprotect;
volatile lp_wdt_int_raw_reg_t int_raw;
volatile lp_wdt_int_st_reg_t int_st;
volatile lp_wdt_int_ena_reg_t int_ena;
volatile lp_wdt_int_clr_reg_t int_clr;
uint32_t reserved_034[242];
volatile lp_wdt_date_reg_t date;
} lp_wdt_dev_t;
extern lp_wdt_dev_t LP_WDT;
#ifndef __cplusplus
_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/lpperi_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LPPERI_CLK_EN_REG register
* need_des
*/
#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
* need_des
*/
#define LPPERI_RNG_CK_EN (BIT(24))
#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S)
#define LPPERI_RNG_CK_EN_V 0x00000001U
#define LPPERI_RNG_CK_EN_S 24
/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1;
* need_des
*/
#define LPPERI_OTP_DBG_CK_EN (BIT(25))
#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S)
#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U
#define LPPERI_OTP_DBG_CK_EN_S 25
/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1;
* need_des
*/
#define LPPERI_LP_UART_CK_EN (BIT(26))
#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S)
#define LPPERI_LP_UART_CK_EN_V 0x00000001U
#define LPPERI_LP_UART_CK_EN_S 26
/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1;
* need_des
*/
#define LPPERI_LP_IO_CK_EN (BIT(27))
#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S)
#define LPPERI_LP_IO_CK_EN_V 0x00000001U
#define LPPERI_LP_IO_CK_EN_S 27
/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1;
* need_des
*/
#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S)
#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_CK_EN_S 28
/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S)
#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_CK_EN_S 29
/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LPPERI_EFUSE_CK_EN (BIT(30))
#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S)
#define LPPERI_EFUSE_CK_EN_V 0x00000001U
#define LPPERI_EFUSE_CK_EN_S 30
/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_LP_CPU_CK_EN (BIT(31))
#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S)
#define LPPERI_LP_CPU_CK_EN_V 0x00000001U
#define LPPERI_LP_CPU_CK_EN_S 31
/** LPPERI_RESET_EN_REG register
* need_des
*/
#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0;
* need_des
*/
#define LPPERI_BUS_RESET_EN (BIT(23))
#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S)
#define LPPERI_BUS_RESET_EN_V 0x00000001U
#define LPPERI_BUS_RESET_EN_S 23
/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define LPPERI_OTP_DBG_RESET_EN (BIT(25))
#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S)
#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U
#define LPPERI_OTP_DBG_RESET_EN_S 25
/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define LPPERI_LP_UART_RESET_EN (BIT(26))
#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S)
#define LPPERI_LP_UART_RESET_EN_V 0x00000001U
#define LPPERI_LP_UART_RESET_EN_S 26
/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LPPERI_LP_IO_RESET_EN (BIT(27))
#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S)
#define LPPERI_LP_IO_RESET_EN_V 0x00000001U
#define LPPERI_LP_IO_RESET_EN_S 27
/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S)
#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_RESET_EN_S 28
/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S)
#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_RESET_EN_S 29
/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_EFUSE_RESET_EN (BIT(30))
#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S)
#define LPPERI_EFUSE_RESET_EN_V 0x00000001U
#define LPPERI_EFUSE_RESET_EN_S 30
/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_LP_CPU_RESET_EN (BIT(31))
#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S)
#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U
#define LPPERI_LP_CPU_RESET_EN_S 31
/** LPPERI_RNG_DATA_REG register
* need_des
*/
#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8)
/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LPPERI_RND_DATA 0xFFFFFFFFU
#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S)
#define LPPERI_RND_DATA_V 0xFFFFFFFFU
#define LPPERI_RND_DATA_S 0
/** LPPERI_CPU_REG register
* need_des
*/
#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31))
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S)
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31
/** LPPERI_BUS_TIMEOUT_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10)
/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S)
#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14
/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30))
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S)
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30
/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31))
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S)
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31
/** LPPERI_BUS_TIMEOUT_ADDR_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14)
/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S)
#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0
/** LPPERI_BUS_TIMEOUT_UID_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18)
/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S)
#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_S 0
/** LPPERI_MEM_CTRL_REG register
* need_des
*/
#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c)
/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0))
#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S)
#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0
/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_FLAG (BIT(1))
#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S)
#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_S 1
/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_EN (BIT(29))
#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S)
#define LPPERI_UART_WAKEUP_EN_V 0x00000001U
#define LPPERI_UART_WAKEUP_EN_S 29
/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_UART_MEM_FORCE_PD (BIT(30))
#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S)
#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PD_S 30
/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_UART_MEM_FORCE_PU (BIT(31))
#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S)
#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PU_S 31
/** LPPERI_INTERRUPT_SOURCE_REG register
* need_des
*/
#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S)
#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_S 0
/** LPPERI_DATE_REG register
* need_des
*/
#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 35676464;
* need_des
*/
#define LPPERI_LPPERI_DATE 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_S 0
/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_CLK_EN (BIT(31))
#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
#define LPPERI_CLK_EN_V 0x00000001U
#define LPPERI_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
* need_des
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1;
* need_des
*/
uint32_t otp_dbg_ck_en:1;
/** lp_uart_ck_en : R/W; bitpos: [26]; default: 1;
* need_des
*/
uint32_t lp_uart_ck_en:1;
/** lp_io_ck_en : R/W; bitpos: [27]; default: 1;
* need_des
*/
uint32_t lp_io_ck_en:1;
/** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1;
* need_des
*/
uint32_t lp_ext_i2c_ck_en:1;
/** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t lp_ana_i2c_ck_en:1;
/** efuse_ck_en : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t efuse_ck_en:1;
/** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cpu_ck_en:1;
};
uint32_t val;
} lpperi_clk_en_reg_t;
/** Type of reset_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** bus_reset_en : WT; bitpos: [23]; default: 0;
* need_des
*/
uint32_t bus_reset_en:1;
uint32_t reserved_24:1;
/** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t otp_dbg_reset_en:1;
/** lp_uart_reset_en : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t lp_uart_reset_en:1;
/** lp_io_reset_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t lp_io_reset_en:1;
/** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t lp_ext_i2c_reset_en:1;
/** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_ana_i2c_reset_en:1;
/** efuse_reset_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t efuse_reset_en:1;
/** lp_cpu_reset_en : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cpu_reset_en:1;
};
uint32_t val;
} lpperi_reset_en_reg_t;
/** Type of rng_data register
* need_des
*/
typedef union {
struct {
/** rnd_data : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t rnd_data:32;
};
uint32_t val;
} lpperi_rng_data_reg_t;
/** Type of cpu register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lpcore_dbgm_unavaliable:1;
};
uint32_t val;
} lpperi_cpu_reg_t;
/** Type of bus_timeout register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535;
* need_des
*/
uint32_t lp_peri_timeout_thres:16;
/** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_int_clear:1;
/** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lp_peri_timeout_protect_en:1;
};
uint32_t val;
} lpperi_bus_timeout_reg_t;
/** Type of bus_timeout_addr register
* need_des
*/
typedef union {
struct {
/** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_addr:32;
};
uint32_t val;
} lpperi_bus_timeout_addr_reg_t;
/** Type of bus_timeout_uid register
* need_des
*/
typedef union {
struct {
/** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lpperi_bus_timeout_uid_reg_t;
/** Type of mem_ctrl register
* need_des
*/
typedef union {
struct {
/** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t uart_wakeup_flag_clr:1;
/** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t uart_wakeup_flag:1;
uint32_t reserved_2:27;
/** uart_wakeup_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t uart_wakeup_en:1;
/** uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t uart_mem_force_pd:1;
/** uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t uart_mem_force_pu:1;
};
uint32_t val;
} lpperi_mem_ctrl_reg_t;
/** Type of interrupt_source register
* need_des
*/
typedef union {
struct {
/** lp_interrupt_source : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
uint32_t lp_interrupt_source:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lpperi_interrupt_source_reg_t;
/** Group: Version register */
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lpperi_date : R/W; bitpos: [30:0]; default: 35676464;
* need_des
*/
uint32_t lpperi_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lpperi_date_reg_t;
typedef struct lpperi_dev_t {
volatile lpperi_clk_en_reg_t clk_en;
volatile lpperi_reset_en_reg_t reset_en;
volatile lpperi_rng_data_reg_t rng_data;
volatile lpperi_cpu_reg_t cpu;
volatile lpperi_bus_timeout_reg_t bus_timeout;
volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr;
volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid;
volatile lpperi_mem_ctrl_reg_t mem_ctrl;
volatile lpperi_interrupt_source_reg_t interrupt_source;
uint32_t reserved_024[246];
volatile lpperi_date_reg_t date;
} lpperi_dev_t;
extern lpperi_dev_t LPPERI;
#ifndef __cplusplus
_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
* log config regsiter
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
* enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.
*/
#define MEM_MONITOR_LOG_ENA 0x00000007U
#define MEM_MONITOR_LOG_ENA_M (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
#define MEM_MONITOR_LOG_ENA_V 0x00000007U
#define MEM_MONITOR_LOG_ENA_S 0
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
* This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
* HALFWORD monitor, 4'b1000: BYTE monitor.
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
#define MEM_MONITOR_LOG_MODE_S 3
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(7))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
* check data regsiter
*/
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
/** MEM_MONITOR_LOG_DATA_MASK_REG register
* check data mask register
*/
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_S 0
/** MEM_MONITOR_LOG_MIN_REG register
* log boundary regsiter
*/
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_S 0
/** MEM_MONITOR_LOG_MAX_REG register
* log boundary regsiter
*/
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_S 0
/** MEM_MONITOR_LOG_MEM_START_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_S 0
/** MEM_MONITOR_LOG_MEM_END_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_S 0
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
* current writing address.
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
* writing address update
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
* full flag status register
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
/** MEM_MONITOR_CLOCK_GATE_REG register
* clock gate force on register
*/
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
#define MEM_MONITOR_CLK_EN_V 0x00000001U
#define MEM_MONITOR_CLK_EN_S 0
/** MEM_MONITOR_DATE_REG register
* version register
*/
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096;
* version register
*/
#define MEM_MONITOR_DATE 0x0FFFFFFFU
#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
#define MEM_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
* log config regsiter
*/
typedef union {
struct {
/** log_ena : R/W; bitpos: [2:0]; default: 0;
* enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.
*/
uint32_t log_ena:3;
/** log_mode : R/W; bitpos: [6:3]; default: 0;
* This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
* HALFWORD monitor, 4'b1000: BYTE monitor.
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [7]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
uint32_t log_mem_loop_enable:1;
uint32_t reserved_8:24;
};
uint32_t val;
} mem_monitor_log_setting_reg_t;
/** Type of log_check_data register
* check data regsiter
*/
typedef union {
struct {
/** log_check_data : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
uint32_t log_check_data:32;
};
uint32_t val;
} mem_monitor_log_check_data_reg_t;
/** Type of log_data_mask register
* check data mask register
*/
typedef union {
struct {
/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
uint32_t log_data_mask:4;
uint32_t reserved_4:28;
};
uint32_t val;
} mem_monitor_log_data_mask_reg_t;
/** Type of log_min register
* log boundary regsiter
*/
typedef union {
struct {
/** log_min : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
uint32_t log_min:32;
};
uint32_t val;
} mem_monitor_log_min_reg_t;
/** Type of log_max register
* log boundary regsiter
*/
typedef union {
struct {
/** log_max : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
uint32_t log_max:32;
};
uint32_t val;
} mem_monitor_log_max_reg_t;
/** Type of log_mem_start register
* log message store range register
*/
typedef union {
struct {
/** log_mem_start : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
uint32_t log_mem_start:32;
};
uint32_t val;
} mem_monitor_log_mem_start_reg_t;
/** Type of log_mem_end register
* log message store range register
*/
typedef union {
struct {
/** log_mem_end : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
uint32_t log_mem_end:32;
};
uint32_t val;
} mem_monitor_log_mem_end_reg_t;
/** Type of log_mem_current_addr register
* current writing address.
*/
typedef union {
struct {
/** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
uint32_t log_mem_current_addr:32;
};
uint32_t val;
} mem_monitor_log_mem_current_addr_reg_t;
/** Type of log_mem_addr_update register
* writing address update
*/
typedef union {
struct {
/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
uint32_t log_mem_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_log_mem_addr_update_reg_t;
/** Type of log_mem_full_flag register
* full flag status register
*/
typedef union {
struct {
/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
uint32_t log_mem_full_flag:1;
/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
uint32_t clr_log_mem_full_flag:1;
uint32_t reserved_2:30;
};
uint32_t val;
} mem_monitor_log_mem_full_flag_reg_t;
/** Group: clk register */
/** Type of clock_gate register
* clock gate force on register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_clock_gate_reg_t;
/** Group: version register */
/** Type of date register
* version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35660096;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} mem_monitor_date_reg_t;
typedef struct mem_monitor_dev_t {
volatile mem_monitor_log_setting_reg_t log_setting;
volatile mem_monitor_log_check_data_reg_t log_check_data;
volatile mem_monitor_log_data_mask_reg_t log_data_mask;
volatile mem_monitor_log_min_reg_t log_min;
volatile mem_monitor_log_max_reg_t log_max;
volatile mem_monitor_log_mem_start_reg_t log_mem_start;
volatile mem_monitor_log_mem_end_reg_t log_mem_end;
volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
volatile mem_monitor_clock_gate_reg_t clock_gate;
uint32_t reserved_02c[244];
volatile mem_monitor_date_reg_t date;
} mem_monitor_dev_t;
extern mem_monitor_dev_t MEM_MONITOR;
#ifndef __cplusplus
_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PARL_IO_RX_CFG0_REG register
* Parallel RX module configuration register0.
*/
#define PARL_IO_RX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x0)
/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [0]; default: 0;
* Write 0 to select eof generated manchnism by configured data byte length. Write 1
* to select eof generated manchnism by external enable signal.
*/
#define PARL_IO_RX_EOF_GEN_SEL (BIT(0))
#define PARL_IO_RX_EOF_GEN_SEL_M (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
#define PARL_IO_RX_EOF_GEN_SEL_V 0x00000001U
#define PARL_IO_RX_EOF_GEN_SEL_S 0
/** PARL_IO_RX_START : R/W; bitpos: [1]; default: 0;
* Write 1 to start rx global data sampling.
*/
#define PARL_IO_RX_START (BIT(1))
#define PARL_IO_RX_START_M (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
#define PARL_IO_RX_START_V 0x00000001U
#define PARL_IO_RX_START_S 1
/** PARL_IO_RX_DATA_BYTELEN : R/W; bitpos: [17:2]; default: 0;
* Configures rx receieved data byte length.
*/
#define PARL_IO_RX_DATA_BYTELEN 0x0000FFFFU
#define PARL_IO_RX_DATA_BYTELEN_M (PARL_IO_RX_DATA_BYTELEN_V << PARL_IO_RX_DATA_BYTELEN_S)
#define PARL_IO_RX_DATA_BYTELEN_V 0x0000FFFFU
#define PARL_IO_RX_DATA_BYTELEN_S 2
/** PARL_IO_RX_SW_EN : R/W; bitpos: [18]; default: 0;
* Write 1 to enable software data sampling.
*/
#define PARL_IO_RX_SW_EN (BIT(18))
#define PARL_IO_RX_SW_EN_M (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
#define PARL_IO_RX_SW_EN_V 0x00000001U
#define PARL_IO_RX_SW_EN_S 18
/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [22:19]; default: 0;
* Pulse submode selection.
* 0000: positive pulse start(data bit included) && positive pulse end(data bit
* included)
* 0001: positive pulse start(data bit included) && positive pulse end (data bit
* excluded)
* 0010: positive pulse start(data bit excluded) && positive pulse end (data bit
* included)
* 0011: positive pulse start(data bit excluded) && positive pulse end (data bit
* excluded)
* 0100: positive pulse start(data bit included) && length end
* 0101: positive pulse start(data bit excluded) && length end
* 0110: negative pulse start(data bit included) && negative pulse end(data bit
* included)
* 0111: negative pulse start(data bit included) && negative pulse end (data bit
* excluded)
* 1000: negative pulse start(data bit excluded) && negative pulse end (data bit
* included)
* 1001: negative pulse start(data bit excluded) && negative pulse end (data bit
* excluded)
* 1010: negative pulse start(data bit included) && length end
* 1011: negative pulse start(data bit excluded) && length end
*/
#define PARL_IO_RX_PULSE_SUBMODE_SEL 0x0000000FU
#define PARL_IO_RX_PULSE_SUBMODE_SEL_M (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
#define PARL_IO_RX_PULSE_SUBMODE_SEL_V 0x0000000FU
#define PARL_IO_RX_PULSE_SUBMODE_SEL_S 19
/** PARL_IO_RX_LEVEL_SUBMODE_SEL : R/W; bitpos: [23]; default: 0;
* Write 0 to sample data at high level of external enable signal. Write 1 to sample
* data at low level of external enable signal.
*/
#define PARL_IO_RX_LEVEL_SUBMODE_SEL (BIT(23))
#define PARL_IO_RX_LEVEL_SUBMODE_SEL_M (PARL_IO_RX_LEVEL_SUBMODE_SEL_V << PARL_IO_RX_LEVEL_SUBMODE_SEL_S)
#define PARL_IO_RX_LEVEL_SUBMODE_SEL_V 0x00000001U
#define PARL_IO_RX_LEVEL_SUBMODE_SEL_S 23
/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [25:24]; default: 0;
* Rx data sampling mode selection.
* 000: external level enable mode
* 001: external pulse enable mode
* 010: internal software enable mode
*/
#define PARL_IO_RX_SMP_MODE_SEL 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_M (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
#define PARL_IO_RX_SMP_MODE_SEL_V 0x00000003U
#define PARL_IO_RX_SMP_MODE_SEL_S 24
/** PARL_IO_RX_CLK_EDGE_SEL : R/W; bitpos: [26]; default: 0;
* Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable
* sampling data on the falling edge of rx clock.
*/
#define PARL_IO_RX_CLK_EDGE_SEL (BIT(26))
#define PARL_IO_RX_CLK_EDGE_SEL_M (PARL_IO_RX_CLK_EDGE_SEL_V << PARL_IO_RX_CLK_EDGE_SEL_S)
#define PARL_IO_RX_CLK_EDGE_SEL_V 0x00000001U
#define PARL_IO_RX_CLK_EDGE_SEL_S 26
/** PARL_IO_RX_BIT_PACK_ORDER : R/W; bitpos: [27]; default: 0;
* Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0
* to pack bits into 1byte from LSB when data bus width is 4/2/1 bits.
*/
#define PARL_IO_RX_BIT_PACK_ORDER (BIT(27))
#define PARL_IO_RX_BIT_PACK_ORDER_M (PARL_IO_RX_BIT_PACK_ORDER_V << PARL_IO_RX_BIT_PACK_ORDER_S)
#define PARL_IO_RX_BIT_PACK_ORDER_V 0x00000001U
#define PARL_IO_RX_BIT_PACK_ORDER_S 27
/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [30:28]; default: 0;
* Rx data bus width selection.
* 100: bus width is 1 bit
* 011: bus width is 2 bits
* 010: bus width is 4 bits
* 001: bus width is 8 bits
* 000: bus width is 16 bits
*/
#define PARL_IO_RX_BUS_WID_SEL 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_M (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
#define PARL_IO_RX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_RX_BUS_WID_SEL_S 28
/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
* Write 1 to enable soft reset of async fifo in rx module.
*/
#define PARL_IO_RX_FIFO_SRST (BIT(31))
#define PARL_IO_RX_FIFO_SRST_M (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
#define PARL_IO_RX_FIFO_SRST_V 0x00000001U
#define PARL_IO_RX_FIFO_SRST_S 31
/** PARL_IO_RX_CFG1_REG register
* Parallel RX module configuration register1.
*/
#define PARL_IO_RX_CFG1_REG (DR_REG_PARL_IO_BASE + 0x4)
/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [2]; default: 0;
* Write 1 to update rx register configuration signals.
*/
#define PARL_IO_RX_REG_UPDATE (BIT(2))
#define PARL_IO_RX_REG_UPDATE_M (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
#define PARL_IO_RX_REG_UPDATE_V 0x00000001U
#define PARL_IO_RX_REG_UPDATE_S 2
/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [3]; default: 1;
* Write 1 to enable timeout count to generate error eof.
*/
#define PARL_IO_RX_TIMEOUT_EN (BIT(3))
#define PARL_IO_RX_TIMEOUT_EN_M (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
#define PARL_IO_RX_TIMEOUT_EN_V 0x00000001U
#define PARL_IO_RX_TIMEOUT_EN_S 3
/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [15:12]; default: 15;
* Configures rx external enable signal selection from 16 data lines.
*/
#define PARL_IO_RX_EXT_EN_SEL 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_M (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
#define PARL_IO_RX_EXT_EN_SEL_V 0x0000000FU
#define PARL_IO_RX_EXT_EN_SEL_S 12
/** PARL_IO_RX_TIMEOUT_THRESHOLD : R/W; bitpos: [31:16]; default: 4095;
* Configures rx threshold of timeout counter.
*/
#define PARL_IO_RX_TIMEOUT_THRESHOLD 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRESHOLD_M (PARL_IO_RX_TIMEOUT_THRESHOLD_V << PARL_IO_RX_TIMEOUT_THRESHOLD_S)
#define PARL_IO_RX_TIMEOUT_THRESHOLD_V 0x0000FFFFU
#define PARL_IO_RX_TIMEOUT_THRESHOLD_S 16
/** PARL_IO_TX_CFG0_REG register
* Parallel TX module configuration register0.
*/
#define PARL_IO_TX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x8)
/** PARL_IO_TX_BYTELEN : R/W; bitpos: [17:2]; default: 0;
* Configures tx sending data byte length.
*/
#define PARL_IO_TX_BYTELEN 0x0000FFFFU
#define PARL_IO_TX_BYTELEN_M (PARL_IO_TX_BYTELEN_V << PARL_IO_TX_BYTELEN_S)
#define PARL_IO_TX_BYTELEN_V 0x0000FFFFU
#define PARL_IO_TX_BYTELEN_S 2
/** PARL_IO_TX_GATING_EN : R/W; bitpos: [18]; default: 0;
* Write 1 to enable output tx clock gating.
*/
#define PARL_IO_TX_GATING_EN (BIT(18))
#define PARL_IO_TX_GATING_EN_M (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
#define PARL_IO_TX_GATING_EN_V 0x00000001U
#define PARL_IO_TX_GATING_EN_S 18
/** PARL_IO_TX_START : R/W; bitpos: [19]; default: 0;
* Write 1 to start tx global data output.
*/
#define PARL_IO_TX_START (BIT(19))
#define PARL_IO_TX_START_M (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
#define PARL_IO_TX_START_V 0x00000001U
#define PARL_IO_TX_START_S 19
/** PARL_IO_TX_HW_VALID_EN : R/W; bitpos: [20]; default: 0;
* Write 1 to enable tx hardware data valid signal.
*/
#define PARL_IO_TX_HW_VALID_EN (BIT(20))
#define PARL_IO_TX_HW_VALID_EN_M (PARL_IO_TX_HW_VALID_EN_V << PARL_IO_TX_HW_VALID_EN_S)
#define PARL_IO_TX_HW_VALID_EN_V 0x00000001U
#define PARL_IO_TX_HW_VALID_EN_S 20
/** PARL_IO_TX_SMP_EDGE_SEL : R/W; bitpos: [25]; default: 0;
* Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable
* sampling data on the falling edge of tx clock.
*/
#define PARL_IO_TX_SMP_EDGE_SEL (BIT(25))
#define PARL_IO_TX_SMP_EDGE_SEL_M (PARL_IO_TX_SMP_EDGE_SEL_V << PARL_IO_TX_SMP_EDGE_SEL_S)
#define PARL_IO_TX_SMP_EDGE_SEL_V 0x00000001U
#define PARL_IO_TX_SMP_EDGE_SEL_S 25
/** PARL_IO_TX_BIT_UNPACK_ORDER : R/W; bitpos: [26]; default: 0;
* Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write
* 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits.
*/
#define PARL_IO_TX_BIT_UNPACK_ORDER (BIT(26))
#define PARL_IO_TX_BIT_UNPACK_ORDER_M (PARL_IO_TX_BIT_UNPACK_ORDER_V << PARL_IO_TX_BIT_UNPACK_ORDER_S)
#define PARL_IO_TX_BIT_UNPACK_ORDER_V 0x00000001U
#define PARL_IO_TX_BIT_UNPACK_ORDER_S 26
/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [29:27]; default: 0;
* Tx data bus width selection.
* 100: bus width is 1 bit
* 011: bus width is 2 bits
* 010: bus width is 4 bits
* 001: bus width is 8 bits
* 000: bus width is 16 bits
*/
#define PARL_IO_TX_BUS_WID_SEL 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_M (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
#define PARL_IO_TX_BUS_WID_SEL_V 0x00000007U
#define PARL_IO_TX_BUS_WID_SEL_S 27
/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
* Write 1 to enable soft reset of async fifo in tx module.
*/
#define PARL_IO_TX_FIFO_SRST (BIT(30))
#define PARL_IO_TX_FIFO_SRST_M (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
#define PARL_IO_TX_FIFO_SRST_V 0x00000001U
#define PARL_IO_TX_FIFO_SRST_S 30
/** PARL_IO_TX_CFG1_REG register
* Parallel TX module configuration register1.
*/
#define PARL_IO_TX_CFG1_REG (DR_REG_PARL_IO_BASE + 0xc)
/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [31:16]; default: 0;
* Configures data value on tx bus when IDLE state.
*/
#define PARL_IO_TX_IDLE_VALUE 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_M (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
#define PARL_IO_TX_IDLE_VALUE_V 0x0000FFFFU
#define PARL_IO_TX_IDLE_VALUE_S 16
/** PARL_IO_ST_REG register
* Parallel IO module status register0.
*/
#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x10)
/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready.
*/
#define PARL_IO_TX_READY (BIT(31))
#define PARL_IO_TX_READY_M (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
#define PARL_IO_TX_READY_V 0x00000001U
#define PARL_IO_TX_READY_S 31
/** PARL_IO_INT_ENA_REG register
* Parallel IO interrupt enable singal configuration register.
*/
#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x14)
/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INTR.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S 0
/** PARL_IO_RX_FIFO_WFULL_INT_ENA : R/W; bitpos: [1]; default: 0;
* Write 1 to enable RX_FIFO_WFULL_INTR.
*/
#define PARL_IO_RX_FIFO_WFULL_INT_ENA (BIT(1))
#define PARL_IO_RX_FIFO_WFULL_INT_ENA_M (PARL_IO_RX_FIFO_WFULL_INT_ENA_V << PARL_IO_RX_FIFO_WFULL_INT_ENA_S)
#define PARL_IO_RX_FIFO_WFULL_INT_ENA_V 0x00000001U
#define PARL_IO_RX_FIFO_WFULL_INT_ENA_S 1
/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
* Write 1 to enable TX_EOF_INTR.
*/
#define PARL_IO_TX_EOF_INT_ENA (BIT(2))
#define PARL_IO_TX_EOF_INT_ENA_M (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
#define PARL_IO_TX_EOF_INT_ENA_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ENA_S 2
/** PARL_IO_INT_RAW_REG register
* Parallel IO interrupt raw singal status register.
*/
#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x18)
/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INTR.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S 0
/** PARL_IO_RX_FIFO_WFULL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WFULL_INTR.
*/
#define PARL_IO_RX_FIFO_WFULL_INT_RAW (BIT(1))
#define PARL_IO_RX_FIFO_WFULL_INT_RAW_M (PARL_IO_RX_FIFO_WFULL_INT_RAW_V << PARL_IO_RX_FIFO_WFULL_INT_RAW_S)
#define PARL_IO_RX_FIFO_WFULL_INT_RAW_V 0x00000001U
#define PARL_IO_RX_FIFO_WFULL_INT_RAW_S 1
/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INTR.
*/
#define PARL_IO_TX_EOF_INT_RAW (BIT(2))
#define PARL_IO_TX_EOF_INT_RAW_M (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
#define PARL_IO_TX_EOF_INT_RAW_V 0x00000001U
#define PARL_IO_TX_EOF_INT_RAW_S 2
/** PARL_IO_INT_ST_REG register
* Parallel IO interrupt singal status register.
*/
#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x1c)
/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INTR.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_ST (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S 0
/** PARL_IO_RX_FIFO_WFULL_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WFULL_INTR.
*/
#define PARL_IO_RX_FIFO_WFULL_INT_ST (BIT(1))
#define PARL_IO_RX_FIFO_WFULL_INT_ST_M (PARL_IO_RX_FIFO_WFULL_INT_ST_V << PARL_IO_RX_FIFO_WFULL_INT_ST_S)
#define PARL_IO_RX_FIFO_WFULL_INT_ST_V 0x00000001U
#define PARL_IO_RX_FIFO_WFULL_INT_ST_S 1
/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INTR.
*/
#define PARL_IO_TX_EOF_INT_ST (BIT(2))
#define PARL_IO_TX_EOF_INT_ST_M (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
#define PARL_IO_TX_EOF_INT_ST_V 0x00000001U
#define PARL_IO_TX_EOF_INT_ST_S 2
/** PARL_IO_INT_CLR_REG register
* Parallel IO interrupt clear singal configuration register.
*/
#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x20)
/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INTR.
*/
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR (BIT(0))
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V 0x00000001U
#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S 0
/** PARL_IO_RX_FIFO_WFULL_INT_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear RX_FIFO_WFULL_INTR.
*/
#define PARL_IO_RX_FIFO_WFULL_INT_CLR (BIT(1))
#define PARL_IO_RX_FIFO_WFULL_INT_CLR_M (PARL_IO_RX_FIFO_WFULL_INT_CLR_V << PARL_IO_RX_FIFO_WFULL_INT_CLR_S)
#define PARL_IO_RX_FIFO_WFULL_INT_CLR_V 0x00000001U
#define PARL_IO_RX_FIFO_WFULL_INT_CLR_S 1
/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear TX_EOF_INTR.
*/
#define PARL_IO_TX_EOF_INT_CLR (BIT(2))
#define PARL_IO_TX_EOF_INT_CLR_M (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
#define PARL_IO_TX_EOF_INT_CLR_V 0x00000001U
#define PARL_IO_TX_EOF_INT_CLR_S 2
/** PARL_IO_CLK_REG register
* Parallel IO clk configuration register
*/
#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
/** PARL_IO_CLK_EN : R/W; bitpos: [0]; default: 0;
* Force clock on for this register file
*/
#define PARL_IO_CLK_EN (BIT(0))
#define PARL_IO_CLK_EN_M (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
#define PARL_IO_CLK_EN_V 0x00000001U
#define PARL_IO_CLK_EN_S 0
/** PARL_IO_VERSION_REG register
* Version register.
*/
#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35660352;
* Version of this register file
*/
#define PARL_IO_DATE 0x0FFFFFFFU
#define PARL_IO_DATE_M (PARL_IO_DATE_V << PARL_IO_DATE_S)
#define PARL_IO_DATE_V 0x0FFFFFFFU
#define PARL_IO_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: PARL_IO RX Configuration0 */
/** Type of rx_cfg0 register
* Parallel RX module configuration register0.
*/
typedef union {
struct {
/** rx_eof_gen_sel : R/W; bitpos: [0]; default: 0;
* Write 0 to select eof generated manchnism by configured data byte length. Write 1
* to select eof generated manchnism by external enable signal.
*/
uint32_t rx_eof_gen_sel:1;
/** rx_start : R/W; bitpos: [1]; default: 0;
* Write 1 to start rx global data sampling.
*/
uint32_t rx_start:1;
/** rx_data_bytelen : R/W; bitpos: [17:2]; default: 0;
* Configures rx receieved data byte length.
*/
uint32_t rx_data_bytelen:16;
/** rx_sw_en : R/W; bitpos: [18]; default: 0;
* Write 1 to enable software data sampling.
*/
uint32_t rx_sw_en:1;
/** rx_pulse_submode_sel : R/W; bitpos: [22:19]; default: 0;
* Pulse submode selection.
* 0000: positive pulse start(data bit included) && positive pulse end(data bit
* included)
* 0001: positive pulse start(data bit included) && positive pulse end (data bit
* excluded)
* 0010: positive pulse start(data bit excluded) && positive pulse end (data bit
* included)
* 0011: positive pulse start(data bit excluded) && positive pulse end (data bit
* excluded)
* 0100: positive pulse start(data bit included) && length end
* 0101: positive pulse start(data bit excluded) && length end
* 0110: negative pulse start(data bit included) && negative pulse end(data bit
* included)
* 0111: negative pulse start(data bit included) && negative pulse end (data bit
* excluded)
* 1000: negative pulse start(data bit excluded) && negative pulse end (data bit
* included)
* 1001: negative pulse start(data bit excluded) && negative pulse end (data bit
* excluded)
* 1010: negative pulse start(data bit included) && length end
* 1011: negative pulse start(data bit excluded) && length end
*/
uint32_t rx_pulse_submode_sel:4;
/** rx_level_submode_sel : R/W; bitpos: [23]; default: 0;
* Write 0 to sample data at high level of external enable signal. Write 1 to sample
* data at low level of external enable signal.
*/
uint32_t rx_level_submode_sel:1;
/** rx_smp_mode_sel : R/W; bitpos: [25:24]; default: 0;
* Rx data sampling mode selection.
* 000: external level enable mode
* 001: external pulse enable mode
* 010: internal software enable mode
*/
uint32_t rx_smp_mode_sel:2;
/** rx_clk_edge_sel : R/W; bitpos: [26]; default: 0;
* Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable
* sampling data on the falling edge of rx clock.
*/
uint32_t rx_clk_edge_sel:1;
/** rx_bit_pack_order : R/W; bitpos: [27]; default: 0;
* Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0
* to pack bits into 1byte from LSB when data bus width is 4/2/1 bits.
*/
uint32_t rx_bit_pack_order:1;
/** rx_bus_wid_sel : R/W; bitpos: [30:28]; default: 0;
* Rx data bus width selection.
* 100: bus width is 1 bit
* 011: bus width is 2 bits
* 010: bus width is 4 bits
* 001: bus width is 8 bits
* 000: bus width is 16 bits
*/
uint32_t rx_bus_wid_sel:3;
/** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
* Write 1 to enable soft reset of async fifo in rx module.
*/
uint32_t rx_fifo_srst:1;
};
uint32_t val;
} parl_io_rx_cfg0_reg_t;
/** Group: PARL_IO RX Configuration1 */
/** Type of rx_cfg1 register
* Parallel RX module configuration register1.
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** rx_reg_update : WT; bitpos: [2]; default: 0;
* Write 1 to update rx register configuration signals.
*/
uint32_t rx_reg_update:1;
/** rx_timeout_en : R/W; bitpos: [3]; default: 1;
* Write 1 to enable timeout count to generate error eof.
*/
uint32_t rx_timeout_en:1;
uint32_t reserved_4:8;
/** rx_ext_en_sel : R/W; bitpos: [15:12]; default: 15;
* Configures rx external enable signal selection from 16 data lines.
*/
uint32_t rx_ext_en_sel:4;
/** rx_timeout_threshold : R/W; bitpos: [31:16]; default: 4095;
* Configures rx threshold of timeout counter.
*/
uint32_t rx_timeout_threshold:16;
};
uint32_t val;
} parl_io_rx_cfg1_reg_t;
/** Group: PARL_IO TX Configuration0 */
/** Type of tx_cfg0 register
* Parallel TX module configuration register0.
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** tx_bytelen : R/W; bitpos: [17:2]; default: 0;
* Configures tx sending data byte length.
*/
uint32_t tx_bytelen:16;
/** tx_gating_en : R/W; bitpos: [18]; default: 0;
* Write 1 to enable output tx clock gating.
*/
uint32_t tx_gating_en:1;
/** tx_start : R/W; bitpos: [19]; default: 0;
* Write 1 to start tx global data output.
*/
uint32_t tx_start:1;
/** tx_hw_valid_en : R/W; bitpos: [20]; default: 0;
* Write 1 to enable tx hardware data valid signal.
*/
uint32_t tx_hw_valid_en:1;
uint32_t reserved_21:4;
/** tx_smp_edge_sel : R/W; bitpos: [25]; default: 0;
* Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable
* sampling data on the falling edge of tx clock.
*/
uint32_t tx_smp_edge_sel:1;
/** tx_bit_unpack_order : R/W; bitpos: [26]; default: 0;
* Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write
* 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits.
*/
uint32_t tx_bit_unpack_order:1;
/** tx_bus_wid_sel : R/W; bitpos: [29:27]; default: 0;
* Tx data bus width selection.
* 100: bus width is 1 bit
* 011: bus width is 2 bits
* 010: bus width is 4 bits
* 001: bus width is 8 bits
* 000: bus width is 16 bits
*/
uint32_t tx_bus_wid_sel:3;
/** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
* Write 1 to enable soft reset of async fifo in tx module.
*/
uint32_t tx_fifo_srst:1;
uint32_t reserved_31:1;
};
uint32_t val;
} parl_io_tx_cfg0_reg_t;
/** Group: PARL_IO TX Configuration1 */
/** Type of tx_cfg1 register
* Parallel TX module configuration register1.
*/
typedef union {
struct {
uint32_t reserved_0:16;
/** tx_idle_value : R/W; bitpos: [31:16]; default: 0;
* Configures data value on tx bus when IDLE state.
*/
uint32_t tx_idle_value:16;
};
uint32_t val;
} parl_io_tx_cfg1_reg_t;
/** Group: PARL_IO TX Status0 */
/** Type of st register
* Parallel IO module status register0.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_ready : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready.
*/
uint32_t tx_ready:1;
};
uint32_t val;
} parl_io_st_reg_t;
/** Group: PARL_IO Interrupt Configuration and Status */
/** Type of int_ena register
* Parallel IO interrupt enable singal configuration register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INTR.
*/
uint32_t tx_fifo_rempty_int_ena:1;
/** rx_fifo_wfull_int_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to enable RX_FIFO_WFULL_INTR.
*/
uint32_t rx_fifo_wfull_int_ena:1;
/** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable TX_EOF_INTR.
*/
uint32_t tx_eof_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_ena_reg_t;
/** Type of int_raw register
* Parallel IO interrupt raw singal status register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INTR.
*/
uint32_t tx_fifo_rempty_int_raw:1;
/** rx_fifo_wfull_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WFULL_INTR.
*/
uint32_t rx_fifo_wfull_int_raw:1;
/** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INTR.
*/
uint32_t tx_eof_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_raw_reg_t;
/** Type of int_st register
* Parallel IO interrupt singal status register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INTR.
*/
uint32_t tx_fifo_rempty_int_st:1;
/** rx_fifo_wfull_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WFULL_INTR.
*/
uint32_t rx_fifo_wfull_int_st:1;
/** tx_eof_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INTR.
*/
uint32_t tx_eof_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_st_reg_t;
/** Type of int_clr register
* Parallel IO interrupt clear singal configuration register.
*/
typedef union {
struct {
/** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INTR.
*/
uint32_t tx_fifo_rempty_int_clr:1;
/** rx_fifo_wfull_int_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear RX_FIFO_WFULL_INTR.
*/
uint32_t rx_fifo_wfull_int_clr:1;
/** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear TX_EOF_INTR.
*/
uint32_t tx_eof_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_clr_reg_t;
/** Group: PARL_IO Clock Gating Configuration */
/** Type of clk register
* Parallel IO clk configuration register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Force clock on for this register file
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} parl_io_clk_reg_t;
/** Group: PARL_IO Version Register */
/** Type of version register
* Version register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35660352;
* Version of this register file
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} parl_io_version_reg_t;
typedef struct parl_io_dev_t {
volatile parl_io_rx_cfg0_reg_t rx_cfg0;
volatile parl_io_rx_cfg1_reg_t rx_cfg1;
volatile parl_io_tx_cfg0_reg_t tx_cfg0;
volatile parl_io_tx_cfg1_reg_t tx_cfg1;
volatile parl_io_st_reg_t st;
volatile parl_io_int_ena_reg_t int_ena;
volatile parl_io_int_raw_reg_t int_raw;
volatile parl_io_int_st_reg_t int_st;
volatile parl_io_int_clr_reg_t int_clr;
uint32_t reserved_024[63];
volatile parl_io_clk_reg_t clk;
uint32_t reserved_124[182];
volatile parl_io_version_reg_t version;
} parl_io_dev_t;
extern parl_io_dev_t PARL_IO;
#ifndef __cplusplus
_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PAU_REGDMA_CONF_REG register
* Peri backup control register
*/
#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
#define PAU_FLOW_ERR 0x00000007U
#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
#define PAU_FLOW_ERR_V 0x00000007U
#define PAU_FLOW_ERR_S 0
/** PAU_START : WT; bitpos: [3]; default: 0;
* backup start signal
*/
#define PAU_START (BIT(3))
#define PAU_START_M (PAU_START_V << PAU_START_S)
#define PAU_START_V 0x00000001U
#define PAU_START_S 3
/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM (BIT(4))
#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S)
#define PAU_TO_MEM_V 0x00000001U
#define PAU_TO_MEM_S 4
/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0;
* Link select
*/
#define PAU_LINK_SEL 0x00000003U
#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
#define PAU_LINK_SEL_V 0x00000003U
#define PAU_LINK_SEL_S 5
/** PAU_START_MAC : WT; bitpos: [7]; default: 0;
* mac sw backup start signal
*/
#define PAU_START_MAC (BIT(7))
#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S)
#define PAU_START_MAC_V 0x00000001U
#define PAU_START_MAC_S 7
/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM_MAC (BIT(8))
#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
#define PAU_TO_MEM_MAC_V 0x00000001U
#define PAU_TO_MEM_MAC_S 8
/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0;
* mac hw/sw select
*/
#define PAU_SEL_MAC (BIT(9))
#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
#define PAU_SEL_MAC_V 0x00000001U
#define PAU_SEL_MAC_S 9
/** PAU_REGDMA_CLK_CONF_REG register
* Clock control register
*/
#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
* clock enable
*/
#define PAU_CLK_EN (BIT(0))
#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S)
#define PAU_CLK_EN_V 0x00000001U
#define PAU_CLK_EN_S 0
/** PAU_REGDMA_ETM_CTRL_REG register
* ETM start ctrl reg
*/
#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
#define PAU_ETM_START_0 (BIT(0))
#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
#define PAU_ETM_START_0_V 0x00000001U
#define PAU_ETM_START_0_S 0
/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
#define PAU_ETM_START_1 (BIT(1))
#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
#define PAU_ETM_START_1_V 0x00000001U
#define PAU_ETM_START_1_S 1
/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
#define PAU_ETM_START_2 (BIT(2))
#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
#define PAU_ETM_START_2_V 0x00000001U
#define PAU_ETM_START_2_S 2
/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
#define PAU_ETM_START_3 (BIT(3))
#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
#define PAU_ETM_START_3_V 0x00000001U
#define PAU_ETM_START_3_S 3
/** PAU_REGDMA_LINK_0_ADDR_REG register
* link_0_addr
*/
#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0;
* link_0_addr reg
*/
#define PAU_LINK_ADDR_0 0xFFFFFFFFU
#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S)
#define PAU_LINK_ADDR_0_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_0_S 0
/** PAU_REGDMA_LINK_1_ADDR_REG register
* Link_1_addr
*/
#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0;
* Link_1_addr reg
*/
#define PAU_LINK_ADDR_1 0xFFFFFFFFU
#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S)
#define PAU_LINK_ADDR_1_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_1_S 0
/** PAU_REGDMA_LINK_2_ADDR_REG register
* Link_2_addr
*/
#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0;
* Link_2_addr reg
*/
#define PAU_LINK_ADDR_2 0xFFFFFFFFU
#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S)
#define PAU_LINK_ADDR_2_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_2_S 0
/** PAU_REGDMA_LINK_3_ADDR_REG register
* Link_3_addr
*/
#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0;
* Link_3_addr reg
*/
#define PAU_LINK_ADDR_3 0xFFFFFFFFU
#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S)
#define PAU_LINK_ADDR_3_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_3_S 0
/** PAU_REGDMA_LINK_MAC_ADDR_REG register
* Link_mac_addr
*/
#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0;
* Link_mac_addr reg
*/
#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU
#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S)
#define PAU_LINK_ADDR_MAC_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_MAC_S 0
/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
* current link addr
*/
#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_S 0
/** PAU_REGDMA_BACKUP_ADDR_REG register
* Backup addr
*/
#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0;
* backup addr reg
*/
#define PAU_BACKUP_ADDR 0xFFFFFFFFU
#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S)
#define PAU_BACKUP_ADDR_V 0xFFFFFFFFU
#define PAU_BACKUP_ADDR_S 0
/** PAU_REGDMA_MEM_ADDR_REG register
* mem addr
*/
#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28)
/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
#define PAU_MEM_ADDR 0xFFFFFFFFU
#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
#define PAU_MEM_ADDR_V 0xFFFFFFFFU
#define PAU_MEM_ADDR_S 0
/** PAU_REGDMA_BKP_CONF_REG register
* backup config
*/
#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c)
/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32;
* Link read_interval
*/
#define PAU_READ_INTERVAL 0x0000007FU
#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S)
#define PAU_READ_INTERVAL_V 0x0000007FU
#define PAU_READ_INTERVAL_S 0
/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50;
* link wait timeout threshold
*/
#define PAU_LINK_TOUT_THRES 0x000003FFU
#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S)
#define PAU_LINK_TOUT_THRES_V 0x000003FFU
#define PAU_LINK_TOUT_THRES_S 7
/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8;
* burst limit
*/
#define PAU_BURST_LIMIT 0x0000001FU
#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S)
#define PAU_BURST_LIMIT_V 0x0000001FU
#define PAU_BURST_LIMIT_S 17
/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500;
* Backup timeout threshold
*/
#define PAU_BACKUP_TOUT_THRES 0x000003FFU
#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S)
#define PAU_BACKUP_TOUT_THRES_V 0x000003FFU
#define PAU_BACKUP_TOUT_THRES_S 22
/** PAU_RETENTION_LINK_BASE_REG register
* retention dma link base
*/
#define PAU_RETENTION_LINK_BASE_REG (DR_REG_PAU_BASE + 0x30)
/** PAU_LINK_BASE_ADDR : R/W; bitpos: [26:0]; default: 0;
* retention dma link base
*/
#define PAU_LINK_BASE_ADDR 0x07FFFFFFU
#define PAU_LINK_BASE_ADDR_M (PAU_LINK_BASE_ADDR_V << PAU_LINK_BASE_ADDR_S)
#define PAU_LINK_BASE_ADDR_V 0x07FFFFFFU
#define PAU_LINK_BASE_ADDR_S 0
/** PAU_RETENTION_CFG_REG register
* retention_cfg
*/
#define PAU_RETENTION_CFG_REG (DR_REG_PAU_BASE + 0x34)
/** PAU_RET_INV_CFG : R/W; bitpos: [31:0]; default: 4294967295;
* retention inv scan out
*/
#define PAU_RET_INV_CFG 0xFFFFFFFFU
#define PAU_RET_INV_CFG_M (PAU_RET_INV_CFG_V << PAU_RET_INV_CFG_S)
#define PAU_RET_INV_CFG_V 0xFFFFFFFFU
#define PAU_RET_INV_CFG_S 0
/** PAU_INT_ENA_REG register
* Read only register for error and done
*/
#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x38)
/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ENA (BIT(0))
#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
#define PAU_DONE_INT_ENA_V 0x00000001U
#define PAU_DONE_INT_ENA_S 0
/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ENA (BIT(1))
#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
#define PAU_ERROR_INT_ENA_V 0x00000001U
#define PAU_ERROR_INT_ENA_S 1
/** PAU_INT_RAW_REG register
* Read only register for error and done
*/
#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x3c)
/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_RAW (BIT(0))
#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
#define PAU_DONE_INT_RAW_V 0x00000001U
#define PAU_DONE_INT_RAW_S 0
/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_RAW (BIT(1))
#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
#define PAU_ERROR_INT_RAW_V 0x00000001U
#define PAU_ERROR_INT_RAW_S 1
/** PAU_INT_CLR_REG register
* Read only register for error and done
*/
#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x40)
/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_CLR (BIT(0))
#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
#define PAU_DONE_INT_CLR_V 0x00000001U
#define PAU_DONE_INT_CLR_S 0
/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_CLR (BIT(1))
#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
#define PAU_ERROR_INT_CLR_V 0x00000001U
#define PAU_ERROR_INT_CLR_S 1
/** PAU_INT_ST_REG register
* Read only register for error and done
*/
#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x44)
/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ST (BIT(0))
#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
#define PAU_DONE_INT_ST_V 0x00000001U
#define PAU_DONE_INT_ST_S 0
/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ST (BIT(1))
#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
#define PAU_ERROR_INT_ST_V 0x00000001U
#define PAU_ERROR_INT_ST_S 1
/** PAU_DATE_REG register
* Date register.
*/
#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
/** PAU_DATE : R/W; bitpos: [27:0]; default: 35663984;
* REGDMA date information/ REGDMA version information.
*/
#define PAU_DATE 0x0FFFFFFFU
#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S)
#define PAU_DATE_V 0x0FFFFFFFU
#define PAU_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of regdma_conf register
* Peri backup control register
*/
typedef union {
struct {
/** flow_err : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
uint32_t flow_err:3;
/** start : WT; bitpos: [3]; default: 0;
* backup start signal
*/
uint32_t start:1;
/** to_mem : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem:1;
/** link_sel : R/W; bitpos: [6:5]; default: 0;
* Link select
*/
uint32_t link_sel:2;
/** start_mac : WT; bitpos: [7]; default: 0;
* mac sw backup start signal
*/
uint32_t start_mac:1;
/** to_mem_mac : R/W; bitpos: [8]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem_mac:1;
/** sel_mac : R/W; bitpos: [9]; default: 0;
* mac hw/sw select
*/
uint32_t sel_mac:1;
uint32_t reserved_10:22;
};
uint32_t val;
} pau_regdma_conf_reg_t;
/** Type of regdma_clk_conf register
* Clock control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* clock enable
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} pau_regdma_clk_conf_reg_t;
/** Type of regdma_etm_ctrl register
* ETM start ctrl reg
*/
typedef union {
struct {
/** etm_start_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
uint32_t etm_start_0:1;
/** etm_start_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
uint32_t etm_start_1:1;
/** etm_start_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
uint32_t etm_start_2:1;
/** etm_start_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
uint32_t etm_start_3:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pau_regdma_etm_ctrl_reg_t;
/** Type of regdma_link_0_addr register
* link_0_addr
*/
typedef union {
struct {
/** link_addr_0 : R/W; bitpos: [31:0]; default: 0;
* link_0_addr reg
*/
uint32_t link_addr_0:32;
};
uint32_t val;
} pau_regdma_link_0_addr_reg_t;
/** Type of regdma_link_1_addr register
* Link_1_addr
*/
typedef union {
struct {
/** link_addr_1 : R/W; bitpos: [31:0]; default: 0;
* Link_1_addr reg
*/
uint32_t link_addr_1:32;
};
uint32_t val;
} pau_regdma_link_1_addr_reg_t;
/** Type of regdma_link_2_addr register
* Link_2_addr
*/
typedef union {
struct {
/** link_addr_2 : R/W; bitpos: [31:0]; default: 0;
* Link_2_addr reg
*/
uint32_t link_addr_2:32;
};
uint32_t val;
} pau_regdma_link_2_addr_reg_t;
/** Type of regdma_link_3_addr register
* Link_3_addr
*/
typedef union {
struct {
/** link_addr_3 : R/W; bitpos: [31:0]; default: 0;
* Link_3_addr reg
*/
uint32_t link_addr_3:32;
};
uint32_t val;
} pau_regdma_link_3_addr_reg_t;
/** Type of regdma_link_mac_addr register
* Link_mac_addr
*/
typedef union {
struct {
/** link_addr_mac : R/W; bitpos: [31:0]; default: 0;
* Link_mac_addr reg
*/
uint32_t link_addr_mac:32;
};
uint32_t val;
} pau_regdma_link_mac_addr_reg_t;
/** Type of regdma_current_link_addr register
* current link addr
*/
typedef union {
struct {
/** current_link_addr : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
uint32_t current_link_addr:32;
};
uint32_t val;
} pau_regdma_current_link_addr_reg_t;
/** Type of regdma_backup_addr register
* Backup addr
*/
typedef union {
struct {
/** backup_addr : RO; bitpos: [31:0]; default: 0;
* backup addr reg
*/
uint32_t backup_addr:32;
};
uint32_t val;
} pau_regdma_backup_addr_reg_t;
/** Type of regdma_mem_addr register
* mem addr
*/
typedef union {
struct {
/** mem_addr : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
uint32_t mem_addr:32;
};
uint32_t val;
} pau_regdma_mem_addr_reg_t;
/** Type of regdma_bkp_conf register
* backup config
*/
typedef union {
struct {
/** read_interval : R/W; bitpos: [6:0]; default: 32;
* Link read_interval
*/
uint32_t read_interval:7;
/** link_tout_thres : R/W; bitpos: [16:7]; default: 50;
* link wait timeout threshold
*/
uint32_t link_tout_thres:10;
/** burst_limit : R/W; bitpos: [21:17]; default: 8;
* burst limit
*/
uint32_t burst_limit:5;
/** backup_tout_thres : R/W; bitpos: [31:22]; default: 500;
* Backup timeout threshold
*/
uint32_t backup_tout_thres:10;
};
uint32_t val;
} pau_regdma_bkp_conf_reg_t;
/** Type of retention_link_base register
* retention dma link base
*/
typedef union {
struct {
/** link_base_addr : R/W; bitpos: [26:0]; default: 0;
* retention dma link base
*/
uint32_t link_base_addr:27;
uint32_t reserved_27:5;
};
uint32_t val;
} pau_retention_link_base_reg_t;
/** Type of retention_cfg register
* retention_cfg
*/
typedef union {
struct {
/** ret_inv_cfg : R/W; bitpos: [31:0]; default: 4294967295;
* retention inv scan out
*/
uint32_t ret_inv_cfg:32;
};
uint32_t val;
} pau_retention_cfg_reg_t;
/** Type of int_ena register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_ena : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_ena:1;
/** error_int_ena : R/W; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_ena_reg_t;
/** Type of int_raw register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_raw:1;
/** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_raw_reg_t;
/** Type of int_clr register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_clr : WT; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_clr:1;
/** error_int_clr : WT; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_clr_reg_t;
/** Type of int_st register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_st : RO; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_st:1;
/** error_int_st : RO; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_st_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35663984;
* REGDMA date information/ REGDMA version information.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} pau_date_reg_t;
typedef struct pau_dev_t {
volatile pau_regdma_conf_reg_t regdma_conf;
volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr;
volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr;
volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr;
volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr;
volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr;
volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr;
volatile pau_regdma_backup_addr_reg_t regdma_backup_addr;
volatile pau_regdma_mem_addr_reg_t regdma_mem_addr;
volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf;
volatile pau_retention_link_base_reg_t retention_link_base;
volatile pau_retention_cfg_reg_t retention_cfg;
volatile pau_int_ena_reg_t int_ena;
volatile pau_int_raw_reg_t int_raw;
volatile pau_int_clr_reg_t int_clr;
volatile pau_int_st_reg_t int_st;
uint32_t reserved_048[237];
volatile pau_date_reg_t date;
} pau_dev_t;
extern pau_dev_t PAU;
#ifndef __cplusplus
_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
* Configuration register 0 for unit n
*/
typedef union {
struct {
/** filter_thres : R/W; bitpos: [9:0]; default: 16;
* This sets the maximum threshold, in APB_CLK cycles, for the filter.
*
* Any pulses with width less than this will be ignored when the filter is enabled.
*/
uint32_t filter_thres:10;
/** filter_en : R/W; bitpos: [10]; default: 1;
* This is the enable bit for unit n's input filter.
*/
uint32_t filter_en:1;
/** thr_zero_en : R/W; bitpos: [11]; default: 1;
* This is the enable bit for unit n's zero comparator.
*/
uint32_t thr_zero_en:1;
/** thr_h_lim_en : R/W; bitpos: [12]; default: 1;
* This is the enable bit for unit n's thr_h_lim comparator.
*/
uint32_t thr_h_lim_en:1;
/** thr_l_lim_en : R/W; bitpos: [13]; default: 1;
* This is the enable bit for unit n's thr_l_lim comparator.
*/
uint32_t thr_l_lim_en:1;
/** thr_thres0_en : R/W; bitpos: [14]; default: 0;
* This is the enable bit for unit n's thres0 comparator.
*/
uint32_t thr_thres0_en:1;
/** thr_thres1_en : R/W; bitpos: [15]; default: 0;
* This is the enable bit for unit n's thres1 comparator.
*/
uint32_t thr_thres1_en:1;
/** ch0_neg_mode : R/W; bitpos: [17:16]; default: 0;
* This register sets the behavior when the signal input of channel 0 detects a
* negative edge.
*
* 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
*/
uint32_t ch0_neg_mode:2;
/** ch0_pos_mode : R/W; bitpos: [19:18]; default: 0;
* This register sets the behavior when the signal input of channel 0 detects a
* positive edge.
*
* 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
*/
uint32_t ch0_pos_mode:2;
/** ch0_hctrl_mode : R/W; bitpos: [21:20]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is high.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch0_hctrl_mode:2;
/** ch0_lctrl_mode : R/W; bitpos: [23:22]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is low.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch0_lctrl_mode:2;
/** ch1_neg_mode : R/W; bitpos: [25:24]; default: 0;
* This register sets the behavior when the signal input of channel 1 detects a
* negative edge.
*
* 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
*/
uint32_t ch1_neg_mode:2;
/** ch1_pos_mode : R/W; bitpos: [27:26]; default: 0;
* This register sets the behavior when the signal input of channel 1 detects a
* positive edge.
*
* 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
*/
uint32_t ch1_pos_mode:2;
/** ch1_hctrl_mode : R/W; bitpos: [29:28]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is high.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch1_hctrl_mode:2;
/** ch1_lctrl_mode : R/W; bitpos: [31:30]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is low.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch1_lctrl_mode:2;
};
uint32_t val;
} pcnt_un_conf0_reg_t;
/** Type of un_conf1 register
* Configuration register 1 for unit n
*/
typedef union {
struct {
/** cnt_thres0 : R/W; bitpos: [15:0]; default: 0;
* This register is used to configure the thres0 value for unit n.
*/
uint32_t cnt_thres0:16;
/** cnt_thres1 : R/W; bitpos: [31:16]; default: 0;
* This register is used to configure the thres1 value for unit n.
*/
uint32_t cnt_thres1:16;
};
uint32_t val;
} pcnt_un_conf1_reg_t;
/** Type of un_conf2 register
* Configuration register 2 for unit n
*/
typedef union {
struct {
/** cnt_h_lim : R/W; bitpos: [15:0]; default: 0;
* This register is used to configure the thr_h_lim value for unit n.
*/
uint32_t cnt_h_lim:16;
/** cnt_l_lim : R/W; bitpos: [31:16]; default: 0;
* This register is used to configure the thr_l_lim value for unit n.
*/
uint32_t cnt_l_lim:16;
};
uint32_t val;
} pcnt_un_conf2_reg_t;
/** Type of ctrl register
* Control register for all counters
*/
typedef union {
struct {
/** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
* Set this bit to clear unit 0's counter.
*/
uint32_t pulse_cnt_rst_u0:1;
/** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
* Set this bit to freeze unit 0's counter.
*/
uint32_t cnt_pause_u0:1;
/** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
* Set this bit to clear unit 1's counter.
*/
uint32_t pulse_cnt_rst_u1:1;
/** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
* Set this bit to freeze unit 1's counter.
*/
uint32_t cnt_pause_u1:1;
/** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
* Set this bit to clear unit 2's counter.
*/
uint32_t pulse_cnt_rst_u2:1;
/** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
* Set this bit to freeze unit 2's counter.
*/
uint32_t cnt_pause_u2:1;
/** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
* Set this bit to clear unit 3's counter.
*/
uint32_t pulse_cnt_rst_u3:1;
/** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
* Set this bit to freeze unit 3's counter.
*/
uint32_t cnt_pause_u3:1;
uint32_t reserved_8:8;
/** clk_en : R/W; bitpos: [16]; default: 0;
* The registers clock gate enable signal of PCNT module. 1: the registers can be read
* and written by application. 0: the registers can not be read or written by
* application
*/
uint32_t clk_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} pcnt_ctrl_reg_t;
/** Group: Status Register */
/** Type of un_cnt register
* Counter value for unit n
*/
typedef union {
struct {
/** pulse_cnt : RO; bitpos: [15:0]; default: 0;
* This register stores the current pulse count value for unit n.
*/
uint32_t pulse_cnt:16;
uint32_t reserved_16:16;
};
uint32_t val;
} pcnt_un_cnt_reg_t;
/** Type of un_status register
* PNCT UNITn status register
*/
typedef union {
struct {
/** cnt_thr_zero_mode : RO; bitpos: [1:0]; default: 0;
* The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
* from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
* is negative. 3: pulse counter is positive.
*/
uint32_t cnt_thr_zero_mode:2;
/** cnt_thr_thres1_lat : RO; bitpos: [2]; default: 0;
* The latched value of thres1 event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
* others
*/
uint32_t cnt_thr_thres1_lat:1;
/** cnt_thr_thres0_lat : RO; bitpos: [3]; default: 0;
* The latched value of thres0 event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
* others
*/
uint32_t cnt_thr_thres0_lat:1;
/** cnt_thr_l_lim_lat : RO; bitpos: [4]; default: 0;
* The latched value of low limit event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
* valid. 0: others
*/
uint32_t cnt_thr_l_lim_lat:1;
/** cnt_thr_h_lim_lat : RO; bitpos: [5]; default: 0;
* The latched value of high limit event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
* valid. 0: others
*/
uint32_t cnt_thr_h_lim_lat:1;
/** cnt_thr_zero_lat : RO; bitpos: [6]; default: 0;
* The latched value of zero threshold event of PCNT_Un when threshold event interrupt
* is valid. 1: the current pulse counter equals to 0 and zero threshold event is
* valid. 0: others
*/
uint32_t cnt_thr_zero_lat:1;
uint32_t reserved_7:25;
};
uint32_t val;
} pcnt_un_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* Interrupt raw status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_raw : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_raw:1;
/** cnt_thr_event_u1_int_raw : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_raw:1;
/** cnt_thr_event_u2_int_raw : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_raw:1;
/** cnt_thr_event_u3_int_raw : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_st:1;
/** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_st:1;
/** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_st:1;
/** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_ena:1;
/** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_ena:1;
/** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_ena:1;
/** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_clr : WO; bitpos: [0]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_clr:1;
/** cnt_thr_event_u1_int_clr : WO; bitpos: [1]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_clr:1;
/** cnt_thr_event_u2_int_clr : WO; bitpos: [2]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_clr:1;
/** cnt_thr_event_u3_int_clr : WO; bitpos: [3]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* PCNT version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 419898881;
* This is the PCNT version control register.
*/
uint32_t date:32;
};
uint32_t val;
} pcnt_date_reg_t;
typedef struct pcnt_dev_t {
volatile struct {
pcnt_un_conf0_reg_t conf0;
pcnt_un_conf1_reg_t conf1;
pcnt_un_conf2_reg_t conf2;
} conf_unit[4];
volatile pcnt_un_cnt_reg_t cnt_unit[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
volatile pcnt_int_ena_reg_t int_ena;
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t status_unit[4];
volatile pcnt_ctrl_reg_t ctrl;
uint32_t reserved_064[38];
volatile pcnt_date_reg_t date;
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#ifndef __cplusplus
_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_RMT_MODULE,
PERIPH_SPI_MODULE, //SPI1
PERIPH_SPI2_MODULE, //SPI2
PERIPH_TWAI0_MODULE,
PERIPH_TWAI1_MODULE,
PERIPH_RNG_MODULE,
PERIPH_WIFI_MODULE,
PERIPH_BT_MODULE,
PERIPH_WIFI_BT_COMMON_MODULE,
PERIPH_BT_BASEBAND_MODULE,
PERIPH_BT_LC_MODULE,
PERIPH_RSA_MODULE,
PERIPH_AES_MODULE,
PERIPH_SHA_MODULE,
PERIPH_HMAC_MODULE,
PERIPH_DS_MODULE,
PERIPH_GDMA_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_SARADC_MODULE,
PERIPH_MODULE_MAX
} periph_module_t;
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
ETS_LP_TIMER_INTR_SOURCE,
ETS_COEX_INTR_SOURCE,
ETS_BLE_TIMER_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
ETS_ZB_MAC_SOURCE,
ETS_PMU_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_LP_RTC_TIMER_INTR_SOURCE,
ETS_LP_UART_INTR_SOURCE,
ETS_LP_I2C_INTR_SOURCE,
ETS_LP_WDT_INTR_SOURCE,
ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
ETS_LP_APM_M0_INTR_SOURCE,
ETS_LP_APM_M1_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_TRACE_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
ETS_HP_APM_M0_INTR_SOURCE,
ETS_HP_APM_M1_INTR_SOURCE,
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/
ETS_TWAI1_INTR_SOURCE, /**< interrupt of can1, level*/
ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/
ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_PWM_INTR_SOURCE,
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_INTR_SOURCE,
ETS_SLC0_INTR_SOURCE,
ETS_SLC_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/
ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/
ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/
ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/
ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/
ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/
ETS_GSPI2_INTR_SOURCE,
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/
ETS_MAX_INTR_SOURCE,
} periph_interrput_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ICG_MAP_H_
#define _SOC_ICG_MAP_H_
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_APB_ENA_I2S 4
#define PMU_ICG_APB_ENA_INTMTX 3
#define PMU_ICG_APB_ENA_IOMUX 26
#define PMU_ICG_APB_ENA_LEDC 14
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
#define PMU_ICG_APB_ENA_MSPI 5
#define PMU_ICG_APB_ENA_PARL 23
#define PMU_ICG_APB_ENA_PCNT 20
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
#define PMU_ICG_APB_ENA_PWM 21
#define PMU_ICG_APB_ENA_REGDMA 24
#define PMU_ICG_APB_ENA_RMT 15
#define PMU_ICG_APB_ENA_SARADC 9
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_SOC_ETM 22
#define PMU_ICG_APB_ENA_SPI2 2
#define PMU_ICG_APB_ENA_SYSTIMER 16
#define PMU_ICG_APB_ENA_TG0 11
#define PMU_ICG_APB_ENA_TG1 12
#define PMU_ICG_APB_ENA_UART0 6
#define PMU_ICG_APB_ENA_UART1 7
#define PMU_ICG_APB_ENA_UHCI 8
#define PMU_ICG_APB_ENA_USB_DEVICE 17
#define PMU_ICG_FUNC_ENA_CAN0 31
#define PMU_ICG_FUNC_ENA_CAN1 30
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_I2S_RX 2
#define PMU_ICG_FUNC_ENA_I2S_TX 7
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
#define PMU_ICG_FUNC_ENA_PWM 22
#define PMU_ICG_FUNC_ENA_RMT 21
#define PMU_ICG_FUNC_ENA_SARADC 20
#define PMU_ICG_FUNC_ENA_SEC 19
#define PMU_ICG_FUNC_ENA_SPI2 1
#define PMU_ICG_FUNC_ENA_SYSTIMER 18
#define PMU_ICG_FUNC_ENA_TG0 14
#define PMU_ICG_FUNC_ENA_TG1 13
#define PMU_ICG_FUNC_ENA_TSENS 12
#define PMU_ICG_FUNC_ENA_UART0 3
#define PMU_ICG_FUNC_ENA_UART1 4
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
#define PMU_ICG_FUNC_ENA_GDMA 0
#define PMU_ICG_FUNC_ENA_SOC_ETM 16
#define PMU_ICG_FUNC_ENA_REGDMA 8
#define PMU_ICG_FUNC_ENA_RETENTION 9
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
#define PMU_ICG_FUNC_ENA_UHCI 5
#define PMU_ICG_FUNC_ENA_HPCORE 17
#define PMU_ICG_FUNC_ENA_HPBUS 15
#endif /* _SOC_ICG_MAP_H_ */

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DR_REG_CLINT_M_BASE 0x20001800
#define DR_REG_CLINT_U_BASE 0x20001C00
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_UART1_BASE 0x60001000
#define DR_REG_SPI0_BASE 0x60002000
#define DR_REG_SPI1_BASE 0x60003000
#define DR_REG_I2C_EXT_BASE 0x60004000
#define DR_REG_UHCI0_BASE 0x60005000
#define DR_REG_RMT_BASE 0x60006000
#define DR_REG_LEDC_BASE 0x60007000
#define DR_REG_TIMERGROUP0_BASE 0x60008000
#define DR_REG_TIMERGROUP1_BASE 0x60009000
#define DR_REG_SYSTIMER_BASE 0x6000A000
#define DR_REG_TWAI0_BASE 0x6000B000
#define DR_REG_I2S_BASE 0x6000C000
#define DR_REG_TWAI1_BASE 0x6000D000
#define DR_REG_APB_SARADC_BASE 0x6000E000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
#define DR_REG_ATOMIC_BASE 0x60011000
#define DR_REG_PCNT_BASE 0x60012000
#define DR_REG_SOC_ETM_BASE 0x60013000
#define DR_REG_MCPWM_BASE 0x60014000
#define DR_REG_PARL_IO_BASE 0x60015000
#define DR_REG_HINF_BASE 0x60016000
#define DR_REG_SLC_BASE 0x60017000
#define DR_REG_SLCHOST_BASE 0x60018000
#define DR_REG_PVT_MONITOR_BASE 0x60019000
#define DR_REG_GDMA_BASE 0x60080000
#define DR_REG_SPI2_BASE 0x60081000
#define DR_REG_AES_BASE 0x60088000
#define DR_REG_SHA_BASE 0x60089000
#define DR_REG_RSA_BASE 0x6008A000
#define DR_REG_ECC_MULT_BASE 0x6008B000
#define DR_REG_DS_BASE 0x6008C000
#define DR_REG_HMAC_BASE 0x6008D000
#define DR_REG_IO_MUX_BASE 0x60090000
#define DR_REG_GPIO_BASE 0x60091000
#define DR_REG_GPIO_EXT_BASE 0x60091f00 //ESP32C6-TODO
#define DR_REG_MEM_MONITOR_BASE 0x60092000
#define DR_REG_PAU_BASE 0x60093000
#define DR_REG_HP_SYSTEM_BASE 0x60095000
#define DR_REG_PCR_BASE 0x60096000
#define DR_REG_TEE_BASE 0x60098000
#define DR_REG_HP_APM_BASE 0x60099000
#define DR_REG_LP_APM0_BASE 0x60099800
#define DR_REG_MISC_BASE 0x6009F000
#define DR_REG_PMU_BASE 0x600B0000
#define DR_REG_LP_CLKRST_BASE 0x600B0400
#define DR_REG_EFUSE_BASE 0x600B0800
#define DR_REG_LP_TIMER_BASE 0x600B0C00
#define DR_REG_LP_AON_BASE 0x600B1000
#define DR_REG_LP_UART_BASE 0x600B1400
#define DR_REG_LP_I2C_BASE 0x600B1800
#define DR_REG_LP_WDT_BASE 0x600B1C00
#define DR_REG_LP_IO_BASE 0x600B2000
#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400
#define DR_REG_LPPERI_BASE 0x600B2800
#define DR_REG_LP_ANALOG_PERI_BASE 0x600B2C00
#define DR_REG_LP_TEE_BASE 0x600B3400
#define DR_REG_LP_APM_BASE 0x600B3800
#define DR_REG_OPT_DEBUG_BASE 0x600B3C00
#define DR_REG_TRACE_BASE 0x600C0000
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
#define DR_REG_CPU_BUS_MONITOR_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_EXTMEM_BASE 0x600C8000

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: FIFO R/W registers */
/** Type of chndata register
* The read and write data register for CHANNELn by apb fifo access.
*/
typedef union {
struct {
/** chndata : HRO; bitpos: [31:0]; default: 0;
* Read and write data for channel n via APB FIFO.
*/
uint32_t chndata:32;
};
uint32_t val;
} rmt_chndata_reg_t;
/** Type of chmdata register
* The read and write data register for CHANNEL$n by apb fifo access.
*/
typedef union {
struct {
/** chmdata : RO; bitpos: [31:0]; default: 0;
* Read and write data for channel $n via APB FIFO.
*/
uint32_t chmdata: 32;
};
uint32_t val;
} rmt_chmdata_reg_t;
/** Group: Configuration registers */
/** Type of chnconf0 register
* Channel n configure register 0
*/
typedef union {
struct {
/** tx_start_chn : WT; bitpos: [0]; default: 0;
* Set this bit to start sending data on CHANNELn.
*/
uint32_t tx_start_chn:1;
/** mem_rd_rst_chn : WT; bitpos: [1]; default: 0;
* Set this bit to reset read ram address for CHANNELn by accessing transmitter.
*/
uint32_t mem_rd_rst_chn:1;
/** apb_mem_rst_chn : WT; bitpos: [2]; default: 0;
* Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo.
*/
uint32_t apb_mem_rst_chn:1;
/** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0;
* Set this bit to restart transmission from the first data to the last data in
* CHANNELn.
*/
uint32_t tx_conti_mode_chn:1;
/** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0;
* This is the channel n enable bit for wraparound mode: it will resume sending at the
* start when the data to be sent is more than its memory size.
*/
uint32_t mem_tx_wrap_en_chn:1;
/** idle_out_lv_chn : R/W; bitpos: [5]; default: 0;
* This bit configures the level of output signal in CHANNELn when the latter is in
* IDLE state.
*/
uint32_t idle_out_lv_chn:1;
/** idle_out_en_chn : R/W; bitpos: [6]; default: 0;
* This is the output enable-control bit for CHANNELn in IDLE state.
*/
uint32_t idle_out_en_chn:1;
/** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0;
* Set this bit to stop the transmitter of CHANNELn sending data out.
*/
uint32_t tx_stop_chn:1;
/** div_cnt_chn : R/W; bitpos: [15:8]; default: 2;
* This register is used to configure the divider for clock of CHANNELn.
*/
uint32_t div_cnt_chn:8;
/** mem_size_chn : R/W; bitpos: [18:16]; default: 1;
* This register is used to configure the maximum size of memory allocated to CHANNELn.
*/
uint32_t mem_size_chn:3;
uint32_t reserved_19:1;
/** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1;
* 1: Add carrier modulation on the output signal only at the send data state for
* CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn.
* Only valid when RMT_CARRIER_EN_CHn is 1.
*/
uint32_t carrier_eff_en_chn:1;
/** carrier_en_chn : R/W; bitpos: [21]; default: 1;
* This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier
* modulation in the output signal. 0: No carrier modulation in sig_out.
*/
uint32_t carrier_en_chn:1;
/** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1;
* This bit is used to configure the position of carrier wave for CHANNELn.
*
* 1'h0: add carrier wave on low level.
*
* 1'h1: add carrier wave on high level.
*/
uint32_t carrier_out_lv_chn:1;
/** afifo_rst_chn : WT; bitpos: [23]; default: 0;
* Reserved
*/
uint32_t afifo_rst_chn:1;
/** conf_update_chn : WT; bitpos: [24]; default: 0;
* synchronization bit for CHANNELn
*/
uint32_t conf_update_chn:1;
uint32_t reserved_25:7;
};
uint32_t val;
} rmt_chnconf0_reg_t;
/** Type of chmconf0 register
* Channel m configure register 0
*/
typedef union {
struct {
/** div_cnt_chm : R/W; bitpos: [7:0]; default: 2;
* This register is used to configure the divider for clock of CHANNELm.
*/
uint32_t div_cnt_chm:8;
/** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767;
* When no edge is detected on the input signal and continuous clock cycles is longer
* than this register value, received process is finished.
*/
uint32_t idle_thres_chm:15;
/** mem_size_chm : R/W; bitpos: [25:23]; default: 1;
* This register is used to configure the maximum size of memory allocated to CHANNELm.
*/
uint32_t mem_size_chm:3;
uint32_t reserved_26:2;
/** carrier_en_chm : R/W; bitpos: [28]; default: 1;
* This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier
* modulation in the output signal. 0: No carrier modulation in sig_out.
*/
uint32_t carrier_en_chm:1;
/** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1;
* This bit is used to configure the position of carrier wave for CHANNELm.
*
* 1'h0: add carrier wave on low level.
*
* 1'h1: add carrier wave on high level.
*/
uint32_t carrier_out_lv_chm:1;
uint32_t reserved_30:2;
};
uint32_t val;
} rmt_chmconf0_reg_t;
/** Type of chmconf1 register
* Channel m configure register 1
*/
typedef union {
struct {
/** rx_en_chm : R/W; bitpos: [0]; default: 0;
* Set this bit to enable receiver to receive data on CHANNELm.
*/
uint32_t rx_en_chm:1;
/** mem_wr_rst_chm : WT; bitpos: [1]; default: 0;
* Set this bit to reset write ram address for CHANNELm by accessing receiver.
*/
uint32_t mem_wr_rst_chm:1;
/** apb_mem_rst_chm : WT; bitpos: [2]; default: 0;
* Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo.
*/
uint32_t apb_mem_rst_chm:1;
/** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1;
* This register marks the ownership of CHANNELm's ram block.
*
* 1'h1: Receiver is using the ram.
*
* 1'h0: APB bus is using the ram.
*/
uint32_t mem_owner_chm:1;
/** rx_filter_en_chm : R/W; bitpos: [4]; default: 0;
* This is the receive filter's enable bit for CHANNELm.
*/
uint32_t rx_filter_en_chm:1;
/** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15;
* Ignores the input pulse when its width is smaller than this register value in APB
* clock periods (in receive mode).
*/
uint32_t rx_filter_thres_chm:8;
/** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0;
* This is the channel m enable bit for wraparound mode: it will resume receiving at
* the start when the data to be received is more than its memory size.
*/
uint32_t mem_rx_wrap_en_chm:1;
/** afifo_rst_chm : WT; bitpos: [14]; default: 0;
* Reserved
*/
uint32_t afifo_rst_chm:1;
/** conf_update_chm : WT; bitpos: [15]; default: 0;
* synchronization bit for CHANNELm
*/
uint32_t conf_update_chm:1;
uint32_t reserved_16:16;
};
uint32_t val;
} rmt_chmconf1_reg_t;
/** Type of sys_conf register
* RMT apb configuration register
*/
typedef union {
struct {
/** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
* 1'h1: access memory directly. 1'h0: access memory by FIFO.
*/
uint32_t apb_fifo_mask:1;
/** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
* Set this bit to enable the clock for RMT memory.
*/
uint32_t mem_clk_force_on:1;
/** mem_force_pd : R/W; bitpos: [2]; default: 0;
* Set this bit to power down RMT memory.
*/
uint32_t mem_force_pd:1;
/** mem_force_pu : R/W; bitpos: [3]; default: 0;
* 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory
* when RMT is in light sleep mode.
*/
uint32_t mem_force_pu:1;
/** sclk_div_num : R/W; bitpos: [11:4]; default: 1;
* the integral part of the fractional divisor
*/
uint32_t sclk_div_num:8;
/** sclk_div_a : R/W; bitpos: [17:12]; default: 0;
* the numerator of the fractional part of the fractional divisor
*/
uint32_t sclk_div_a:6;
/** sclk_div_b : R/W; bitpos: [23:18]; default: 0;
* the denominator of the fractional part of the fractional divisor
*/
uint32_t sclk_div_b:6;
/** sclk_sel : R/W; bitpos: [25:24]; default: 1;
* choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL
*/
uint32_t sclk_sel:2;
/** sclk_active : R/W; bitpos: [26]; default: 1;
* rmt_sclk switch
*/
uint32_t sclk_active:1;
uint32_t reserved_27:4;
/** clk_en : R/W; bitpos: [31]; default: 0;
* RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0:
* Power down the drive clock of registers
*/
uint32_t clk_en:1;
};
uint32_t val;
} rmt_sys_conf_reg_t;
/** Type of ref_cnt_rst register
* RMT clock divider reset register
*/
typedef union {
struct {
/** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0;
* This register is used to reset the clock divider of CHANNEL0.
*/
uint32_t ref_cnt_rst_ch0:1;
/** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0;
* This register is used to reset the clock divider of CHANNEL1.
*/
uint32_t ref_cnt_rst_ch1:1;
/** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0;
* This register is used to reset the clock divider of CHANNEL2.
*/
uint32_t ref_cnt_rst_ch2:1;
/** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0;
* This register is used to reset the clock divider of CHANNEL3.
*/
uint32_t ref_cnt_rst_ch3:1;
uint32_t reserved_4:28;
};
uint32_t val;
} rmt_ref_cnt_rst_reg_t;
/** Group: Status registers */
/** Type of chnstatus register
* Channel n status register
*/
typedef union {
struct {
/** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0;
* This register records the memory address offset when transmitter of CHANNELn is
* using the RAM.
*/
uint32_t mem_raddr_ex_chn:9;
/** state_chn : RO; bitpos: [11:9]; default: 0;
* This register records the FSM status of CHANNELn.
*/
uint32_t state_chn:3;
/** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0;
* This register records the memory address offset when writes RAM over APB bus.
*/
uint32_t apb_mem_waddr_chn:9;
/** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0;
* This status bit will be set if the offset address out of memory size when reading
* via APB bus.
*/
uint32_t apb_mem_rd_err_chn:1;
/** mem_empty_chn : RO; bitpos: [22]; default: 0;
* This status bit will be set when the data to be set is more than memory size and
* the wraparound mode is disabled.
*/
uint32_t mem_empty_chn:1;
/** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0;
* This status bit will be set if the offset address out of memory size when writes
* via APB bus.
*/
uint32_t apb_mem_wr_err_chn:1;
/** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0;
* This register records the memory address offset when reading RAM over APB bus.
*/
uint32_t apb_mem_raddr_chn:8;
};
uint32_t val;
} rmt_chnstatus_reg_t;
/** Type of chmstatus register
* Channel m status register
*/
typedef union {
struct {
/** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0;
* This register records the memory address offset when receiver of CHANNELm is using
* the RAM.
*/
uint32_t mem_waddr_ex_chm:9;
uint32_t reserved_9:3;
/** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0;
* This register records the memory address offset when reads RAM over APB bus.
*/
uint32_t apb_mem_raddr_chm:9;
uint32_t reserved_21:1;
/** state_chm : RO; bitpos: [24:22]; default: 0;
* This register records the FSM status of CHANNELm.
*/
uint32_t state_chm:3;
/** mem_owner_err_chm : RO; bitpos: [25]; default: 0;
* This status bit will be set when the ownership of memory block is wrong.
*/
uint32_t mem_owner_err_chm:1;
/** mem_full_chm : RO; bitpos: [26]; default: 0;
* This status bit will be set if the receiver receives more data than the memory size.
*/
uint32_t mem_full_chm:1;
/** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0;
* This status bit will be set if the offset address out of memory size when reads via
* APB bus.
*/
uint32_t apb_mem_rd_err_chm:1;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_chmstatus_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmission done.
*/
uint32_t ch0_tx_end_int_raw:1;
/** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmission done.
*/
uint32_t ch1_tx_end_int_raw:1;
/** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when reception done.
*/
uint32_t ch2_rx_end_int_raw:1;
/** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when reception done.
*/
uint32_t ch3_rx_end_int_raw:1;
/** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch0_err_int_raw:1;
/** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch1_err_int_raw:1;
/** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch2_err_int_raw:1;
/** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch3_err_int_raw:1;
/** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch0_tx_thr_event_int_raw:1;
/** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch1_tx_thr_event_int_raw:1;
/** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch2_rx_thr_event_int_raw:1;
/** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch3_rx_thr_event_int_raw:1;
/** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch0_tx_loop_int_raw:1;
/** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch1_tx_loop_int_raw:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_raw_reg_t;
/** Type of int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_st:1;
/** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_st:1;
/** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_st:1;
/** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_st:1;
/** ch0_err_int_st : RO; bitpos: [4]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_st:1;
/** ch1_err_int_st : RO; bitpos: [5]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_st:1;
/** ch2_err_int_st : RO; bitpos: [6]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_st:1;
/** ch3_err_int_st : RO; bitpos: [7]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_st:1;
/** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0;
* The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_st:1;
/** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0;
* The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_st:1;
/** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0;
* The masked interrupt status bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_st:1;
/** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0;
* The masked interrupt status bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_st:1;
/** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0;
* The masked interrupt status bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_st:1;
/** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0;
* The masked interrupt status bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_st:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_ena:1;
/** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_ena:1;
/** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_ena:1;
/** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_ena:1;
/** ch0_err_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_ena:1;
/** ch1_err_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_ena:1;
/** ch2_err_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_ena:1;
/** ch3_err_int_ena : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_ena:1;
/** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_ena:1;
/** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_ena:1;
/** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_ena:1;
/** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_ena:1;
/** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0;
* The interrupt enable bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_ena:1;
/** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0;
* The interrupt enable bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_ena:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear theCH0_TX_END_INT interrupt.
*/
uint32_t ch0_tx_end_int_clr:1;
/** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear theCH1_TX_END_INT interrupt.
*/
uint32_t ch1_tx_end_int_clr:1;
/** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear theCH2_RX_END_INT interrupt.
*/
uint32_t ch2_rx_end_int_clr:1;
/** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear theCH3_RX_END_INT interrupt.
*/
uint32_t ch3_rx_end_int_clr:1;
/** ch0_err_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch0_err_int_clr:1;
/** ch1_err_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch1_err_int_clr:1;
/** ch2_err_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch2_err_int_clr:1;
/** ch3_err_int_clr : WT; bitpos: [7]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch3_err_int_clr:1;
/** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0;
* Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch0_tx_thr_event_int_clr:1;
/** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0;
* Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch1_tx_thr_event_int_clr:1;
/** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch2_rx_thr_event_int_clr:1;
/** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0;
* Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch3_rx_thr_event_int_clr:1;
/** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0;
* Set this bit to clear theCH0_TX_LOOP_INT interrupt.
*/
uint32_t ch0_tx_loop_int_clr:1;
/** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0;
* Set this bit to clear theCH1_TX_LOOP_INT interrupt.
*/
uint32_t ch1_tx_loop_int_clr:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_clr_reg_t;
/** Group: Carrier wave duty cycle registers */
/** Type of chncarrier_duty register
* Channel n duty cycle configuration register
*/
typedef union {
struct {
/** carrier_low_chn : R/W; bitpos: [15:0]; default: 64;
* This register is used to configure carrier wave 's low level clock period for
* CHANNELn.
*/
uint32_t carrier_low_chn:16;
/** carrier_high_chn : R/W; bitpos: [31:16]; default: 64;
* This register is used to configure carrier wave 's high level clock period for
* CHANNELn.
*/
uint32_t carrier_high_chn:16;
};
uint32_t val;
} rmt_chncarrier_duty_reg_t;
/** Type of chm_rx_carrier_rm register
* Channel m carrier remove register
*/
typedef union {
struct {
/** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0;
* The low level period in a carrier modulation mode is
* (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m.
*/
uint32_t carrier_low_thres_chm:16;
/** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0;
* The high level period in a carrier modulation mode is
* (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m.
*/
uint32_t carrier_high_thres_chm:16;
};
uint32_t val;
} rmt_chm_rx_carrier_rm_reg_t;
/** Group: Tx event configuration registers */
/** Type of chn_tx_lim register
* Channel n Tx event configuration register
*/
typedef union {
struct {
/** tx_lim_chn : R/W; bitpos: [8:0]; default: 128;
* This register is used to configure the maximum entries that CHANNELn can send out.
*/
uint32_t tx_lim_chn:9;
/** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0;
* This register is used to configure the maximum loop count when tx_conti_mode is
* valid.
*/
uint32_t tx_loop_num_chn:10;
/** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0;
* This register is the enabled bit for loop count.
*/
uint32_t tx_loop_cnt_en_chn:1;
/** loop_count_reset_chn : WT; bitpos: [20]; default: 0;
* This register is used to reset the loop count when tx_conti_mode is valid.
*/
uint32_t loop_count_reset_chn:1;
/** loop_stop_en_chn : R/W; bitpos: [21]; default: 0;
* This bit is used to enable the loop send stop function after the loop counter
* counts to loop number for CHANNELn.
*/
uint32_t loop_stop_en_chn:1;
uint32_t reserved_22:10;
};
uint32_t val;
} rmt_chn_tx_lim_reg_t;
/** Type of tx_sim register
* RMT TX synchronous register
*/
typedef union {
struct {
/** tx_sim_ch0 : R/W; bitpos: [0]; default: 0;
* Set this bit to enable CHANNEL0 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch0:1;
/** tx_sim_ch1 : R/W; bitpos: [1]; default: 0;
* Set this bit to enable CHANNEL1 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch1:1;
/** tx_sim_en : R/W; bitpos: [2]; default: 0;
* This register is used to enable multiple of channels to start sending data
* synchronously.
*/
uint32_t tx_sim_en:1;
uint32_t reserved_3:29;
};
uint32_t val;
} rmt_tx_sim_reg_t;
/** Group: Rx event configuration registers */
/** Type of chm_rx_lim register
* Channel m Rx event configuration register
*/
typedef union {
struct {
/** rmt_rx_lim_chm : R/W; bitpos: [8:0]; default: 128;
* This register is used to configure the maximum entries that CHANNELm can receive.
*/
uint32_t rmt_rx_lim_chm:9;
uint32_t reserved_9:23;
};
uint32_t val;
} rmt_chm_rx_lim_reg_t;
/** Group: Version register */
/** Type of date register
* RMT version register
*/
typedef union {
struct {
/** rmt_date : R/W; bitpos: [27:0]; default: 34636307;
* This is the version register.
*/
uint32_t rmt_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_date_reg_t;
typedef struct rmt_dev_t {
volatile rmt_chndata_reg_t chndata[2];
volatile rmt_chmdata_reg_t chmdata[2];
volatile rmt_chnconf0_reg_t chnconf0[2];
volatile struct {
rmt_chmconf0_reg_t conf0;
rmt_chmconf1_reg_t conf1;
} chmconf[2];
volatile rmt_chnstatus_reg_t chnstatus[2];
volatile rmt_chmstatus_reg_t chmstatus[2];
volatile rmt_int_raw_reg_t int_raw;
volatile rmt_int_st_reg_t int_st;
volatile rmt_int_ena_reg_t int_ena;
volatile rmt_int_clr_reg_t int_clr;
volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2];
volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2];
volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2];
volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2];
volatile rmt_sys_conf_reg_t sys_conf;
volatile rmt_tx_sim_reg_t tx_sim;
volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst;
uint32_t reserved_074[22];
volatile rmt_date_reg_t date;
} rmt_dev_t;
extern rmt_dev_t RMT;
#ifndef __cplusplus
_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c6/include/soc/rsa_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RSA_M_MEM register
* Represents M
*/
#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
#define RSA_M_MEM_SIZE_BYTES 16
/** RSA_Z_MEM register
* Represents Z
*/
#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
#define RSA_Z_MEM_SIZE_BYTES 16
/** RSA_Y_MEM register
* Represents Y
*/
#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400)
#define RSA_Y_MEM_SIZE_BYTES 16
/** RSA_X_MEM register
* Represents X
*/
#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600)
#define RSA_X_MEM_SIZE_BYTES 16
/** RSA_M_PRIME_REG register
* Represents M'
*/
#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
* Represents M'
*/
#define RSA_M_PRIME 0xFFFFFFFFU
#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S)
#define RSA_M_PRIME_V 0xFFFFFFFFU
#define RSA_M_PRIME_S 0
/** RSA_MODE_REG register
* Configures RSA length
*/
#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
/** RSA_MODE : R/W; bitpos: [6:0]; default: 0;
* Configures the RSA length.
*/
#define RSA_MODE 0x0000007FU
#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S)
#define RSA_MODE_V 0x0000007FU
#define RSA_MODE_S 0
/** RSA_QUERY_CLEAN_REG register
* RSA clean register
*/
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.
*
* 0: Not complete
*
* 1: Completed
*
*/
#define RSA_QUERY_CLEAN (BIT(0))
#define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S)
#define RSA_QUERY_CLEAN_V 0x00000001U
#define RSA_QUERY_CLEAN_S 0
/** RSA_SET_START_MODEXP_REG register
* Starts modular exponentiation
*/
#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c)
/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular exponentiation.
*
* 0: No effect
*
* 1: Start
*
*/
#define RSA_SET_START_MODEXP (BIT(0))
#define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S)
#define RSA_SET_START_MODEXP_V 0x00000001U
#define RSA_SET_START_MODEXP_S 0
/** RSA_SET_START_MODMULT_REG register
* Starts modular multiplication
*/
#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810)
/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
#define RSA_SET_START_MODMULT (BIT(0))
#define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S)
#define RSA_SET_START_MODMULT_V 0x00000001U
#define RSA_SET_START_MODMULT_S 0
/** RSA_SET_START_MULT_REG register
* Starts multiplication
*/
#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814)
/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
#define RSA_SET_START_MULT (BIT(0))
#define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S)
#define RSA_SET_START_MULT_V 0x00000001U
#define RSA_SET_START_MULT_S 0
/** RSA_QUERY_IDLE_REG register
* Represents the RSA status
*/
#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818)
/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0;
* Represents the RSA status.
*
* 0: Busy
*
* 1: Idle
*
*/
#define RSA_QUERY_IDLE (BIT(0))
#define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S)
#define RSA_QUERY_IDLE_V 0x00000001U
#define RSA_QUERY_IDLE_S 0
/** RSA_INT_CLR_REG register
* Clears RSA interrupt
*/
#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c)
/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0;
* Write 1 to clear the RSA interrupt.
*/
#define RSA_CLEAR_INTERRUPT (BIT(0))
#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
#define RSA_CLEAR_INTERRUPT_V 0x00000001U
#define RSA_CLEAR_INTERRUPT_S 0
/** RSA_CONSTANT_TIME_REG register
* Configures the constant_time option
*/
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option.
*
* 0: Acceleration
*
* 1: No acceleration (default)
*
*/
#define RSA_CONSTANT_TIME (BIT(0))
#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
#define RSA_CONSTANT_TIME_V 0x00000001U
#define RSA_CONSTANT_TIME_S 0
/** RSA_SEARCH_ENABLE_REG register
* Configures the search option
*/
#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
* Configure the search option.
*
* 0: No acceleration (default)
*
* 1: Acceleration
*
* This option should be used together with RSA_SEARCH_POS.
*/
#define RSA_SEARCH_ENABLE (BIT(0))
#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
#define RSA_SEARCH_ENABLE_V 0x00000001U
#define RSA_SEARCH_ENABLE_S 0
/** RSA_SEARCH_POS_REG register
* Configures the search position
*/
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
* Configures the starting address to start search. This field should be used together
* with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
*/
#define RSA_SEARCH_POS 0x00000FFFU
#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
#define RSA_SEARCH_POS_V 0x00000FFFU
#define RSA_SEARCH_POS_S 0
/** RSA_INT_ENA_REG register
* Enables the RSA interrupt
*/
#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the RSA interrupt.
*/
#define RSA_INT_ENA (BIT(0))
#define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S)
#define RSA_INT_ENA_V 0x00000001U
#define RSA_INT_ENA_S 0
/** RSA_DATE_REG register
* Version control register
*/
#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624;
* Version control register.
*/
#define RSA_DATE 0x3FFFFFFFU
#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S)
#define RSA_DATE_V 0x3FFFFFFFU
#define RSA_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory */
/** Group: Control / Configuration Registers */
/** Type of m_prime register
* Represents M'
*/
typedef union {
struct {
/** m_prime : R/W; bitpos: [31:0]; default: 0;
* Represents M'
*/
uint32_t m_prime:32;
};
uint32_t val;
} rsa_m_prime_reg_t;
/** Type of mode register
* Configures RSA length
*/
typedef union {
struct {
/** mode : R/W; bitpos: [6:0]; default: 0;
* Configures the RSA length.
*/
uint32_t mode:7;
uint32_t reserved_7:25;
};
uint32_t val;
} rsa_mode_reg_t;
/** Type of set_start_modexp register
* Starts modular exponentiation
*/
typedef union {
struct {
/** set_start_modexp : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular exponentiation.
*
* 0: No effect
*
* 1: Start
*
*/
uint32_t set_start_modexp:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_modexp_reg_t;
/** Type of set_start_modmult register
* Starts modular multiplication
*/
typedef union {
struct {
/** set_start_modmult : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the modular multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
uint32_t set_start_modmult:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_modmult_reg_t;
/** Type of set_start_mult register
* Starts multiplication
*/
typedef union {
struct {
/** set_start_mult : WT; bitpos: [0]; default: 0;
* Configure whether or not to start the multiplication.
*
* 0: No effect
*
* 1: Start
*
*/
uint32_t set_start_mult:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_set_start_mult_reg_t;
/** Type of query_idle register
* Represents the RSA status
*/
typedef union {
struct {
/** query_idle : RO; bitpos: [0]; default: 0;
* Represents the RSA status.
*
* 0: Busy
*
* 1: Idle
*
*/
uint32_t query_idle:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_query_idle_reg_t;
/** Type of constant_time register
* Configures the constant_time option
*/
typedef union {
struct {
/** constant_time : R/W; bitpos: [0]; default: 1;
* Configures the constant_time option.
*
* 0: Acceleration
*
* 1: No acceleration (default)
*
*/
uint32_t constant_time:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_constant_time_reg_t;
/** Type of search_enable register
* Configures the search option
*/
typedef union {
struct {
/** search_enable : R/W; bitpos: [0]; default: 0;
* Configure the search option.
*
* 0: No acceleration (default)
*
* 1: Acceleration
*
* This option should be used together with RSA_SEARCH_POS.
*/
uint32_t search_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_search_enable_reg_t;
/** Type of search_pos register
* Configures the search position
*/
typedef union {
struct {
/** search_pos : R/W; bitpos: [11:0]; default: 0;
* Configures the starting address to start search. This field should be used together
* with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
*/
uint32_t search_pos:12;
uint32_t reserved_12:20;
};
uint32_t val;
} rsa_search_pos_reg_t;
/** Group: Status Register */
/** Type of query_clean register
* RSA clean register
*/
typedef union {
struct {
/** query_clean : RO; bitpos: [0]; default: 0;
* Represents whether or not the RSA memory completes initialization.
*
* 0: Not complete
*
* 1: Completed
*
*/
uint32_t query_clean:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_query_clean_reg_t;
/** Group: Interrupt Registers */
/** Type of int_clr register
* Clears RSA interrupt
*/
typedef union {
struct {
/** clear_interrupt : WT; bitpos: [0]; default: 0;
* Write 1 to clear the RSA interrupt.
*/
uint32_t clear_interrupt:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_int_clr_reg_t;
/** Type of int_ena register
* Enables the RSA interrupt
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the RSA interrupt.
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} rsa_int_ena_reg_t;
/** Group: Version Control Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* Version control register.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} rsa_date_reg_t;
typedef struct rsa_dev_t {
volatile uint32_t m[4];
uint32_t reserved_010[124];
volatile uint32_t z[4];
uint32_t reserved_210[124];
volatile uint32_t y[4];
uint32_t reserved_410[124];
volatile uint32_t x[4];
uint32_t reserved_610[124];
volatile rsa_m_prime_reg_t m_prime;
volatile rsa_mode_reg_t mode;
volatile rsa_query_clean_reg_t query_clean;
volatile rsa_set_start_modexp_reg_t set_start_modexp;
volatile rsa_set_start_modmult_reg_t set_start_modmult;
volatile rsa_set_start_mult_reg_t set_start_mult;
volatile rsa_query_idle_reg_t query_idle;
volatile rsa_int_clr_reg_t int_clr;
volatile rsa_constant_time_reg_t constant_time;
volatile rsa_search_enable_reg_t search_enable;
volatile rsa_search_pos_reg_t search_pos;
volatile rsa_int_ena_reg_t int_ena;
volatile rsa_date_reg_t date;
} rsa_dev_t;
extern rsa_dev_t RSA;
#ifndef __cplusplus
_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SHA_MODE_REG register
* Initial configuration register.
*/
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* Sha mode.
*/
#define SHA_MODE 0x00000007U
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
#define SHA_MODE_V 0x00000007U
#define SHA_MODE_S 0
/** SHA_T_STRING_REG register
* SHA 512/t configuration register 0.
*/
#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
* Sha t_string (used if and only if mode == SHA_512/t).
*/
#define SHA_T_STRING 0xFFFFFFFFU
#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S)
#define SHA_T_STRING_V 0xFFFFFFFFU
#define SHA_T_STRING_S 0
/** SHA_T_LENGTH_REG register
* SHA 512/t configuration register 1.
*/
#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
* Sha t_length (used if and only if mode == SHA_512/t).
*/
#define SHA_T_LENGTH 0x0000003FU
#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
#define SHA_T_LENGTH_V 0x0000003FU
#define SHA_T_LENGTH_S 0
/** SHA_DMA_BLOCK_NUM_REG register
* DMA configuration register 0.
*/
#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
* Dma-sha block number.
*/
#define SHA_DMA_BLOCK_NUM 0x0000003FU
#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
#define SHA_DMA_BLOCK_NUM_V 0x0000003FU
#define SHA_DMA_BLOCK_NUM_S 0
/** SHA_START_REG register
* Typical SHA configuration register 0.
*/
#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
/** SHA_START : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
#define SHA_START 0x7FFFFFFFU
#define SHA_START_M (SHA_START_V << SHA_START_S)
#define SHA_START_V 0x7FFFFFFFU
#define SHA_START_S 1
/** SHA_CONTINUE_REG register
* Typical SHA configuration register 1.
*/
#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
#define SHA_CONTINUE 0x7FFFFFFFU
#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
#define SHA_CONTINUE_V 0x7FFFFFFFU
#define SHA_CONTINUE_S 1
/** SHA_BUSY_REG register
* Busy register.
*/
#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Sha busy state. 1'b0: idle. 1'b1: busy.
*/
#define SHA_BUSY_STATE (BIT(0))
#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
#define SHA_BUSY_STATE_V 0x00000001U
#define SHA_BUSY_STATE_S 0
/** SHA_DMA_START_REG register
* DMA configuration register 1.
*/
#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
* Start dma-sha.
*/
#define SHA_DMA_START (BIT(0))
#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S)
#define SHA_DMA_START_V 0x00000001U
#define SHA_DMA_START_S 0
/** SHA_DMA_CONTINUE_REG register
* DMA configuration register 2.
*/
#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
* Continue dma-sha.
*/
#define SHA_DMA_CONTINUE (BIT(0))
#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
#define SHA_DMA_CONTINUE_V 0x00000001U
#define SHA_DMA_CONTINUE_S 0
/** SHA_CLEAR_IRQ_REG register
* Interrupt clear register.
*/
#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
* Clear sha interrupt.
*/
#define SHA_CLEAR_INTERRUPT (BIT(0))
#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
#define SHA_CLEAR_INTERRUPT_V 0x00000001U
#define SHA_CLEAR_INTERRUPT_S 0
/** SHA_IRQ_ENA_REG register
* Interrupt enable register.
*/
#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
*/
#define SHA_INTERRUPT_ENA (BIT(0))
#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
#define SHA_INTERRUPT_ENA_V 0x00000001U
#define SHA_INTERRUPT_ENA_S 0
/** SHA_DATE_REG register
* Date register.
*/
#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
* Sha date information/ sha version information.
*/
#define SHA_DATE 0x3FFFFFFFU
#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S)
#define SHA_DATE_V 0x3FFFFFFFU
#define SHA_DATE_S 0
/** SHA_H_MEM register
* Sha H memory which contains intermediate hash or finial hash.
*/
#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
#define SHA_H_MEM_SIZE_BYTES 64
/** SHA_M_MEM register
* Sha M memory which contains message.
*/
#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
#define SHA_M_MEM_SIZE_BYTES 64
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of mode register
* Initial configuration register.
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* Sha mode.
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} sha_mode_reg_t;
/** Type of t_string register
* SHA 512/t configuration register 0.
*/
typedef union {
struct {
/** t_string : R/W; bitpos: [31:0]; default: 0;
* Sha t_string (used if and only if mode == SHA_512/t).
*/
uint32_t t_string:32;
};
uint32_t val;
} sha_t_string_reg_t;
/** Type of t_length register
* SHA 512/t configuration register 1.
*/
typedef union {
struct {
/** t_length : R/W; bitpos: [5:0]; default: 0;
* Sha t_length (used if and only if mode == SHA_512/t).
*/
uint32_t t_length:6;
uint32_t reserved_6:26;
};
uint32_t val;
} sha_t_length_reg_t;
/** Type of dma_block_num register
* DMA configuration register 0.
*/
typedef union {
struct {
/** dma_block_num : R/W; bitpos: [5:0]; default: 0;
* Dma-sha block number.
*/
uint32_t dma_block_num:6;
uint32_t reserved_6:26;
};
uint32_t val;
} sha_dma_block_num_reg_t;
/** Type of start register
* Typical SHA configuration register 0.
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** start : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
uint32_t start:31;
};
uint32_t val;
} sha_start_reg_t;
/** Type of continue register
* Typical SHA configuration register 1.
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** conti : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
uint32_t conti:31;
};
uint32_t val;
} sha_continue_reg_t;
/** Type of dma_start register
* DMA configuration register 1.
*/
typedef union {
struct {
/** dma_start : WO; bitpos: [0]; default: 0;
* Start dma-sha.
*/
uint32_t dma_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_start_reg_t;
/** Type of dma_continue register
* DMA configuration register 2.
*/
typedef union {
struct {
/** dma_continue : WO; bitpos: [0]; default: 0;
* Continue dma-sha.
*/
uint32_t dma_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_continue_reg_t;
/** Group: Status Register */
/** Type of busy register
* Busy register.
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Sha busy state. 1'b0: idle. 1'b1: busy.
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_busy_reg_t;
/** Group: Interrupt Register */
/** Type of clear_irq register
* Interrupt clear register.
*/
typedef union {
struct {
/** clear_interrupt : WO; bitpos: [0]; default: 0;
* Clear sha interrupt.
*/
uint32_t clear_interrupt:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_clear_irq_reg_t;
/** Type of irq_ena register
* Interrupt enable register.
*/
typedef union {
struct {
/** interrupt_ena : R/W; bitpos: [0]; default: 0;
* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
*/
uint32_t interrupt_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_irq_ena_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538972713;
* Sha date information/ sha version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} sha_date_reg_t;
/** Group: memory type */
typedef struct sha_dev_t {
volatile sha_mode_reg_t mode;
volatile sha_t_string_reg_t t_string;
volatile sha_t_length_reg_t t_length;
volatile sha_dma_block_num_reg_t dma_block_num;
volatile sha_start_reg_t start;
volatile sha_continue_reg_t conti;
volatile sha_busy_reg_t busy;
volatile sha_dma_start_reg_t dma_start;
volatile sha_dma_continue_reg_t dma_continue;
volatile sha_clear_irq_reg_t clear_irq;
volatile sha_irq_ena_reg_t irq_ena;
volatile sha_date_reg_t date;
uint32_t reserved_030[4];
volatile uint32_t h[16];
volatile uint32_t m[16];
} sha_dev_t;
extern sha_dev_t SHA;
#ifndef __cplusplus
_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define GPIO_EVT_CH0_RISE_EDGE 1
#define GPIO_EVT_CH1_RISE_EDGE 2
#define GPIO_EVT_CH2_RISE_EDGE 3
#define GPIO_EVT_CH3_RISE_EDGE 4
#define GPIO_EVT_CH4_RISE_EDGE 5
#define GPIO_EVT_CH5_RISE_EDGE 6
#define GPIO_EVT_CH6_RISE_EDGE 7
#define GPIO_EVT_CH7_RISE_EDGE 8
#define GPIO_EVT_CH0_FALL_EDGE 9
#define GPIO_EVT_CH1_FALL_EDGE 10
#define GPIO_EVT_CH2_FALL_EDGE 11
#define GPIO_EVT_CH3_FALL_EDGE 12
#define GPIO_EVT_CH4_FALL_EDGE 13
#define GPIO_EVT_CH5_FALL_EDGE 14
#define GPIO_EVT_CH6_FALL_EDGE 15
#define GPIO_EVT_CH7_FALL_EDGE 16
#define GPIO_EVT_CH0_ANY_EDGE 17
#define GPIO_EVT_CH1_ANY_EDGE 18
#define GPIO_EVT_CH2_ANY_EDGE 19
#define GPIO_EVT_CH3_ANY_EDGE 20
#define GPIO_EVT_CH4_ANY_EDGE 21
#define GPIO_EVT_CH5_ANY_EDGE 22
#define GPIO_EVT_CH6_ANY_EDGE 23
#define GPIO_EVT_CH7_ANY_EDGE 24
#define LEDC_EVT_DUTY_CHNG_END_CH0 25
#define LEDC_EVT_DUTY_CHNG_END_CH1 26
#define LEDC_EVT_DUTY_CHNG_END_CH2 27
#define LEDC_EVT_DUTY_CHNG_END_CH3 28
#define LEDC_EVT_DUTY_CHNG_END_CH4 29
#define LEDC_EVT_DUTY_CHNG_END_CH5 30
#define LEDC_EVT_OVF_CNT_PLS_CH0 31
#define LEDC_EVT_OVF_CNT_PLS_CH1 32
#define LEDC_EVT_OVF_CNT_PLS_CH2 33
#define LEDC_EVT_OVF_CNT_PLS_CH3 34
#define LEDC_EVT_OVF_CNT_PLS_CH4 35
#define LEDC_EVT_OVF_CNT_PLS_CH5 36
#define LEDC_EVT_TIME_OVF_TIMER0 37
#define LEDC_EVT_TIME_OVF_TIMER1 38
#define LEDC_EVT_TIME_OVF_TIMER2 39
#define LEDC_EVT_TIME_OVF_TIMER3 40
#define LEDC_EVT_TIMER0_CMP 41
#define LEDC_EVT_TIMER1_CMP 42
#define LEDC_EVT_TIMER2_CMP 43
#define LEDC_EVT_TIMER3_CMP 44
#define PCNT_EVT_CNT_EQ_THRESH 45
#define PCNT_EVT_CNT_EQ_LMT 46
#define PCNT_EVT_CNT_EQ_ZERO 47
#define TIMER0_EVT_CNT_CMP_TIMER0 48
#define TIMER1_EVT_CNT_CMP_TIMER0 49
#define SYSTIMER_EVT_CNT_CMP0 50
#define SYSTIMER_EVT_CNT_CMP1 51
#define SYSTIMER_EVT_CNT_CMP2 52
#define RMT_EVT_TX_END 53
#define RMT_EVT_TX_LOOP 54
#define RMT_EVT_RX_END 55
#define RMT_EVT_TX_THRESH 56
#define RMT_EVT_RX_THRESH 57
#define MCPWM_EVT_TIMER0_STOP 58
#define MCPWM_EVT_TIMER1_STOP 59
#define MCPWM_EVT_TIMER2_STOP 60
#define MCPWM_EVT_TIMER0_TEZ 61
#define MCPWM_EVT_TIMER1_TEZ 62
#define MCPWM_EVT_TIMER2_TEZ 63
#define MCPWM_EVT_TIMER0_TEP 64
#define MCPWM_EVT_TIMER1_TEP 65
#define MCPWM_EVT_TIMER2_TEP 66
#define MCPWM_EVT_OP0_TEA 67
#define MCPWM_EVT_OP1_TEA 68
#define MCPWM_EVT_OP2_TEA 69
#define MCPWM_EVT_OP0_TEB 70
#define MCPWM_EVT_OP1_TEB 71
#define MCPWM_EVT_OP2_TEB 72
#define MCPWM_EVT_F0 73
#define MCPWM_EVT_F1 74
#define MCPWM_EVT_F2 75
#define MCPWM_EVT_F0_CLR 76
#define MCPWM_EVT_F1_CLR 77
#define MCPWM_EVT_F2_CLR 78
#define MCPWM_EVT_TZ0_CBC 79
#define MCPWM_EVT_TZ1_CBC 80
#define MCPWM_EVT_TZ2_CBC 81
#define MCPWM_EVT_TZ0_OST 82
#define MCPWM_EVT_TZ1_OST 83
#define MCPWM_EVT_TZ2_OST 84
#define MCPWM_EVT_CAP0 85
#define MCPWM_EVT_CAP1 86
#define MCPWM_EVT_CAP2 87
#define ADC_EVT_CONV_CMPLT0 88
#define ADC_EVT_EQ_ABOVE_THRESH0 89
#define ADC_EVT_EQ_ABOVE_THRESH1 90
#define ADC_EVT_EQ_BELOW_THRESH0 91
#define ADC_EVT_EQ_BELOW_THRESH1 92
#define ADC_EVT_RESULT_DONE0 93
#define ADC_EVT_STOPPED0 94
#define ADC_EVT_STARTED0 95
#define REGDMA_EVT_DONE0 96
#define REGDMA_EVT_DONE1 97
#define REGDMA_EVT_DONE2 98
#define REGDMA_EVT_DONE3 99
#define REGDMA_EVT_ERR0 100
#define REGDMA_EVT_ERR1 101
#define REGDMA_EVT_ERR2 102
#define REGDMA_EVT_ERR3 103
#define PDMA_EVT_TX_DONE 104
#define PDMA_EVT_OUT_EOF 105
#define PDMA_EVT_IN_SUC_EOF 106
#define PDMA_EVT_FULL_OR_EMPTY 107
#define PDMA_EVT_ALL_DONE 108
#define PDMA_EVT_RX_DONE 109
#define TMPSNSR_EVT_OVER_LIMIT 110
#define UART_EVT_REC_DATA_OVF0 111
#define UART_EVT_REC_DATA_OVF1 112
#define UART_EVT_TX_DONE0 113
#define UART_EVT_TX_DONE1 114
#define UART_EVT_TIMEOUT0 115
#define UART_EVT_TIMEOUT1 116
#define UART_EVT_ERR0 117
#define UART_EVT_ERR1 118
#define UART_EVT_CTS0 119
#define UART_EVT_CTS1 120
#define UART_EVT_TX_EMPTY0 121
#define UART_EVT_TX_EMPTY1 122
#define UART_EVT_AT_PATTERNS0 123
#define UART_EVT_AT_PATTERNS1 124
#define SPI_EVT_STOPPED 125
#define I2S_EVT_RX_DONE 126
#define I2S_EVT_TX_DONE 127
#define I2S_EVT_X_WORDS_RECEIVED 128
#define I2S_EVT_X_WORDS_SENT 129
#define I2C_EVT_TRANS_DONE 130
#define LCDCAM_EVT_TRANS_DONE 131
#define CAN_EVT_TRANS_DONE 132
#define ULP_EVT_ERR_INTR 133
#define ULP_EVT_START_INTR 134
#define RTC_EVT_TICK 135
#define RTC_EVT_OVF 136
#define RTC_EVT_CMP 137
#define GDMA_EVT_IN_DONE_CH0 138
#define GDMA_EVT_IN_DONE_CH1 139
#define GDMA_EVT_IN_DONE_CH2 140
#define GDMA_EVT_IN_SUC_EOF_CH0 141
#define GDMA_EVT_IN_SUC_EOF_CH1 142
#define GDMA_EVT_IN_SUC_EOF_CH2 143
#define GDMA_EVT_IN_FIFO_EMPTY_CH0 144
#define GDMA_EVT_IN_FIFO_EMPTY_CH1 145
#define GDMA_EVT_IN_FIFO_EMPTY_CH2 146
#define GDMA_EVT_IN_FIFO_FULL_CH0 147
#define GDMA_EVT_IN_FIFO_FULL_CH1 148
#define GDMA_EVT_IN_FIFO_FULL_CH2 149
#define GDMA_EVT_OUT_DONE_CH0 150
#define GDMA_EVT_OUT_DONE_CH1 151
#define GDMA_EVT_OUT_DONE_CH2 152
#define GDMA_EVT_OUT_EOF_CH0 153
#define GDMA_EVT_OUT_EOF_CH1 154
#define GDMA_EVT_OUT_EOF_CH2 155
#define GDMA_EVT_OUT_TOTAL_EOF_CH0 156
#define GDMA_EVT_OUT_TOTAL_EOF_CH1 157
#define GDMA_EVT_OUT_TOTAL_EOF_CH2 158
#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 159
#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 160
#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 161
#define GDMA_EVT_OUT_FIFO_FULL_CH0 162
#define GDMA_EVT_OUT_FIFO_FULL_CH1 163
#define GDMA_EVT_OUT_FIFO_FULL_CH2 164
#define PMU_EVT_SLEEP_WEEKUP 165
#define GPIO_TASK_CH0_SET 1
#define GPIO_TASK_CH1_SET 2
#define GPIO_TASK_CH2_SET 3
#define GPIO_TASK_CH3_SET 4
#define GPIO_TASK_CH4_SET 5
#define GPIO_TASK_CH5_SET 6
#define GPIO_TASK_CH6_SET 7
#define GPIO_TASK_CH7_SET 8
#define GPIO_TASK_CH0_CLEAR 9
#define GPIO_TASK_CH1_CLEAR 10
#define GPIO_TASK_CH2_CLEAR 11
#define GPIO_TASK_CH3_CLEAR 12
#define GPIO_TASK_CH4_CLEAR 13
#define GPIO_TASK_CH5_CLEAR 14
#define GPIO_TASK_CH6_CLEAR 15
#define GPIO_TASK_CH7_CLEAR 16
#define GPIO_TASK_CH0_TOGGLE 17
#define GPIO_TASK_CH1_TOGGLE 18
#define GPIO_TASK_CH2_TOGGLE 19
#define GPIO_TASK_CH3_TOGGLE 20
#define GPIO_TASK_CH4_TOGGLE 21
#define GPIO_TASK_CH5_TOGGLE 22
#define GPIO_TASK_CH6_TOGGLE 23
#define GPIO_TASK_CH7_TOGGLE 24
#define LEDC_TASK_TIMER0_RES_UPDATE 25
#define LEDC_TASK_TIMER1_RES_UPDATE 26
#define LEDC_TASK_TIMER2_RES_UPDATE 27
#define LEDC_TASK_TIMER3_RES_UPDATE 28
#define LEDC_TASK_RESERVED0 29
#define LEDC_TASK_RESERVED1 30
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 31
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 32
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 33
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 34
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 35
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 36
#define LEDC_TASK_TIMER0_CAP 37
#define LEDC_TASK_TIMER1_CAP 38
#define LEDC_TASK_TIMER2_CAP 39
#define LEDC_TASK_TIMER3_CAP 40
#define LEDC_TASK_SIG_OUT_DIS_CH0 41
#define LEDC_TASK_SIG_OUT_DIS_CH1 42
#define LEDC_TASK_SIG_OUT_DIS_CH2 43
#define LEDC_TASK_SIG_OUT_DIS_CH3 44
#define LEDC_TASK_SIG_OUT_DIS_CH4 45
#define LEDC_TASK_SIG_OUT_DIS_CH5 46
#define LEDC_TASK_OVF_CNT_RST_CH0 47
#define LEDC_TASK_OVF_CNT_RST_CH1 48
#define LEDC_TASK_OVF_CNT_RST_CH2 49
#define LEDC_TASK_OVF_CNT_RST_CH3 50
#define LEDC_TASK_OVF_CNT_RST_CH4 51
#define LEDC_TASK_OVF_CNT_RST_CH5 52
#define LEDC_TASK_TIMER0_RST 53
#define LEDC_TASK_TIMER1_RST 54
#define LEDC_TASK_TIMER2_RST 55
#define LEDC_TASK_TIMER3_RST 56
#define LEDC_TASK_TIMER0_RESUME 57
#define LEDC_TASK_TIMER1_RESUME 58
#define LEDC_TASK_TIMER2_RESUME 59
#define LEDC_TASK_TIMER3_RESUME 60
#define LEDC_TASK_TIMER0_PAUSE 61
#define LEDC_TASK_TIMER1_PAUSE 62
#define LEDC_TASK_TIMER2_PAUSE 63
#define LEDC_TASK_TIMER3_PAUSE 64
#define LEDC_TASK_GAMMA_RESTART_CH0 65
#define LEDC_TASK_GAMMA_RESTART_CH1 66
#define LEDC_TASK_GAMMA_RESTART_CH2 67
#define LEDC_TASK_GAMMA_RESTART_CH3 68
#define LEDC_TASK_GAMMA_RESTART_CH4 69
#define LEDC_TASK_GAMMA_RESTART_CH5 70
#define LEDC_TASK_GAMMA_PAUSE_CH0 71
#define LEDC_TASK_GAMMA_PAUSE_CH1 72
#define LEDC_TASK_GAMMA_PAUSE_CH2 73
#define LEDC_TASK_GAMMA_PAUSE_CH3 74
#define LEDC_TASK_GAMMA_PAUSE_CH4 75
#define LEDC_TASK_GAMMA_PAUSE_CH5 76
#define LEDC_TASK_GAMMA_RESUME_CH0 77
#define LEDC_TASK_GAMMA_RESUME_CH1 78
#define LEDC_TASK_GAMMA_RESUME_CH2 79
#define LEDC_TASK_GAMMA_RESUME_CH3 80
#define LEDC_TASK_GAMMA_RESUME_CH4 81
#define LEDC_TASK_GAMMA_RESUME_CH5 82
#define PCNT_TASK_START 83
#define PCNT_TASK_STOP 84
#define PCNT_TASK_CNT_INC 85
#define PCNT_TASK_CNT_DEC 86
#define PCNT_TASK_CNT_RST 87
#define TIMER0_TASK_CNT_START_TIMER0 88
#define TIMER1_TASK_CNT_START_TIMER0 89
#define TIMER0_TASK_ALARM_START_TIMER0 90
#define TIMER1_TASK_ALARM_START_TIMER0 91
#define TIMER0_TASK_CNT_STOP_TIMER0 92
#define TIMER1_TASK_CNT_STOP_TIMER0 93
#define TIMER0_TASK_CNT_RELOAD_TIMER0 94
#define TIMER1_TASK_CNT_RELOAD_TIMER0 95
#define TIMER0_TASK_CNT_CAP_TIMER0 96
#define TIMER1_TASK_CNT_CAP_TIMER0 97
#define RMT_TASK_TX_START 98
#define RMT_TASK_TX_STOP 99
#define RMT_TASK_RX_DONE 100
#define RMT_TASK_RX_START 101
#define MCPWM_TASK_CMPR0_A_UP 102
#define MCPWM_TASK_CMPR1_A_UP 103
#define MCPWM_TASK_CMPR2_A_UP 104
#define MCPWM_TASK_CMPR0_B_UP 105
#define MCPWM_TASK_CMPR1_B_UP 106
#define MCPWM_TASK_CMPR2_B_UP 107
#define MCPWM_TASK_GEN_STOP 108
#define MCPWM_TASK_TIMER0_SYN 109
#define MCPWM_TASK_TIMER1_SYN 110
#define MCPWM_TASK_TIMER2_SYN 111
#define MCPWM_TASK_TIMER0_PERIOD_UP 112
#define MCPWM_TASK_TIMER1_PERIOD_UP 113
#define MCPWM_TASK_TIMER2_PERIOD_UP 114
#define MCPWM_TASK_TZ0_OST 115
#define MCPWM_TASK_TZ1_OST 116
#define MCPWM_TASK_TZ2_OST 117
#define MCPWM_TASK_CLR0_OST 118
#define MCPWM_TASK_CLR1_OST 119
#define MCPWM_TASK_CLR2_OST 120
#define MCPWM_TASK_CAP0 121
#define MCPWM_TASK_CAP1 122
#define MCPWM_TASK_CAP2 123
#define ADC_TASK_SAMPLE0 124
#define ADC_TASK_SAMPLE1 125
#define ADC_TASK_START0 126
#define ADC_TASK_STOP0 127
#define REGDMA_TASK_START0 128
#define REGDMA_TASK_START1 129
#define REGDMA_TASK_START2 130
#define REGDMA_TASK_START3 131
#define PDMA_TASK_START_TX 132
#define PDMA_TASK_START_RX 133
#define PDMA_TASK_STOP 134
#define TMPSNSR_TASK_START_SAMPLE 135
#define TMPSNSR_TASK_STOP_SAMPLE 136
#define UART_TASK_TX_START0 137
#define UART_TASK_TX_START1 138
#define UART_TASK_TX_STOP0 139
#define UART_TASK_TX_STOP1 140
#define UART_TASK_RX_START0 141
#define UART_TASK_RX_START1 142
#define UART_TASK_RX_STOP0 143
#define UART_TASK_RX_STOP1 144
#define SPI_TASK_TX_START 145
#define SPI_TASK_SLAVE_HD 146
#define SPI_TASK_STOP 147
#define I2S_TASK_START_RX 148
#define I2S_TASK_START_TX 149
#define I2S_TASK_STOP_RX 150
#define I2S_TASK_STOP_TX 151
#define I2C_TASK_START_TRANS 152
#define CAN_TASK_TRANS_START 153
#define ULP_TASK_WAKEUP_CPU 154
#define RTC_TASK_START 155
#define RTC_TASK_STOP 156
#define RTC_TASK_CLR 157
#define RTC_TASK_TRIGGERFLW 158
#define GDMA_TASK_IN_START_CH0 159
#define GDMA_TASK_IN_START_CH1 160
#define GDMA_TASK_IN_START_CH2 161
#define GDMA_TASK_OUT_START_CH0 162
#define GDMA_TASK_OUT_START_CH1 163
#define GDMA_TASK_OUT_START_CH2 164
#define PMU_TASK_SLEEP_REQ 165

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components/soc/esp32c6/include/soc/soc_etm_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of ch_ena_ad0 register
* channel enable register
*/
typedef union {
struct {
/** ch_ena0 : R/WTC/WTS; bitpos: [0]; default: 0;
* ch0 enable
*/
uint32_t ch_ena0:1;
/** ch_ena1 : R/WTC/WTS; bitpos: [1]; default: 0;
* ch1 enable
*/
uint32_t ch_ena1:1;
/** ch_ena2 : R/WTC/WTS; bitpos: [2]; default: 0;
* ch2 enable
*/
uint32_t ch_ena2:1;
/** ch_ena3 : R/WTC/WTS; bitpos: [3]; default: 0;
* ch3 enable
*/
uint32_t ch_ena3:1;
/** ch_ena4 : R/WTC/WTS; bitpos: [4]; default: 0;
* ch4 enable
*/
uint32_t ch_ena4:1;
/** ch_ena5 : R/WTC/WTS; bitpos: [5]; default: 0;
* ch5 enable
*/
uint32_t ch_ena5:1;
/** ch_ena6 : R/WTC/WTS; bitpos: [6]; default: 0;
* ch6 enable
*/
uint32_t ch_ena6:1;
/** ch_ena7 : R/WTC/WTS; bitpos: [7]; default: 0;
* ch7 enable
*/
uint32_t ch_ena7:1;
/** ch_ena8 : R/WTC/WTS; bitpos: [8]; default: 0;
* ch8 enable
*/
uint32_t ch_ena8:1;
/** ch_ena9 : R/WTC/WTS; bitpos: [9]; default: 0;
* ch9 enable
*/
uint32_t ch_ena9:1;
/** ch_ena10 : R/WTC/WTS; bitpos: [10]; default: 0;
* ch10 enable
*/
uint32_t ch_ena10:1;
/** ch_ena11 : R/WTC/WTS; bitpos: [11]; default: 0;
* ch11 enable
*/
uint32_t ch_ena11:1;
/** ch_ena12 : R/WTC/WTS; bitpos: [12]; default: 0;
* ch12 enable
*/
uint32_t ch_ena12:1;
/** ch_ena13 : R/WTC/WTS; bitpos: [13]; default: 0;
* ch13 enable
*/
uint32_t ch_ena13:1;
/** ch_ena14 : R/WTC/WTS; bitpos: [14]; default: 0;
* ch14 enable
*/
uint32_t ch_ena14:1;
/** ch_ena15 : R/WTC/WTS; bitpos: [15]; default: 0;
* ch15 enable
*/
uint32_t ch_ena15:1;
/** ch_ena16 : R/WTC/WTS; bitpos: [16]; default: 0;
* ch16 enable
*/
uint32_t ch_ena16:1;
/** ch_ena17 : R/WTC/WTS; bitpos: [17]; default: 0;
* ch17 enable
*/
uint32_t ch_ena17:1;
/** ch_ena18 : R/WTC/WTS; bitpos: [18]; default: 0;
* ch18 enable
*/
uint32_t ch_ena18:1;
/** ch_ena19 : R/WTC/WTS; bitpos: [19]; default: 0;
* ch19 enable
*/
uint32_t ch_ena19:1;
/** ch_ena20 : R/WTC/WTS; bitpos: [20]; default: 0;
* ch20 enable
*/
uint32_t ch_ena20:1;
/** ch_ena21 : R/WTC/WTS; bitpos: [21]; default: 0;
* ch21 enable
*/
uint32_t ch_ena21:1;
/** ch_ena22 : R/WTC/WTS; bitpos: [22]; default: 0;
* ch22 enable
*/
uint32_t ch_ena22:1;
/** ch_ena23 : R/WTC/WTS; bitpos: [23]; default: 0;
* ch23 enable
*/
uint32_t ch_ena23:1;
/** ch_ena24 : R/WTC/WTS; bitpos: [24]; default: 0;
* ch24 enable
*/
uint32_t ch_ena24:1;
/** ch_ena25 : R/WTC/WTS; bitpos: [25]; default: 0;
* ch25 enable
*/
uint32_t ch_ena25:1;
/** ch_ena26 : R/WTC/WTS; bitpos: [26]; default: 0;
* ch26 enable
*/
uint32_t ch_ena26:1;
/** ch_ena27 : R/WTC/WTS; bitpos: [27]; default: 0;
* ch27 enable
*/
uint32_t ch_ena27:1;
/** ch_ena28 : R/WTC/WTS; bitpos: [28]; default: 0;
* ch28 enable
*/
uint32_t ch_ena28:1;
/** ch_ena29 : R/WTC/WTS; bitpos: [29]; default: 0;
* ch29 enable
*/
uint32_t ch_ena29:1;
/** ch_ena30 : R/WTC/WTS; bitpos: [30]; default: 0;
* ch30 enable
*/
uint32_t ch_ena30:1;
/** ch_ena31 : R/WTC/WTS; bitpos: [31]; default: 0;
* ch31 enable
*/
uint32_t ch_ena31:1;
};
uint32_t val;
} soc_etm_ch_ena_ad0_reg_t;
/** Type of ch_ena_ad0_set register
* channel enable set register
*/
typedef union {
struct {
/** ch_set0 : WT; bitpos: [0]; default: 0;
* ch0 set
*/
uint32_t ch_set0:1;
/** ch_set1 : WT; bitpos: [1]; default: 0;
* ch1 set
*/
uint32_t ch_set1:1;
/** ch_set2 : WT; bitpos: [2]; default: 0;
* ch2 set
*/
uint32_t ch_set2:1;
/** ch_set3 : WT; bitpos: [3]; default: 0;
* ch3 set
*/
uint32_t ch_set3:1;
/** ch_set4 : WT; bitpos: [4]; default: 0;
* ch4 set
*/
uint32_t ch_set4:1;
/** ch_set5 : WT; bitpos: [5]; default: 0;
* ch5 set
*/
uint32_t ch_set5:1;
/** ch_set6 : WT; bitpos: [6]; default: 0;
* ch6 set
*/
uint32_t ch_set6:1;
/** ch_set7 : WT; bitpos: [7]; default: 0;
* ch7 set
*/
uint32_t ch_set7:1;
/** ch_set8 : WT; bitpos: [8]; default: 0;
* ch8 set
*/
uint32_t ch_set8:1;
/** ch_set9 : WT; bitpos: [9]; default: 0;
* ch9 set
*/
uint32_t ch_set9:1;
/** ch_set10 : WT; bitpos: [10]; default: 0;
* ch10 set
*/
uint32_t ch_set10:1;
/** ch_set11 : WT; bitpos: [11]; default: 0;
* ch11 set
*/
uint32_t ch_set11:1;
/** ch_set12 : WT; bitpos: [12]; default: 0;
* ch12 set
*/
uint32_t ch_set12:1;
/** ch_set13 : WT; bitpos: [13]; default: 0;
* ch13 set
*/
uint32_t ch_set13:1;
/** ch_set14 : WT; bitpos: [14]; default: 0;
* ch14 set
*/
uint32_t ch_set14:1;
/** ch_set15 : WT; bitpos: [15]; default: 0;
* ch15 set
*/
uint32_t ch_set15:1;
/** ch_set16 : WT; bitpos: [16]; default: 0;
* ch16 set
*/
uint32_t ch_set16:1;
/** ch_set17 : WT; bitpos: [17]; default: 0;
* ch17 set
*/
uint32_t ch_set17:1;
/** ch_set18 : WT; bitpos: [18]; default: 0;
* ch18 set
*/
uint32_t ch_set18:1;
/** ch_set19 : WT; bitpos: [19]; default: 0;
* ch19 set
*/
uint32_t ch_set19:1;
/** ch_set20 : WT; bitpos: [20]; default: 0;
* ch20 set
*/
uint32_t ch_set20:1;
/** ch_set21 : WT; bitpos: [21]; default: 0;
* ch21 set
*/
uint32_t ch_set21:1;
/** ch_set22 : WT; bitpos: [22]; default: 0;
* ch22 set
*/
uint32_t ch_set22:1;
/** ch_set23 : WT; bitpos: [23]; default: 0;
* ch23 set
*/
uint32_t ch_set23:1;
/** ch_set24 : WT; bitpos: [24]; default: 0;
* ch24 set
*/
uint32_t ch_set24:1;
/** ch_set25 : WT; bitpos: [25]; default: 0;
* ch25 set
*/
uint32_t ch_set25:1;
/** ch_set26 : WT; bitpos: [26]; default: 0;
* ch26 set
*/
uint32_t ch_set26:1;
/** ch_set27 : WT; bitpos: [27]; default: 0;
* ch27 set
*/
uint32_t ch_set27:1;
/** ch_set28 : WT; bitpos: [28]; default: 0;
* ch28 set
*/
uint32_t ch_set28:1;
/** ch_set29 : WT; bitpos: [29]; default: 0;
* ch29 set
*/
uint32_t ch_set29:1;
/** ch_set30 : WT; bitpos: [30]; default: 0;
* ch30 set
*/
uint32_t ch_set30:1;
/** ch_set31 : WT; bitpos: [31]; default: 0;
* ch31 set
*/
uint32_t ch_set31:1;
};
uint32_t val;
} soc_etm_ch_ena_ad0_set_reg_t;
/** Type of ch_ena_ad0_clr register
* channel enable clear register
*/
typedef union {
struct {
/** ch_clr0 : WT; bitpos: [0]; default: 0;
* ch0 clear
*/
uint32_t ch_clr0:1;
/** ch_clr1 : WT; bitpos: [1]; default: 0;
* ch1 clear
*/
uint32_t ch_clr1:1;
/** ch_clr2 : WT; bitpos: [2]; default: 0;
* ch2 clear
*/
uint32_t ch_clr2:1;
/** ch_clr3 : WT; bitpos: [3]; default: 0;
* ch3 clear
*/
uint32_t ch_clr3:1;
/** ch_clr4 : WT; bitpos: [4]; default: 0;
* ch4 clear
*/
uint32_t ch_clr4:1;
/** ch_clr5 : WT; bitpos: [5]; default: 0;
* ch5 clear
*/
uint32_t ch_clr5:1;
/** ch_clr6 : WT; bitpos: [6]; default: 0;
* ch6 clear
*/
uint32_t ch_clr6:1;
/** ch_clr7 : WT; bitpos: [7]; default: 0;
* ch7 clear
*/
uint32_t ch_clr7:1;
/** ch_clr8 : WT; bitpos: [8]; default: 0;
* ch8 clear
*/
uint32_t ch_clr8:1;
/** ch_clr9 : WT; bitpos: [9]; default: 0;
* ch9 clear
*/
uint32_t ch_clr9:1;
/** ch_clr10 : WT; bitpos: [10]; default: 0;
* ch10 clear
*/
uint32_t ch_clr10:1;
/** ch_clr11 : WT; bitpos: [11]; default: 0;
* ch11 clear
*/
uint32_t ch_clr11:1;
/** ch_clr12 : WT; bitpos: [12]; default: 0;
* ch12 clear
*/
uint32_t ch_clr12:1;
/** ch_clr13 : WT; bitpos: [13]; default: 0;
* ch13 clear
*/
uint32_t ch_clr13:1;
/** ch_clr14 : WT; bitpos: [14]; default: 0;
* ch14 clear
*/
uint32_t ch_clr14:1;
/** ch_clr15 : WT; bitpos: [15]; default: 0;
* ch15 clear
*/
uint32_t ch_clr15:1;
/** ch_clr16 : WT; bitpos: [16]; default: 0;
* ch16 clear
*/
uint32_t ch_clr16:1;
/** ch_clr17 : WT; bitpos: [17]; default: 0;
* ch17 clear
*/
uint32_t ch_clr17:1;
/** ch_clr18 : WT; bitpos: [18]; default: 0;
* ch18 clear
*/
uint32_t ch_clr18:1;
/** ch_clr19 : WT; bitpos: [19]; default: 0;
* ch19 clear
*/
uint32_t ch_clr19:1;
/** ch_clr20 : WT; bitpos: [20]; default: 0;
* ch20 clear
*/
uint32_t ch_clr20:1;
/** ch_clr21 : WT; bitpos: [21]; default: 0;
* ch21 clear
*/
uint32_t ch_clr21:1;
/** ch_clr22 : WT; bitpos: [22]; default: 0;
* ch22 clear
*/
uint32_t ch_clr22:1;
/** ch_clr23 : WT; bitpos: [23]; default: 0;
* ch23 clear
*/
uint32_t ch_clr23:1;
/** ch_clr24 : WT; bitpos: [24]; default: 0;
* ch24 clear
*/
uint32_t ch_clr24:1;
/** ch_clr25 : WT; bitpos: [25]; default: 0;
* ch25 clear
*/
uint32_t ch_clr25:1;
/** ch_clr26 : WT; bitpos: [26]; default: 0;
* ch26 clear
*/
uint32_t ch_clr26:1;
/** ch_clr27 : WT; bitpos: [27]; default: 0;
* ch27 clear
*/
uint32_t ch_clr27:1;
/** ch_clr28 : WT; bitpos: [28]; default: 0;
* ch28 clear
*/
uint32_t ch_clr28:1;
/** ch_clr29 : WT; bitpos: [29]; default: 0;
* ch29 clear
*/
uint32_t ch_clr29:1;
/** ch_clr30 : WT; bitpos: [30]; default: 0;
* ch30 clear
*/
uint32_t ch_clr30:1;
/** ch_clr31 : WT; bitpos: [31]; default: 0;
* ch31 clear
*/
uint32_t ch_clr31:1;
};
uint32_t val;
} soc_etm_ch_ena_ad0_clr_reg_t;
/** Type of ch_ena_ad1 register
* channel enable register
*/
typedef union {
struct {
/** ch_ena32 : R/WTC/WTS; bitpos: [0]; default: 0;
* ch32 enable
*/
uint32_t ch_ena32:1;
/** ch_ena33 : R/WTC/WTS; bitpos: [1]; default: 0;
* ch33 enable
*/
uint32_t ch_ena33:1;
/** ch_ena34 : R/WTC/WTS; bitpos: [2]; default: 0;
* ch34 enable
*/
uint32_t ch_ena34:1;
/** ch_ena35 : R/WTC/WTS; bitpos: [3]; default: 0;
* ch35 enable
*/
uint32_t ch_ena35:1;
/** ch_ena36 : R/WTC/WTS; bitpos: [4]; default: 0;
* ch36 enable
*/
uint32_t ch_ena36:1;
/** ch_ena37 : R/WTC/WTS; bitpos: [5]; default: 0;
* ch37 enable
*/
uint32_t ch_ena37:1;
/** ch_ena38 : R/WTC/WTS; bitpos: [6]; default: 0;
* ch38 enable
*/
uint32_t ch_ena38:1;
/** ch_ena39 : R/WTC/WTS; bitpos: [7]; default: 0;
* ch39 enable
*/
uint32_t ch_ena39:1;
/** ch_ena40 : R/WTC/WTS; bitpos: [8]; default: 0;
* ch40 enable
*/
uint32_t ch_ena40:1;
/** ch_ena41 : R/WTC/WTS; bitpos: [9]; default: 0;
* ch41 enable
*/
uint32_t ch_ena41:1;
/** ch_ena42 : R/WTC/WTS; bitpos: [10]; default: 0;
* ch42 enable
*/
uint32_t ch_ena42:1;
/** ch_ena43 : R/WTC/WTS; bitpos: [11]; default: 0;
* ch43 enable
*/
uint32_t ch_ena43:1;
/** ch_ena44 : R/WTC/WTS; bitpos: [12]; default: 0;
* ch44 enable
*/
uint32_t ch_ena44:1;
/** ch_ena45 : R/WTC/WTS; bitpos: [13]; default: 0;
* ch45 enable
*/
uint32_t ch_ena45:1;
/** ch_ena46 : R/WTC/WTS; bitpos: [14]; default: 0;
* ch46 enable
*/
uint32_t ch_ena46:1;
/** ch_ena47 : R/WTC/WTS; bitpos: [15]; default: 0;
* ch47 enable
*/
uint32_t ch_ena47:1;
/** ch_ena48 : R/WTC/WTS; bitpos: [16]; default: 0;
* ch48 enable
*/
uint32_t ch_ena48:1;
/** ch_ena49 : R/WTC/WTS; bitpos: [17]; default: 0;
* ch49 enable
*/
uint32_t ch_ena49:1;
uint32_t reserved_18:14;
};
uint32_t val;
} soc_etm_ch_ena_ad1_reg_t;
/** Type of ch_ena_ad1_set register
* channel enable set register
*/
typedef union {
struct {
/** ch_set32 : WT; bitpos: [0]; default: 0;
* ch32 set
*/
uint32_t ch_set32:1;
/** ch_set33 : WT; bitpos: [1]; default: 0;
* ch33 set
*/
uint32_t ch_set33:1;
/** ch_set34 : WT; bitpos: [2]; default: 0;
* ch34 set
*/
uint32_t ch_set34:1;
/** ch_set35 : WT; bitpos: [3]; default: 0;
* ch35 set
*/
uint32_t ch_set35:1;
/** ch_set36 : WT; bitpos: [4]; default: 0;
* ch36 set
*/
uint32_t ch_set36:1;
/** ch_set37 : WT; bitpos: [5]; default: 0;
* ch37 set
*/
uint32_t ch_set37:1;
/** ch_set38 : WT; bitpos: [6]; default: 0;
* ch38 set
*/
uint32_t ch_set38:1;
/** ch_set39 : WT; bitpos: [7]; default: 0;
* ch39 set
*/
uint32_t ch_set39:1;
/** ch_set40 : WT; bitpos: [8]; default: 0;
* ch40 set
*/
uint32_t ch_set40:1;
/** ch_set41 : WT; bitpos: [9]; default: 0;
* ch41 set
*/
uint32_t ch_set41:1;
/** ch_set42 : WT; bitpos: [10]; default: 0;
* ch42 set
*/
uint32_t ch_set42:1;
/** ch_set43 : WT; bitpos: [11]; default: 0;
* ch43 set
*/
uint32_t ch_set43:1;
/** ch_set44 : WT; bitpos: [12]; default: 0;
* ch44 set
*/
uint32_t ch_set44:1;
/** ch_set45 : WT; bitpos: [13]; default: 0;
* ch45 set
*/
uint32_t ch_set45:1;
/** ch_set46 : WT; bitpos: [14]; default: 0;
* ch46 set
*/
uint32_t ch_set46:1;
/** ch_set47 : WT; bitpos: [15]; default: 0;
* ch47 set
*/
uint32_t ch_set47:1;
/** ch_set48 : WT; bitpos: [16]; default: 0;
* ch48 set
*/
uint32_t ch_set48:1;
/** ch_set49 : WT; bitpos: [17]; default: 0;
* ch49 set
*/
uint32_t ch_set49:1;
uint32_t reserved_18:14;
};
uint32_t val;
} soc_etm_ch_ena_ad1_set_reg_t;
/** Type of ch_ena_ad1_clr register
* channel enable clear register
*/
typedef union {
struct {
/** ch_clr32 : WT; bitpos: [0]; default: 0;
* ch32 clear
*/
uint32_t ch_clr32:1;
/** ch_clr33 : WT; bitpos: [1]; default: 0;
* ch33 clear
*/
uint32_t ch_clr33:1;
/** ch_clr34 : WT; bitpos: [2]; default: 0;
* ch34 clear
*/
uint32_t ch_clr34:1;
/** ch_clr35 : WT; bitpos: [3]; default: 0;
* ch35 clear
*/
uint32_t ch_clr35:1;
/** ch_clr36 : WT; bitpos: [4]; default: 0;
* ch36 clear
*/
uint32_t ch_clr36:1;
/** ch_clr37 : WT; bitpos: [5]; default: 0;
* ch37 clear
*/
uint32_t ch_clr37:1;
/** ch_clr38 : WT; bitpos: [6]; default: 0;
* ch38 clear
*/
uint32_t ch_clr38:1;
/** ch_clr39 : WT; bitpos: [7]; default: 0;
* ch39 clear
*/
uint32_t ch_clr39:1;
/** ch_clr40 : WT; bitpos: [8]; default: 0;
* ch40 clear
*/
uint32_t ch_clr40:1;
/** ch_clr41 : WT; bitpos: [9]; default: 0;
* ch41 clear
*/
uint32_t ch_clr41:1;
/** ch_clr42 : WT; bitpos: [10]; default: 0;
* ch42 clear
*/
uint32_t ch_clr42:1;
/** ch_clr43 : WT; bitpos: [11]; default: 0;
* ch43 clear
*/
uint32_t ch_clr43:1;
/** ch_clr44 : WT; bitpos: [12]; default: 0;
* ch44 clear
*/
uint32_t ch_clr44:1;
/** ch_clr45 : WT; bitpos: [13]; default: 0;
* ch45 clear
*/
uint32_t ch_clr45:1;
/** ch_clr46 : WT; bitpos: [14]; default: 0;
* ch46 clear
*/
uint32_t ch_clr46:1;
/** ch_clr47 : WT; bitpos: [15]; default: 0;
* ch47 clear
*/
uint32_t ch_clr47:1;
/** ch_clr48 : WT; bitpos: [16]; default: 0;
* ch48 clear
*/
uint32_t ch_clr48:1;
/** ch_clr49 : WT; bitpos: [17]; default: 0;
* ch49 clear
*/
uint32_t ch_clr49:1;
uint32_t reserved_18:14;
};
uint32_t val;
} soc_etm_ch_ena_ad1_clr_reg_t;
/** Type of chn_evt_id register
* channeln event id register
*/
typedef union {
struct {
/** evt_id : R/W; bitpos: [7:0]; default: 0;
* chn_evt_id
*/
uint32_t evt_id:8;
uint32_t reserved_8:24;
};
uint32_t val;
} soc_etm_chn_evt_id_reg_t;
/** Type of chn_task_id register
* channeln task id register
*/
typedef union {
struct {
/** task_id : R/W; bitpos: [7:0]; default: 0;
* chn_task_id
*/
uint32_t task_id:8;
uint32_t reserved_8:24;
};
uint32_t val;
} soc_etm_chn_task_id_reg_t;
/** Type of clk_en register
* etm clock enable register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* clock enable
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} soc_etm_clk_en_reg_t;
/** Group: Version Register */
/** Type of date register
* etm date register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35664018;
* date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} soc_etm_date_reg_t;
typedef struct soc_etm_dev_t {
volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0;
volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set;
volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr;
volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1;
volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
volatile struct {
soc_etm_chn_evt_id_reg_t evt_id;
soc_etm_chn_task_id_reg_t task_id;
} channel[50];
volatile soc_etm_clk_en_reg_t clk_en;
volatile soc_etm_date_reg_t date;
} soc_etm_dev_t;
extern soc_etm_dev_t SOC_ETM;
#ifndef __cplusplus
_Static_assert(sizeof(soc_etm_dev_t) == 0x1b0, "Invalid size of soc_etm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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