Angus Gratton 420aef1ffe Updates for riscv support
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00
..
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ESP32-S3 component

This directory contains support for the upcoming ESP32-S3 SoC. This code is still work in progress and not intended for public use.

Please follow announcements on espressif.com and esp32.com to be informed about the ESP32-S3 SoC.

This note will be removed once the ESP32-S3 initial support is ready.