esp-idf/components/soc
Konstantin Kondrashov f1d3332eea Merge branch 'bugfix/c3_efuse_fail_bits' into 'master'
soc: Fix efuse fail bits

See merge request espressif/esp-idf!18321
2022-05-31 21:11:30 +08:00
..
esp32 Merge branch 'feature/support_sleep_for_esp32c2' into 'master' 2022-05-30 17:57:18 +08:00
esp32c2 hal(ecp32c2): Adds spi_flash_encrypted_ll 2022-05-31 11:12:21 +00:00
esp32c3 soc: Fix description of efuse fail bits 2022-05-31 11:21:24 +00:00
esp32h2 Merge branch 'feature/final_h2_bluedroid_skc_common' into 'master' 2022-05-30 21:20:52 +08:00
esp32s2 bootloader: Support Flash Encryption for ESP32-C2 2022-05-31 11:12:21 +00:00
esp32s3 bootloader: Support Flash Encryption for ESP32-C2 2022-05-31 11:12:21 +00:00
include/soc esp_hw_support: move soc_memory_types.h helper functions into esp_hw_support 2022-04-08 11:46:10 +08:00
linux/include/soc build-system: include soc_caps defines into kconfig 2021-12-06 12:37:07 +08:00
CMakeLists.txt soc: move peripheral base address into reg_base.h 2022-01-06 21:43:12 +08:00
linker.lf soc: move implementations to esp_hw_support 2020-10-28 22:38:50 +08:00
lldesc.c crypto: initial S3 Beta 3 bringup and testing for SHA/AES/RSA/flash enc 2021-05-18 11:25:41 +08:00
README.md soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00

soc

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware