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https://github.com/espressif/esp-idf.git
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77 lines
2.3 KiB
C
77 lines
2.3 KiB
C
/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** ATOMIC_ADDR_LOCK_REG register
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* hardware lock regsiter
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*/
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#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
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/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
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* read to acquire hardware lock, write to release hardware lock
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*/
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#define ATOMIC_LOCK 0x00000003U
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#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATOMIC_LOCK_S)
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#define ATOMIC_LOCK_V 0x00000003U
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#define ATOMIC_LOCK_S 0
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/** ATOMIC_LR_ADDR_REG register
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* gloable lr address regsiter
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*/
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#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
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/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
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* backup gloable address
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*/
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#define ATOMIC_GLOABLE_LR_ADDR 0xFFFFFFFFU
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#define ATOMIC_GLOABLE_LR_ADDR_M (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S)
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#define ATOMIC_GLOABLE_LR_ADDR_V 0xFFFFFFFFU
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#define ATOMIC_GLOABLE_LR_ADDR_S 0
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/** ATOMIC_LR_VALUE_REG register
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* gloable lr value regsiter
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*/
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#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
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/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
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* backup gloable value
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*/
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#define ATOMIC_GLOABLE_LR_VALUE 0xFFFFFFFFU
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#define ATOMIC_GLOABLE_LR_VALUE_M (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S)
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#define ATOMIC_GLOABLE_LR_VALUE_V 0xFFFFFFFFU
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#define ATOMIC_GLOABLE_LR_VALUE_S 0
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/** ATOMIC_LOCK_STATUS_REG register
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* lock status regsiter
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*/
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#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
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/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
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* read hareware lock status for debug
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*/
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#define ATOMIC_LOCK_STATUS 0x00000003U
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#define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
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#define ATOMIC_LOCK_STATUS_V 0x00000003U
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#define ATOMIC_LOCK_STATUS_S 0
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/** ATOMIC_COUNTER_REG register
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* wait counter register
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*/
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#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10)
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/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0;
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* delay counter
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*/
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#define ATOMIC_WAIT_COUNTER 0x0000FFFFU
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#define ATOMIC_WAIT_COUNTER_M (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S)
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#define ATOMIC_WAIT_COUNTER_V 0x0000FFFFU
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#define ATOMIC_WAIT_COUNTER_S 0
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#ifdef __cplusplus
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}
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#endif
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