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5926116644
1. move startup_stack attr from soc_memory_type_desc_t to soc_memory_region_t and remove unused aliased_iram field 2. all of the last level of RAM is retention dma accessible on esp32c3 3. remove esp32c2 and later chips retention dma accessible memory caps 4. allow allocate memory from RTC_RAM with MALLOC_CAP_EXEC cap
153 lines
8.8 KiB
C
153 lines
8.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#include "soc/tracemem_config.h"
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#include "heap_memory_layout.h"
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#include "esp_heap_caps.h"
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/**
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* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
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* Each type of memory map consists of one or more regions in the address space.
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* Each type contains an array of prioritized capabilities.
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* Types with later entries are only taken if earlier ones can't fulfill the memory request.
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*
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* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
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* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
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* - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
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* - Most other malloc caps only fit in one region anyway.
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*
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*/
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/* Index of memory in `soc_memory_types[]` */
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enum {
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SOC_MEMORY_TYPE_DIRAM = 0,
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SOC_MEMORY_TYPE_DRAM = 1,
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SOC_MEMORY_TYPE_IRAM = 2,
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SOC_MEMORY_TYPE_SPIRAM = 3,
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SOC_MEMORY_TYPE_RTCRAM = 4,
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SOC_MEMORY_TYPE_NUM,
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};
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/* COMMON_CAPS is the set of attributes common to all types of memory (except I/D cache data memory) on this chip */
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#define ESP32S3_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
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#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
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#define MALLOC_DIRAM_BASE_CAPS ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_RETENTION
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#define MALLOC_RTCRAM_BASE_CAPS ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL
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#else
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#define MALLOC_DIRAM_BASE_CAPS ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_RETENTION | MALLOC_CAP_EXEC
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#define MALLOC_RTCRAM_BASE_CAPS ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_EXEC
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#endif
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/**
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* Defined the attributes and allocation priority of each memory on the chip,
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* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
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* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
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* in turn to continue matching.
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*/
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const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
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/* Mem Type Name | High Priority Matching | Medium Priorty Matching | Low Priority Matching */
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[SOC_MEMORY_TYPE_DIRAM] = { "RAM", { MALLOC_DIRAM_BASE_CAPS, 0, 0 }},
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[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { 0, ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA, 0 }},
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[SOC_MEMORY_TYPE_IRAM] = { "IRAM", { MALLOC_CAP_EXEC, MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0 }},
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[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, ESP32S3_MEM_COMMON_CAPS, 0 }},
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[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS }},
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};
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const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
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/**
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* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
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*
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* @note Because of requirements in the coalescing code which merges adjacent regions,
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* this list should always be sorted from low to high by start address.
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*
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*/
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/**
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* Register the shared buffer area of the last memory block into the heap during heap initialization
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*/
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#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
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const soc_memory_region_t soc_memory_regions[] = {
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#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB && !defined(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
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{ 0x40374000, 0x4000, SOC_MEMORY_TYPE_IRAM, 0, false}, //Level 1, IRAM
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#endif
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{ 0x3FC88000, 0x8000, SOC_MEMORY_TYPE_DIRAM, 0x40378000, false}, //Level 2, IDRAM, can be used as trace memory
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{ 0x3FC90000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40380000, false}, //Level 3, IDRAM, can be used as trace memory
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{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40390000, false}, //Level 4, IDRAM, can be used as trace memory
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{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403A0000, false}, //Level 5, IDRAM, can be used as trace memory
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{ 0x3FCC0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403B0000, false}, //Level 6, IDRAM, can be used as trace memory
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{ 0x3FCD0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403C0000, false}, //Level 7, IDRAM, can be used as trace memory
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{ 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), SOC_MEMORY_TYPE_DIRAM, 0x403D0000, false}, //Level 8, IDRAM, can be used as trace memory,
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{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_DIRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END), true}, //Level 8, IDRAM, can be used as trace memory, ROM reserved area, recycled by heap allocator in app_main task
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#if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB
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{ 0x3FCF0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0, false}, //Level 9, DRAM, DMA is accessible but retention DMA is inaccessible
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#endif
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#if CONFIG_ESP32S3_DATA_CACHE_16KB
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{ 0x3C000000, 0x4000, SOC_MEMORY_TYPE_DRAM, 0, false}, //Level 10, DRAM, DMA is accessible but retention DMA is inaccessible
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#endif
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#ifdef CONFIG_SPIRAM
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{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available
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#endif
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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{ 0x600fe000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
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#endif
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};
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const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
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extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end; // defined in sections.ld.in
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extern int _rtc_reserved_start, _rtc_reserved_end;
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/**
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* Reserved memory regions.
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* These are removed from the soc_memory_regions array when heaps are created.
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*
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*/
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// Static data region. DRAM used by data+bss and possibly rodata
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
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// ESP32S3 has a big D/IRAM region, the part used by code is reserved
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// The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address
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#define I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
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// .text region in diram. DRAM used by text (shared with IBUS).
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code);
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#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code_2);
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#endif
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#ifdef CONFIG_SPIRAM
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/* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this
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* memory to heap depending on the actual SPIRAM chip size. */
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SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region);
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#endif
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#if CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM > 0
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SOC_RESERVE_MEMORY_REGION(TRACEMEM_BLK0_ADDR, TRACEMEM_BLK0_ADDR + CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM / 2, trace_mem0);
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SOC_RESERVE_MEMORY_REGION(TRACEMEM_BLK1_ADDR, TRACEMEM_BLK1_ADDR + CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM / 2, trace_mem1);
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#endif
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// RTC Fast RAM region
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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#ifdef CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
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SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_noinit_end, rtcram_data);
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#else
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SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_fast_end, rtcram_data);
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#endif
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#endif
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data);
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