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change(heap): fix and clean memory caps defination in memory_layout

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1. move startup_stack attr from soc_memory_type_desc_t to soc_memory_region_t and
   remove unused aliased_iram field
2. all of the last level of RAM is retention dma accessible on esp32c3
3. remove esp32c2 and later chips retention dma accessible memory caps
4. allow allocate memory from RTC_RAM with MALLOC_CAP_EXEC cap
This commit is contained in:
wuzhenghui 2023-09-13 17:37:34 +08:00 committed by BOT
parent 492c819357
commit 5926116644
11 changed files with 287 additions and 319 deletions
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4
components/heap/heap_caps_init.c
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@ -69,7 +69,7 @@ void heap_caps_init(void)
for (size_t i = 1; i < num_regions; i++) {
soc_memory_region_t *a = &regions[i - 1];
soc_memory_region_t *b = &regions[i];
if (b->start == (intptr_t)(a->start + a->size) && b->type == a->type ) {
if (b->start == (intptr_t)(a->start + a->size) && b->type == a->type && b->startup_stack == a->startup_stack ) {
a->type = -1;
b->start = a->start;
b->size += a->size;
@ -102,7 +102,7 @@ void heap_caps_init(void)
heap->start = region->start;
heap->end = region->start + region->size;
MULTI_HEAP_LOCK_INIT(&heap->heap_mux);
if (type->startup_stack) {
if (region->startup_stack) {
/* Will be registered when OS scheduler starts */
heap->heap = NULL;
} else {

27
components/heap/include/heap_memory_layout.h
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@ -1,16 +1,8 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdlib.h>
@ -29,8 +21,6 @@ extern "C" {
typedef struct {
const char *name; ///< Name of this memory type
uint32_t caps[SOC_MEMORY_TYPE_NO_PRIOS]; ///< Capabilities for this memory type (as a prioritised set)
bool aliased_iram; ///< If true, this is data memory that is is also mapped in IRAM
bool startup_stack; ///< If true, memory of this type is used for ROM stack during startup
} soc_memory_type_desc_t;
/* Constant table of tag descriptors for all this SoC's tags */
@ -40,10 +30,11 @@ extern const size_t soc_memory_type_count;
/* Region descriptor holds a description for a particular region of memory on a particular SoC.
*/
typedef struct {
intptr_t start; ///< Start address of the region
intptr_t start; ///< Start address of the region
size_t size; ///< Size of the region in bytes
size_t type; ///< Type of the region (index into soc_memory_types array)
intptr_t iram_address; ///< If non-zero, is equivalent address in IRAM
size_t type; ///< Type of the region (index into soc_memory_types array)
intptr_t iram_address; ///< If non-zero, is equivalent address in IRAM
bool startup_stack; ///< If true, memory of this type is used for ROM stack during startup
} soc_memory_region_t;
extern const soc_memory_region_t soc_memory_regions[];

133
components/heap/port/esp32/memory_layout.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -33,34 +33,29 @@ The prioritised capabilities work roughly like this:
- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
- Most other malloc caps only fit in one region anyway.
*/
enum {
SOC_MEMORY_TYPE_DRAM = 0,
SOC_MEMORY_TYPE_DIRAM = 1,
SOC_MEMORY_TYPE_IRAM = 2,
SOC_MEMORY_TYPE_SPIRAM = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_NUM,
};
const soc_memory_type_desc_t soc_memory_types[] = {
//Type 0: Plain ole D-port RAM
{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false},
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }},
//Type 1: Plain ole D-port RAM which has an alias on the I-port
//(This DRAM is also the region used by ROM during startup)
{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true},
//(This DRAM is also the region used by ROM during startup, and decrease the allocation priority to avoid MALLOC_CAP_EXEC memory running out too soon)
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }},
//Type 2: IRAM
{ "IRAM", { MALLOC_CAP_INTERNAL|MALLOC_IRAM_CAP, 0, 0 }, false, false},
//Type 3-8: PID 2-7 IRAM
{ "PID2IRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID3IRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID4IRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID5IRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID6IRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
{ "PID7IRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, 0, MALLOC_IRAM_CAP }, false, false},
//Type 9-14: PID 2-7 DRAM
{ "PID2DRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID3DRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID4DRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID5DRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID6DRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID7DRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
//Type 15: SPI SRAM data
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
//Type 16: RTC Fast RAM
{ "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false},
[SOC_MEMORY_TYPE_IRAM] = { "IRAM", { MALLOC_CAP_INTERNAL|MALLOC_IRAM_CAP, 0, 0 }},
//Type 3: SPI SRAM data
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}},
//Type 4: RTC Fast RAM
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }},
};
const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
@ -73,53 +68,53 @@ from low to high start address.
*/
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 15, 0}, //SPI SRAM, if available
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available
#endif
{ 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
{ 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
{ 0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- if BT is enabled, used data memory for BT ROM functions.
{ 0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
{ 0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
{ 0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
{ 0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
{ 0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
{ 0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
{ 0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
{ 0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
{ 0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
{ 0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
{ 0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
{ 0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
{ 0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
{ 0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
{ 0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
{ 0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
{ 0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
{ 0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
{ 0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
{ 0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
{ 0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
{ 0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
{ 0x40070000, 0x8000, 2, 0}, //pool 0
{ 0x40078000, 0x8000, 2, 0}, //pool 1
{ 0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
{ 0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
{ 0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
{ 0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
{ 0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
{ 0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
{ 0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
{ 0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
{ 0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
{ 0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
{ 0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
{ 0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
{ 0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
{ 0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
{ 0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
{ 0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
{ 0x3FFAE000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 16 <- used for rom code
{ 0x3FFB0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 15 <- if BT is enabled, used as BT HW shared memory
{ 0x3FFB8000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 14 <- if BT is enabled, used data memory for BT ROM functions.
{ 0x3FFC0000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 0
{ 0x3FFC2000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 1
{ 0x3FFC4000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 2
{ 0x3FFC6000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 3
{ 0x3FFC8000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 4
{ 0x3FFCA000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 5
{ 0x3FFCC000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 6
{ 0x3FFCE000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 7
{ 0x3FFD0000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 8
{ 0x3FFD2000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 9
{ 0x3FFD4000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 10
{ 0x3FFD6000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 11
{ 0x3FFD8000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 12
{ 0x3FFDA000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 13
{ 0x3FFDC000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 14
{ 0x3FFDE000, 0x2000, SOC_MEMORY_TYPE_DRAM, 0, false}, //pool 10-13, mmu page 15
{ 0x3FFE0000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x400BC000,true}, //pool 9 blk 1
{ 0x3FFE4000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x400B8000,true}, //pool 9 blk 0
{ 0x3FFE8000, 0x8000, SOC_MEMORY_TYPE_DIRAM, 0x400B0000,true}, //pool 8 <- can be remapped to ROM, used for MAC dump
{ 0x3FFF0000, 0x8000, SOC_MEMORY_TYPE_DIRAM, 0x400A8000,true}, //pool 7 <- can be used for MAC dump
{ 0x3FFF8000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x400A4000,true}, //pool 6 blk 1 <- can be used as trace memory
{ 0x3FFFC000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x400A0000,true}, //pool 6 blk 0 <- can be used as trace memory
{ 0x40070000, 0x8000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 0
{ 0x40078000, 0x8000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 1
{ 0x40080000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 0
{ 0x40082000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 1
{ 0x40084000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 2
{ 0x40086000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 3
{ 0x40088000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 4
{ 0x4008A000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 5
{ 0x4008C000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 6
{ 0x4008E000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 7
{ 0x40090000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 8
{ 0x40092000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 9
{ 0x40094000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 10
{ 0x40096000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 11
{ 0x40098000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 12
{ 0x4009A000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 13
{ 0x4009C000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 14
{ 0x4009E000, 0x2000, SOC_MEMORY_TYPE_IRAM, 0, false}, //pool 2-5, mmu page 15
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ SOC_RTC_DRAM_LOW, 0x2000, 16, 0}, //RTC Fast Memory
{ SOC_RTC_DRAM_LOW, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //RTC Fast Memory
#endif
};

23
components/heap/port/esp32c2/memory_layout.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -28,20 +28,15 @@
/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_STACK_DRAM = 0,
SOC_MEMORY_TYPE_DIRAM = 1,
SOC_MEMORY_TYPE_RAM = 0,
SOC_MEMORY_TYPE_NUM,
};
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
// Type 1: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
// Type 0: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_RAM] = { "RAM", { MALLOC_CAP_DEFAULT | MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_EXEC, 0, 0 }},
};
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
/**
@ -58,16 +53,14 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
const soc_memory_region_t soc_memory_regions[] = {
{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1
{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //D/IRAM level2
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level3
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)} //D/IRAM level3 (ROM reserved area)
{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40380000, false}, //D/IRAM level1
{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40390000, false}, //D/IRAM level2
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_RAM, 0x403A0000, false}, //D/IRAM level3
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END), true} //D/IRAM level3 (ROM reserved area)
};
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
extern int _data_start, _heap_start, _iram_start, _iram_end;
/**

53
components/heap/port/esp32c3/memory_layout.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -27,35 +27,32 @@
/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_DRAM = 0,
SOC_MEMORY_TYPE_STACK_DRAM = 1,
SOC_MEMORY_TYPE_DIRAM = 2,
SOC_MEMORY_TYPE_STACK_DIRAM = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_RAM = 0,
SOC_MEMORY_TYPE_RETENTION_RAM = 1,
SOC_MEMORY_TYPE_RTCRAM = 2,
SOC_MEMORY_TYPE_NUM,
};
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
// Type 2: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
// Type 3: DIRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
// Type 4: RTCRAM
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
};
/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM
#define ESP32C3_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
#else
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM
#define ESP32C3_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
#endif
/**
* Defined the attributes and allocation priority of each memory on the chip,
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
* in turn to continue matching.
*/
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
/* Mem Type Name | High Priority Matching | Medium Priorty Matching | Low Priority Matching */
[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C3_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0 , 0}},
[SOC_MEMORY_TYPE_RETENTION_RAM] = { "Retention RAM", { MALLOC_CAP_RETENTION, ESP32C3_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0}},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, ESP32C3_MEM_COMMON_CAPS }},
};
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
/**
@ -72,12 +69,12 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
const soc_memory_region_t soc_memory_regions[] = {
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40380000, false}, //D/IRAM level1, can be used as trace memory
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x403A0000, false}, //D/IRAM level2, can be used as trace memory
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_RETENTION_RAM, 0x403C0000, false}, //D/IRAM level3, backup dma accessible, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RETENTION_RAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END), true}, //D/IRAM level3, backup dma accessible, can be used as trace memory (ROM reserved area)
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
{ 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
#endif
};

51
components/heap/port/esp32c6/memory_layout.c
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@ -27,35 +27,30 @@
/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_DRAM = 0,
SOC_MEMORY_TYPE_STACK_DRAM = 1,
SOC_MEMORY_TYPE_DIRAM = 2,
SOC_MEMORY_TYPE_STACK_DIRAM = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_RAM = 0,
SOC_MEMORY_TYPE_RTCRAM = 1,
SOC_MEMORY_TYPE_NUM,
};
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
// Type 2: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
// Type 3: DIRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
// Type 4: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
};
/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM
#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
#else
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM
#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
#endif
/**
* Defined the attributes and allocation priority of each memory on the chip,
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
* in turn to continue matching.
*/
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
/* Mem Type Name High Priority Matching Medium Priorty Matching Low Priority Matching */
[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C6_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32C6_MEM_COMMON_CAPS, 0 }},
};
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
/**
@ -72,13 +67,13 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //D/IRAM level0, can be used as trace memory
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level1, can be used as trace memory
{ 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //D/IRAM level2, can be used as trace memory
{ 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level3, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, APP_USABLE_DRAM_END}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory
{ 0x40840000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level2, can be used as trace memory
{ 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_RAM, 0x40860000, false}, //D/IRAM level3, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0}, //LPRAM
{ 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
#endif
};

53
components/heap/port/esp32h2/memory_layout.c
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@ -25,35 +25,30 @@
*/
/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_DRAM = 0,
SOC_MEMORY_TYPE_STACK_DRAM = 1,
SOC_MEMORY_TYPE_DIRAM = 2,
SOC_MEMORY_TYPE_STACK_DIRAM = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_RAM = 0,
SOC_MEMORY_TYPE_RTCRAM = 1,
SOC_MEMORY_TYPE_NUM,
};
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
// Type 2: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
// Type 3: DIRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
// Type 4: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
};
/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM
#define ESP32H2_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
#else
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM
#define ESP32H2_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
#endif
/**
* Defined the attributes and allocation priority of each memory on the chip,
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
* in turn to continue matching.
*/
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
/* Mem Type Name High Priority Matching Medium Priorty Matching Low Priority Matching */
[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32H2_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32H2_MEM_COMMON_CAPS, 0 }},
};
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
/**
@ -70,14 +65,14 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //D/IRAM level 0
{ 0x40810000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40810000}, //D/IRAM level 1
{ 0x40820000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level 2
{ 0x40830000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40830000}, //D/IRAM level 3
{ 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //D/IRAM level 4
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, APP_USABLE_DRAM_END}, //D/IRAM level 4
{ 0x40800000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level 0
{ 0x40810000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40810000, false}, //D/IRAM level 1
{ 0x40820000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level 2
{ 0x40830000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40830000, false}, //D/IRAM level 3
{ 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level 4
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level 4
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
{ 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
#endif
};

65
components/heap/port/esp32p4/memory_layout.c
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@ -26,41 +26,38 @@
/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_DRAM = 0,
SOC_MEMORY_TYPE_STACK_DRAM = 1,
SOC_MEMORY_TYPE_DIRAM = 2,
SOC_MEMORY_TYPE_STACK_DIRAM = 3,
SOC_MEMORY_TYPE_SPIRAM = 4,
SOC_MEMORY_TYPE_RTCRAM = 5,
SOC_MEMORY_TYPE_TCM = 6,
SOC_MEMORY_TYPE_L2MEM = 0,
SOC_MEMORY_TYPE_SPIRAM = 1,
SOC_MEMORY_TYPE_TCM = 2,
SOC_MEMORY_TYPE_RTCRAM = 3,
SOC_MEMORY_TYPE_NUM,
};
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
// Type 2: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
// Type 3: DIRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
// Type 4: SPI SRAM data
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false},
// Type 5: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
// Type 6: TCM
[SOC_MEMORY_TYPE_TCM] = {"TCM", {MALLOC_CAP_TCM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT}, false, false},
};
/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
#define ESP32P4_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM
#define MALLOC_L2MEM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA
#define MALLOC_RTCRAM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL
#else
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM
#define MALLOC_L2MEM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_EXEC
#define MALLOC_RTCRAM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_EXEC
#endif
/**
* Defined the attributes and allocation priority of each memory on the chip,
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
* in turn to continue matching.
*/
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
/* Mem Type Name | High Priority Matching | Medium Priorty Matching | Low Priority Matching */
[SOC_MEMORY_TYPE_L2MEM] = { "RAM", { MALLOC_L2MEM_BASE_CAPS, 0, 0 }},
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, ESP32P4_MEM_COMMON_CAPS, 0 }},
[SOC_MEMORY_TYPE_TCM] = { "TCM", { MALLOC_CAP_TCM, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS}},
};
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
/**
@ -78,22 +75,22 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_LOW, SOC_EXTRAM_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0}, //PSRAM, if available
{ SOC_EXTRAM_LOW, SOC_EXTRAM_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //PSRAM, if available
#endif
// base 192k is always avaible, even if we config l2 cache size to 512k
{ 0x4ff00000, 0x30000, SOC_MEMORY_TYPE_DEFAULT, 0x4ff00000},
{ 0x4ff00000, 0x30000, SOC_MEMORY_TYPE_L2MEM, 0x4ff00000, false},
// 64k for rom startup stack
{ 0x4ff30000, 0x10000, SOC_MEMORY_TYPE_STACK_DRAM, 0x4ff30000},
{ 0x4ff30000, 0x10000, SOC_MEMORY_TYPE_L2MEM, 0x4ff30000, true},
#if CONFIG_ESP32P4_L2_CACHE_256KB // 768-256 = 512k avaible for l2 memory, add extra 256k
{ 0x4ff40000, 0x40000, SOC_MEMORY_TYPE_DEFAULT, 0x4ff40000},
{ 0x4ff40000, 0x40000, SOC_MEMORY_TYPE_L2MEM, 0x4ff40000, false},
#endif
#if CONFIG_ESP32P4_L2_CACHE_128KB // 768 - 128 = 640k avaible for l2 memory, add extra 384k
{ 0x4ff40000, 0x60000, SOC_MEMORY_TYPE_DEFAULT, 0x4ff40000},
{ 0x4ff40000, 0x60000, SOC_MEMORY_TYPE_L2MEM, 0x4ff40000, false},
#endif
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50108000, 0x8000, SOC_MEMORY_TYPE_RTCRAM, 0}, //LPRAM
{ 0x50108000, 0x8000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
#endif
{ 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0},
{ 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0, false},
};
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);

105
components/heap/port/esp32s2/memory_layout.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -28,31 +28,40 @@ The prioritised capabilities work roughly like this:
- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
- Most other malloc caps only fit in one region anyway.
*/
const soc_memory_type_desc_t soc_memory_types[] = {
//Type 0: DRAM
{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, true},
//Type 2: DRAM which has an alias on the I-port
{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, false},
//Type 3: IRAM
//In ESP32S2, All IRAM region are available by D-port (D/IRAM).
{ "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
//Type 4: SPI SRAM data
//TODO, in fact, part of them support EDMA, to be supported.
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
//Type 5: RTC Fast RAM
{ "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false},
enum {
SOC_MEMORY_TYPE_DIRAM = 0,
SOC_MEMORY_TYPE_SPIRAM = 1,
SOC_MEMORY_TYPE_RTCRAM = 2,
SOC_MEMORY_TYPE_NUM,
};
/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
#define ESP32S2_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define SOC_MEMORY_TYPE_DEFAULT 0
#define MALLOC_DIRAM_BASE_CAPS ESP32S2_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA
#define MALLOC_RTCRAM_BASE_CAPS ESP32S2_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL
#else
#define SOC_MEMORY_TYPE_DEFAULT 2
#define MALLOC_DIRAM_BASE_CAPS ESP32S2_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_EXEC
#define MALLOC_RTCRAM_BASE_CAPS ESP32S2_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_EXEC
#endif
/**
* Defined the attributes and allocation priority of each memory on the chip,
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
* in turn to continue matching.
*/
const soc_memory_type_desc_t soc_memory_types[] = {
/* Mem Type Name | High Priority Matching | Medium Priorty Matching | Low Priority Matching */
[SOC_MEMORY_TYPE_DIRAM] = { "RAM", { MALLOC_DIRAM_BASE_CAPS, 0, 0 }},
//TODO, in fact, part of them support EDMA, to be supported.
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, ESP32S2_MEM_COMMON_CAPS, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS }},
};
const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
/*
@ -63,48 +72,48 @@ from low to high start address.
*/
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available
#endif
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
#if CONFIG_ESP32S2_DATA_CACHE_0KB
{ 0x3FFB2000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40022000}, //Block 1, can be use as I/D cache memory
{ 0x3FFB4000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40024000}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
{ 0x3FFB2000, 0x2000, SOC_MEMORY_TYPE_DIRAM, 0x40022000, false}, //Block 1, can be use as I/D cache memory
{ 0x3FFB4000, 0x2000, SOC_MEMORY_TYPE_DIRAM, 0x40024000, false}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DIRAM, 0x40026000, false}, //Block 3, can be use as D cache memory
#elif CONFIG_ESP32S2_DATA_CACHE_8KB
{ 0x3FFB4000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40024000}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
{ 0x3FFB4000, 0x2000, SOC_MEMORY_TYPE_DIRAM, 0x40024000, false}, //Block 2, can be use as D cache memory
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DIRAM, 0x40026000, false}, //Block 3, can be use as D cache memory
#else
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DIRAM, 0x40026000, false}, //Block 3, can be use as D cache memory
#endif
#else
#if CONFIG_ESP32S2_DATA_CACHE_0KB
{ 0x3FFB4000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40024000}, //Block SOC_MEMORY_TYPE_DEFAULT, can be use as D cache memory
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
{ 0x3FFB4000, 0x2000, SOC_MEMORY_TYPE_DIRAM, 0x40024000, false}, //Block 3, can be use as D cache memory
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DIRAM, 0x40026000, false}, //Block 3, can be use as D cache memory
#elif CONFIG_ESP32S2_DATA_CACHE_8KB
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DEFAULT, 0x40026000}, //Block 3, can be use as D cache memory
{ 0x3FFB6000, 0x2000, SOC_MEMORY_TYPE_DIRAM, 0x40026000, false}, //Block 3, can be use as D cache memory
#endif
#endif
{ 0x3FFB8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory
{ 0x3FFBC000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x4002C000}, //Block 5, can be remapped to ROM, can be used as trace memory
{ 0x3FFC0000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40030000}, //Block 6, can be used as trace memory
{ 0x3FFC4000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40034000}, //Block 7, can be used as trace memory
{ 0x3FFC8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40038000}, //Block 8, can be used as trace memory
{ 0x3FFCC000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x4003C000}, //Block 9, can be used as trace memory
{ 0x3FFB8000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40028000, false}, //Block 4, can be remapped to ROM, can be used as trace memory
{ 0x3FFBC000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x4002C000, false}, //Block 5, can be remapped to ROM, can be used as trace memory
{ 0x3FFC0000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40030000, false}, //Block 6, can be used as trace memory
{ 0x3FFC4000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40034000, false}, //Block 7, can be used as trace memory
{ 0x3FFC8000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40038000, false}, //Block 8, can be used as trace memory
{ 0x3FFCC000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x4003C000, false}, //Block 9, can be used as trace memory
{ 0x3FFD0000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40040000}, //Block 10, can be used as trace memory
{ 0x3FFD4000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40044000}, //Block 11, can be used as trace memory
{ 0x3FFD8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40048000}, //Block 12, can be used as trace memory
{ 0x3FFDC000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x4004C000}, //Block 13, can be used as trace memory
{ 0x3FFE0000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40050000}, //Block 14, can be used as trace memory
{ 0x3FFE4000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40054000}, //Block 15, can be used as trace memory
{ 0x3FFE8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40058000}, //Block 16, can be used as trace memory
{ 0x3FFEC000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x4005C000}, //Block 17, can be used as trace memory
{ 0x3FFF0000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40060000}, //Block 18, can be used for MAC dump, can be used as trace memory
{ 0x3FFF4000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40064000}, //Block 19, can be used for MAC dump, can be used as trace memory
{ 0x3FFF8000, 0x4000, SOC_MEMORY_TYPE_DEFAULT, 0x40068000}, //Block 20, can be used for MAC dump, can be used as trace memory
{ 0x3FFFC000, 0x4000, 1, 0x4006C000}, //Block 21, can be used for MAC dump, can be used as trace memory, used for startup stack
{ 0x3FFD0000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40040000, false}, //Block 10, can be used as trace memory
{ 0x3FFD4000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40044000, false}, //Block 11, can be used as trace memory
{ 0x3FFD8000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40048000, false}, //Block 12, can be used as trace memory
{ 0x3FFDC000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x4004C000, false}, //Block 13, can be used as trace memory
{ 0x3FFE0000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40050000, false}, //Block 14, can be used as trace memory
{ 0x3FFE4000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40054000, false}, //Block 15, can be used as trace memory
{ 0x3FFE8000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40058000, false}, //Block 16, can be used as trace memory
{ 0x3FFEC000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x4005C000, false}, //Block 17, can be used as trace memory
{ 0x3FFF0000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40060000, false}, //Block 18, can be used for MAC dump, can be used as trace memory
{ 0x3FFF4000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40064000, false}, //Block 19, can be used for MAC dump, can be used as trace memory
{ 0x3FFF8000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40068000, false}, //Block 20, can be used for MAC dump, can be used as trace memory
{ 0x3FFFC000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x4006C000, true}, //Block 21, can be used for MAC dump, can be used as trace memory, used for startup stack
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ SOC_RTC_DRAM_LOW, 0x2000, 5, 0}, //RTC Fast Memory
{ SOC_RTC_DRAM_LOW, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //RTC Fast Memory
#endif
};

91
components/heap/port/esp32s3/memory_layout.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -29,44 +29,41 @@
/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_DRAM = 0,
SOC_MEMORY_TYPE_STACK_DRAM = 1,
SOC_MEMORY_TYPE_DIRAM = 2,
SOC_MEMORY_TYPE_STACK_DIRAM = 3,
SOC_MEMORY_TYPE_IRAM = 4,
SOC_MEMORY_TYPE_SPIRAM = 5,
SOC_MEMORY_TYPE_NODMARAM = 6,
SOC_MEMORY_TYPE_RTCRAM = 7,
SOC_MEMORY_TYPE_DIRAM = 0,
SOC_MEMORY_TYPE_DRAM = 1,
SOC_MEMORY_TYPE_IRAM = 2,
SOC_MEMORY_TYPE_SPIRAM = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_NUM,
};
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true},
// Type 2: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC | MALLOC_CAP_RETENTION}, true, false},
// Type 3: DIRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
// Type 4: IRAM
[SOC_MEMORY_TYPE_IRAM] = { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
// Type 5: SPI SRAM data
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false},
// Type 6: DRAM which is not DMA accesible
[SOC_MEMORY_TYPE_NODMARAM] = { "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false},
// Type 7: RTC Fast RAM
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
};
/* COMMON_CAPS is the set of attributes common to all types of memory (except I/D cache data memory) on this chip */
#define ESP32S3_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM
#define MALLOC_DIRAM_BASE_CAPS ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_RETENTION
#define MALLOC_RTCRAM_BASE_CAPS ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL
#else
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM
#define MALLOC_DIRAM_BASE_CAPS ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_RETENTION | MALLOC_CAP_EXEC
#define MALLOC_RTCRAM_BASE_CAPS ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_EXEC
#endif
/**
* Defined the attributes and allocation priority of each memory on the chip,
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
* in turn to continue matching.
*/
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
/* Mem Type Name | High Priority Matching | Medium Priorty Matching | Low Priority Matching */
[SOC_MEMORY_TYPE_DIRAM] = { "RAM", { MALLOC_DIRAM_BASE_CAPS, 0, 0 }},
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { 0, ESP32S3_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA, 0 }},
[SOC_MEMORY_TYPE_IRAM] = { "IRAM", { MALLOC_CAP_EXEC, MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0 }},
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, ESP32S3_MEM_COMMON_CAPS, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS }},
};
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
/**
@ -83,28 +80,28 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0}, //SPI SRAM, if available
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB && !defined(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
{ 0x40374000, 0x4000, SOC_MEMORY_TYPE_IRAM, 0, false}, //Level 1, IRAM
#endif
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB
{ 0x40374000, 0x4000, SOC_MEMORY_TYPE_IRAM, 0}, //Level 1, IRAM
#endif
{ 0x3FC88000, 0x8000, SOC_MEMORY_TYPE_DEFAULT, 0x40378000}, //Level 2, IDRAM, can be used as trace memory
{ 0x3FC90000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Level 3, IDRAM, can be used as trace memory
{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //Level 4, IDRAM, can be used as trace memory
{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Level 5, IDRAM, can be used as trace memory
{ 0x3FCC0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x403B0000}, //Level 6, IDRAM, can be used as trace memory
{ 0x3FCD0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //Level 7, IDRAM, can be used as trace memory
{ 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), SOC_MEMORY_TYPE_DEFAULT, 0x403D0000}, //Level 8, IDRAM, can be used as trace memory,
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memory, ROM reserved area, recycled by heap allocator in app_main task
{ 0x3FC88000, 0x8000, SOC_MEMORY_TYPE_DIRAM, 0x40378000, false}, //Level 2, IDRAM, can be used as trace memory
{ 0x3FC90000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40380000, false}, //Level 3, IDRAM, can be used as trace memory
{ 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40390000, false}, //Level 4, IDRAM, can be used as trace memory
{ 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403A0000, false}, //Level 5, IDRAM, can be used as trace memory
{ 0x3FCC0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403B0000, false}, //Level 6, IDRAM, can be used as trace memory
{ 0x3FCD0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403C0000, false}, //Level 7, IDRAM, can be used as trace memory
{ 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), SOC_MEMORY_TYPE_DIRAM, 0x403D0000, false}, //Level 8, IDRAM, can be used as trace memory,
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_DIRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END), true}, //Level 8, IDRAM, can be used as trace memory, ROM reserved area, recycled by heap allocator in app_main task
#if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB
{ 0x3FCF0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0}, //Level 9, DRAM, DMA is accessible but retention DMA is inaccessible
{ 0x3FCF0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0, false}, //Level 9, DRAM, DMA is accessible but retention DMA is inaccessible
#endif
#if CONFIG_ESP32S3_DATA_CACHE_16KB
{ 0x3C000000, 0x4000, SOC_MEMORY_TYPE_DRAM, 0}, //Level 10, DRAM, DMA is accessible but retention DMA is inaccessible
{ 0x3C000000, 0x4000, SOC_MEMORY_TYPE_DRAM, 0, false}, //Level 10, DRAM, DMA is accessible but retention DMA is inaccessible
#endif
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available
#endif
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x600fe000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory
{ 0x600fe000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
#endif
};

1
tools/ci/check_copyright_ignore.txt
View File

@ -550,7 +550,6 @@ components/hal/include/hal/dac_types.h
components/hal/spi_slave_hal.c
components/hal/spi_slave_hal_iram.c
components/hal/test/test_mpu.c
components/heap/include/heap_memory_layout.h
components/heap/test_multi_heap_host/main.cpp
components/heap/test_multi_heap_host/test_multi_heap.cpp
components/idf_test/include/idf_performance.h