Michael (XIAO Xufeng) a0d13a31ec uart: fix misleading files for UART2 ... Includes: header files, ld files and clk.c ESP32-C3 only have UART0 and UART1.		2021-04-27 17:40:19 +08:00
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esp32/rom	secure boot v2: Fix issue checking multiple signature blocks on OTA update	2021-03-15 12:30:20 +00:00
esp32c3/rom	uart: fix misleading files for UART2	2021-04-27 17:40:19 +08:00
esp32s2/rom	secure_boot: Secure Boot V2 verify app signature on update (without Secure boot)	2021-03-15 12:30:20 +00:00
esp32s3/rom	Support ESP32S3 Beta 3 target	2021-03-18 10:24:22 +08:00
esp_rom_crc.h	esp_rom: extract common CRC apis into esp_rom_crc.h	2020-06-23 16:40:14 +08:00
esp_rom_efuse.h	esp_rom: extract common efuse apis into esp_rom_efuse.h	2020-07-15 10:40:50 +08:00
esp_rom_gpio.h	soc: combine xxx_caps.h into one soc_caps.h	2020-10-17 16:10:15 +08:00
esp_rom_md5.h	esp_rom: extract common MD5 hash apis into esp_rom_md5.h	2020-07-21 17:01:28 +08:00
esp_rom_sys.h	rtc: supported disable rom log temporarily	2021-02-22 20:56:43 +08:00
esp_rom_uart.h	Whitespace: Automated whitespace fixes (large commit)	2020-11-11 07:36:35 +00:00