esp-idf/components/soc
Marius Vikhammer 457ce080ae AES: refactor and add HAL layer
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
2020-12-10 09:04:47 +00:00
..
esp32 AES: refactor and add HAL layer 2020-12-10 09:04:47 +00:00
esp32c3 AES: refactor and add HAL layer 2020-12-10 09:04:47 +00:00
esp32s2 AES: refactor and add HAL layer 2020-12-10 09:04:47 +00:00
esp32s3 AES: refactor and add HAL layer 2020-12-10 09:04:47 +00:00
include/soc AES: refactor and add HAL layer 2020-12-10 09:04:47 +00:00
CMakeLists.txt soc: move implementations to esp_hw_support 2020-10-28 22:38:50 +08:00
component.mk Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
linker.lf soc: move implementations to esp_hw_support 2020-10-28 22:38:50 +08:00
lldesc.c soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00
memory_layout_utils.c esp_rom: Add initial ESP32-C3 support 2020-11-30 11:12:56 +11:00
README.md soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00
soc_include_legacy_warn.c Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00

soc

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware