mirror of
https://github.com/espressif/esp-idf.git
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221 lines
8.1 KiB
C
221 lines
8.1 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** TSENS_CTRL_REG register
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* Tsens configuration.
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*/
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#define TSENS_CTRL_REG (DR_REG_TSENS_BASE + 0x0)
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/** TSENS_OUT : RO; bitpos: [7:0]; default: 0;
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* Temperature sensor data out.
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*/
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#define TSENS_OUT 0x000000FFU
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#define TSENS_OUT_M (TSENS_OUT_V << TSENS_OUT_S)
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#define TSENS_OUT_V 0x000000FFU
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#define TSENS_OUT_S 0
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/** TSENS_READY : RO; bitpos: [8]; default: 0;
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* Indicate temperature sensor out ready.
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*/
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#define TSENS_READY (BIT(8))
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#define TSENS_READY_M (TSENS_READY_V << TSENS_READY_S)
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#define TSENS_READY_V 0x00000001U
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#define TSENS_READY_S 8
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/** TSENS_SAMPLE_EN : R/W; bitpos: [9]; default: 0;
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* Enable sample signal for wakeup module.
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*/
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#define TSENS_SAMPLE_EN (BIT(9))
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#define TSENS_SAMPLE_EN_M (TSENS_SAMPLE_EN_V << TSENS_SAMPLE_EN_S)
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#define TSENS_SAMPLE_EN_V 0x00000001U
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#define TSENS_SAMPLE_EN_S 9
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/** TSENS_WAKEUP_MASK : R/W; bitpos: [10]; default: 1;
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* Wake up signal mask.
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*/
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#define TSENS_WAKEUP_MASK (BIT(10))
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#define TSENS_WAKEUP_MASK_M (TSENS_WAKEUP_MASK_V << TSENS_WAKEUP_MASK_S)
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#define TSENS_WAKEUP_MASK_V 0x00000001U
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#define TSENS_WAKEUP_MASK_S 10
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/** TSENS_INT_EN : R/W; bitpos: [12]; default: 1;
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* Enable temperature sensor to send out interrupt.
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*/
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#define TSENS_INT_EN (BIT(12))
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#define TSENS_INT_EN_M (TSENS_INT_EN_V << TSENS_INT_EN_S)
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#define TSENS_INT_EN_V 0x00000001U
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#define TSENS_INT_EN_S 12
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/** TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
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* Invert temperature sensor data.
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*/
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#define TSENS_IN_INV (BIT(13))
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#define TSENS_IN_INV_M (TSENS_IN_INV_V << TSENS_IN_INV_S)
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#define TSENS_IN_INV_V 0x00000001U
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#define TSENS_IN_INV_S 13
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/** TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
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* Temperature sensor clock divider.
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*/
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#define TSENS_CLK_DIV 0x000000FFU
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#define TSENS_CLK_DIV_M (TSENS_CLK_DIV_V << TSENS_CLK_DIV_S)
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#define TSENS_CLK_DIV_V 0x000000FFU
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#define TSENS_CLK_DIV_S 14
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/** TSENS_POWER_UP : R/W; bitpos: [22]; default: 0;
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* Temperature sensor power up.
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*/
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#define TSENS_POWER_UP (BIT(22))
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#define TSENS_POWER_UP_M (TSENS_POWER_UP_V << TSENS_POWER_UP_S)
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#define TSENS_POWER_UP_V 0x00000001U
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#define TSENS_POWER_UP_S 22
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/** TSENS_POWER_UP_FORCE : R/W; bitpos: [23]; default: 0;
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* 1: dump out & power up controlled by SW, 0: by FSM.
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*/
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#define TSENS_POWER_UP_FORCE (BIT(23))
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#define TSENS_POWER_UP_FORCE_M (TSENS_POWER_UP_FORCE_V << TSENS_POWER_UP_FORCE_S)
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#define TSENS_POWER_UP_FORCE_V 0x00000001U
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#define TSENS_POWER_UP_FORCE_S 23
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/** TSENS_INT_RAW_REG register
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* Tsens interrupt raw registers.
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*/
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#define TSENS_INT_RAW_REG (DR_REG_TSENS_BASE + 0x8)
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/** TSENS_COCPU_TSENS_WAKE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
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* Tsens wakeup interrupt raw.
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*/
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#define TSENS_COCPU_TSENS_WAKE_INT_RAW (BIT(0))
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#define TSENS_COCPU_TSENS_WAKE_INT_RAW_M (TSENS_COCPU_TSENS_WAKE_INT_RAW_V << TSENS_COCPU_TSENS_WAKE_INT_RAW_S)
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#define TSENS_COCPU_TSENS_WAKE_INT_RAW_V 0x00000001U
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#define TSENS_COCPU_TSENS_WAKE_INT_RAW_S 0
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/** TSENS_INT_ST_REG register
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* Tsens interrupt status registers.
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*/
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#define TSENS_INT_ST_REG (DR_REG_TSENS_BASE + 0xc)
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/** TSENS_COCPU_TSENS_WAKE_INT_ST : RO; bitpos: [0]; default: 0;
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* Tsens wakeup interrupt status.
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*/
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#define TSENS_COCPU_TSENS_WAKE_INT_ST (BIT(0))
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#define TSENS_COCPU_TSENS_WAKE_INT_ST_M (TSENS_COCPU_TSENS_WAKE_INT_ST_V << TSENS_COCPU_TSENS_WAKE_INT_ST_S)
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#define TSENS_COCPU_TSENS_WAKE_INT_ST_V 0x00000001U
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#define TSENS_COCPU_TSENS_WAKE_INT_ST_S 0
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/** TSENS_INT_ENA_REG register
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* Tsens interrupt enable registers.
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*/
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#define TSENS_INT_ENA_REG (DR_REG_TSENS_BASE + 0x10)
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/** TSENS_COCPU_TSENS_WAKE_INT_ENA : R/WTC; bitpos: [0]; default: 0;
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* Tsens wakeup interrupt enable.
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*/
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA (BIT(0))
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_M (TSENS_COCPU_TSENS_WAKE_INT_ENA_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_S)
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_V 0x00000001U
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_S 0
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/** TSENS_INT_CLR_REG register
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* Tsens interrupt clear registers.
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*/
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#define TSENS_INT_CLR_REG (DR_REG_TSENS_BASE + 0x14)
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/** TSENS_COCPU_TSENS_WAKE_INT_CLR : WT; bitpos: [0]; default: 0;
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* Tsens wakeup interrupt clear.
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*/
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#define TSENS_COCPU_TSENS_WAKE_INT_CLR (BIT(0))
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#define TSENS_COCPU_TSENS_WAKE_INT_CLR_M (TSENS_COCPU_TSENS_WAKE_INT_CLR_V << TSENS_COCPU_TSENS_WAKE_INT_CLR_S)
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#define TSENS_COCPU_TSENS_WAKE_INT_CLR_V 0x00000001U
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#define TSENS_COCPU_TSENS_WAKE_INT_CLR_S 0
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/** TSENS_CLK_CONF_REG register
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* Tsens regbank configuration registers.
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*/
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#define TSENS_CLK_CONF_REG (DR_REG_TSENS_BASE + 0x18)
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/** TSENS_CLK_EN : R/W; bitpos: [0]; default: 0;
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* Tsens regbank clock gating enable.
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*/
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#define TSENS_CLK_EN (BIT(0))
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#define TSENS_CLK_EN_M (TSENS_CLK_EN_V << TSENS_CLK_EN_S)
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#define TSENS_CLK_EN_V 0x00000001U
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#define TSENS_CLK_EN_S 0
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/** TSENS_INT_ENA_W1TS_REG register
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* Tsens wakeup interrupt enable assert.
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*/
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#define TSENS_INT_ENA_W1TS_REG (DR_REG_TSENS_BASE + 0x1c)
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/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS : WT; bitpos: [0]; default: 0;
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* Write 1 to this field to assert interrupt enable.
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*/
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS (BIT(0))
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_M (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S)
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_V 0x00000001U
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TS_S 0
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/** TSENS_INT_ENA_W1TC_REG register
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* Tsens wakeup interrupt enable deassert.
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*/
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#define TSENS_INT_ENA_W1TC_REG (DR_REG_TSENS_BASE + 0x20)
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/** TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC : WT; bitpos: [0]; default: 0;
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* Write 1 to this field to deassert interrupt enable.
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*/
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC (BIT(0))
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_M (TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V << TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S)
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_V 0x00000001U
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#define TSENS_COCPU_TSENS_WAKE_INT_ENA_W1TC_S 0
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/** TSENS_WAKEUP_CTRL_REG register
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* Tsens wakeup control registers.
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*/
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#define TSENS_WAKEUP_CTRL_REG (DR_REG_TSENS_BASE + 0x24)
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/** TSENS_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
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* Lower threshold.
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*/
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#define TSENS_WAKEUP_TH_LOW 0x000000FFU
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#define TSENS_WAKEUP_TH_LOW_M (TSENS_WAKEUP_TH_LOW_V << TSENS_WAKEUP_TH_LOW_S)
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#define TSENS_WAKEUP_TH_LOW_V 0x000000FFU
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#define TSENS_WAKEUP_TH_LOW_S 0
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/** TSENS_WAKEUP_TH_HIGH : R/W; bitpos: [21:14]; default: 255;
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* Upper threshold.
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*/
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#define TSENS_WAKEUP_TH_HIGH 0x000000FFU
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#define TSENS_WAKEUP_TH_HIGH_M (TSENS_WAKEUP_TH_HIGH_V << TSENS_WAKEUP_TH_HIGH_S)
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#define TSENS_WAKEUP_TH_HIGH_V 0x000000FFU
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#define TSENS_WAKEUP_TH_HIGH_S 14
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/** TSENS_WAKEUP_OVER_UPPER_TH : RO; bitpos: [29]; default: 0;
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* Indicates that this wakeup event arose from exceeding upper threshold.
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*/
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#define TSENS_WAKEUP_OVER_UPPER_TH (BIT(29))
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#define TSENS_WAKEUP_OVER_UPPER_TH_M (TSENS_WAKEUP_OVER_UPPER_TH_V << TSENS_WAKEUP_OVER_UPPER_TH_S)
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#define TSENS_WAKEUP_OVER_UPPER_TH_V 0x00000001U
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#define TSENS_WAKEUP_OVER_UPPER_TH_S 29
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/** TSENS_WAKEUP_EN : R/W; bitpos: [30]; default: 0;
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* Tsens wakeup enable.
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*/
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#define TSENS_WAKEUP_EN (BIT(30))
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#define TSENS_WAKEUP_EN_M (TSENS_WAKEUP_EN_V << TSENS_WAKEUP_EN_S)
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#define TSENS_WAKEUP_EN_V 0x00000001U
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#define TSENS_WAKEUP_EN_S 30
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/** TSENS_WAKEUP_MODE : R/W; bitpos: [31]; default: 0;
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* 0:absolute value comparison mode. 1: relative value comparison mode.
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*/
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#define TSENS_WAKEUP_MODE (BIT(31))
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#define TSENS_WAKEUP_MODE_M (TSENS_WAKEUP_MODE_V << TSENS_WAKEUP_MODE_S)
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#define TSENS_WAKEUP_MODE_V 0x00000001U
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#define TSENS_WAKEUP_MODE_S 31
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/** TSENS_SAMPLE_RATE_REG register
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* Hardware automatic sampling control registers.
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*/
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#define TSENS_SAMPLE_RATE_REG (DR_REG_TSENS_BASE + 0x28)
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/** TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
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* Hardware automatic sampling rate.
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*/
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#define TSENS_SAMPLE_RATE 0x0000FFFFU
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#define TSENS_SAMPLE_RATE_M (TSENS_SAMPLE_RATE_V << TSENS_SAMPLE_RATE_S)
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#define TSENS_SAMPLE_RATE_V 0x0000FFFFU
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#define TSENS_SAMPLE_RATE_S 0
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#ifdef __cplusplus
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}
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#endif
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