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feat(soc): added soc support for esp32p4, part3

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This commit is contained in:
Armando 2023-06-30 11:29:39 +08:00
parent 510e544e16
commit 070040c444
155 changed files with 108048 additions and 3 deletions
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2
components/soc/esp32c6/include/soc/parl_io_struct.h
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@ -14,7 +14,7 @@ extern "C" {
/** Type of rx_cfg0 register
* Parallel RX module configuration register0.
*/
typedef union {
typedef volatile union {
struct {
/** rx_eof_gen_sel : R/W; bitpos: [0]; default: 0;
* Write 0 to select eof generated manchnism by configured data byte length. Write 1

21
components/soc/esp32p4/adc_periph.c Normal file
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@ -0,0 +1,21 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
ADC1_CHANNEL_1_GPIO_NUM,
ADC1_CHANNEL_2_GPIO_NUM,
ADC1_CHANNEL_3_GPIO_NUM,
ADC1_CHANNEL_4_GPIO_NUM,
ADC1_CHANNEL_5_GPIO_NUM,
ADC1_CHANNEL_6_GPIO_NUM,
},
};

25
components/soc/esp32p4/gdma_periph.c Normal file
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@ -0,0 +1,25 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gdma_periph.h"
const gdma_signal_conn_t gdma_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_GDMA_MODULE,
.pairs = {
[0] = {
.rx_irq_id = ETS_DMA2D_IN_CH0_INTR_SOURCE,
.tx_irq_id = ETS_DMA2D_OUT_CH0_INTR_SOURCE,
},
[1] = {
.rx_irq_id = ETS_DMA2D_IN_CH1_INTR_SOURCE,
.tx_irq_id = ETS_DMA2D_OUT_CH1_INTR_SOURCE,
},
}
}
}
};

105
components/soc/esp32p4/gpio_periph.c
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@ -0,0 +1,105 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_periph.h"
const uint32_t GPIO_PIN_MUX_REG[] = {
IO_MUX_GPIO0_REG,
IO_MUX_GPIO1_REG,
IO_MUX_GPIO2_REG,
IO_MUX_GPIO3_REG,
IO_MUX_GPIO4_REG,
IO_MUX_GPIO5_REG,
IO_MUX_GPIO6_REG,
IO_MUX_GPIO7_REG,
IO_MUX_GPIO8_REG,
IO_MUX_GPIO9_REG,
IO_MUX_GPIO10_REG,
IO_MUX_GPIO11_REG,
IO_MUX_GPIO12_REG,
IO_MUX_GPIO13_REG,
IO_MUX_GPIO14_REG,
IO_MUX_GPIO15_REG,
IO_MUX_GPIO16_REG,
IO_MUX_GPIO17_REG,
IO_MUX_GPIO18_REG,
IO_MUX_GPIO19_REG,
IO_MUX_GPIO20_REG,
IO_MUX_GPIO21_REG,
IO_MUX_GPIO22_REG,
IO_MUX_GPIO23_REG,
IO_MUX_GPIO24_REG,
IO_MUX_GPIO25_REG,
IO_MUX_GPIO26_REG,
IO_MUX_GPIO27_REG,
IO_MUX_GPIO28_REG,
IO_MUX_GPIO29_REG,
IO_MUX_GPIO30_REG,
IO_MUX_GPIO31_REG,
IO_MUX_GPIO32_REG,
IO_MUX_GPIO33_REG,
IO_MUX_GPIO34_REG,
IO_MUX_GPIO35_REG,
IO_MUX_GPIO36_REG,
IO_MUX_GPIO37_REG,
IO_MUX_GPIO38_REG,
IO_MUX_GPIO39_REG,
IO_MUX_GPIO40_REG,
IO_MUX_GPIO41_REG,
IO_MUX_GPIO42_REG,
IO_MUX_GPIO43_REG,
IO_MUX_GPIO44_REG,
IO_MUX_GPIO45_REG,
IO_MUX_GPIO46_REG,
IO_MUX_GPIO47_REG,
IO_MUX_GPIO48_REG,
IO_MUX_GPIO49_REG,
IO_MUX_GPIO50_REG,
IO_MUX_GPIO51_REG,
IO_MUX_GPIO52_REG,
IO_MUX_GPIO53_REG,
IO_MUX_GPIO54_REG,
IO_MUX_GPIO55_REG,
IO_MUX_GPIO56_REG,
};
_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
const uint32_t GPIO_HOLD_MASK[] = {
BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG
BIT(1), //GPIO1
BIT(2), //GPIO2
BIT(3), //GPIO3
BIT(4), //GPIO4
BIT(5), //GPIO5
BIT(6), //GPIO6
BIT(7), //GPIO7
BIT(8), //GPIO8
BIT(9), //GPIO9
BIT(10), //GPIO10
BIT(11), //GPIO11
BIT(12), //GPIO12
BIT(13), //GPIO13
BIT(14), //GPIO14
BIT(15), //GPIO15
BIT(16), //GPIO16
BIT(17), //GPIO17
BIT(18), //GPIO18
BIT(19), //GPIO19
BIT(20), //GPIO20
BIT(21), //GPIO21
BIT(22), //GPIO22
BIT(23), //GPIO23
BIT(24), //GPIO24
BIT(25), //GPIO25
BIT(26), //GPIO26
BIT(27), //GPIO27
BIT(28), //GPIO28
BIT(29), //GPIO29
BIT(30), //GPIO30
};
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

22
components/soc/esp32p4/i2c_periph.c Normal file
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@ -0,0 +1,22 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
.module = PERIPH_I2C0_MODULE,
},
};

34
components/soc/esp32p4/i2s_periph.c Normal file
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@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
{
.mck_out_sig = 0,
.m_tx_bck_sig = 0,
.m_rx_bck_sig = 0,
.m_tx_ws_sig = 0,
.m_rx_ws_sig = 0,
.s_tx_bck_sig = 0,
.s_rx_bck_sig = 0,
.s_tx_ws_sig = 0,
.s_rx_ws_sig = 0,
.data_out_sigs[0] = 0,
.data_out_sigs[1] = 0,
.data_in_sig = 0,
.irq = -1,
.module = PERIPH_I2S1_MODULE,
}
};

382
components/soc/esp32p4/include/modem/modem_lpcon_reg.h Normal file
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@ -0,0 +1,382 @@
/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "modem/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
/* MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_EN (BIT(0))
#define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S)
#define MODEM_LPCON_CLK_EN_V 0x00000001U
#define MODEM_LPCON_CLK_EN_S 0
/* MODEM_LPCON_CLK_DEBUG_ENA : R/W; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_DEBUG_ENA (BIT(1))
#define MODEM_LPCON_CLK_DEBUG_ENA_M (MODEM_LPCON_CLK_DEBUG_ENA_V << MODEM_LPCON_CLK_DEBUG_ENA_S)
#define MODEM_LPCON_CLK_DEBUG_ENA_V 0x00000001U
#define MODEM_LPCON_CLK_DEBUG_ENA_S 1
#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S)
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x00000001U
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0
/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S)
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x00000001U
#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1
/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S)
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x00000001U
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2
/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S)
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x00000001U
#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3
/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFFU
#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)
#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0x00000FFFU
#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4
#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S)
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0
/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1))
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S)
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1
/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S)
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2
/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3))
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S)
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3
/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU
#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4
#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc)
/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S)
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x00000001U
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0
/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S)
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x00000001U
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1
/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S)
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x00000001U
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2
/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3))
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S)
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x00000001U
#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3
/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFFU
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0x00000FFFU
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4
#define MODEM_LPCON_I2C_MST_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
/* MODEM_LPCON_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_I2C_MST_SEL_160M (BIT(0))
#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M (MODEM_LPCON_CLK_I2C_MST_SEL_160M_V << MODEM_LPCON_CLK_I2C_MST_SEL_160M_S)
#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V 0x00000001U
#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_S 0
#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003U
#define MODEM_LPCON_CLK_MODEM_32K_SEL_M (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S)
#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x00000003U
#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0
#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0))
#define MODEM_LPCON_CLK_WIFIPWR_EN_M (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S)
#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x00000001U
#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0
/* MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S)
#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_EN_S 1
/* MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S)
#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U
#define MODEM_LPCON_CLK_I2C_MST_EN_S 2
/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_EN_M (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S)
#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x00000001U
#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3
#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c)
/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0))
#define MODEM_LPCON_CLK_WIFIPWR_FO_M (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S)
#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x00000001U
#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0
/* MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_COEX_FO (BIT(1))
#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S)
#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U
#define MODEM_LPCON_CLK_COEX_FO_S 1
/* MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2))
#define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S)
#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U
#define MODEM_LPCON_CLK_I2C_MST_FO_S 2
/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3))
#define MODEM_LPCON_CLK_LP_TIMER_FO_M (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S)
#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x00000001U
#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3
/* MODEM_LPCON_CLK_BCMEM_FO : R/W; bitpos: [4]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_BCMEM_FO (BIT(4))
#define MODEM_LPCON_CLK_BCMEM_FO_M (MODEM_LPCON_CLK_BCMEM_FO_V << MODEM_LPCON_CLK_BCMEM_FO_S)
#define MODEM_LPCON_CLK_BCMEM_FO_V 0x00000001U
#define MODEM_LPCON_CLK_BCMEM_FO_S 4
/* MODEM_LPCON_CLK_I2C_MST_MEM_FO : R/W; bitpos: [5]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_I2C_MST_MEM_FO (BIT(5))
#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_M (MODEM_LPCON_CLK_I2C_MST_MEM_FO_V << MODEM_LPCON_CLK_I2C_MST_MEM_FO_S)
#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_V 0x00000001U
#define MODEM_LPCON_CLK_I2C_MST_MEM_FO_S 5
/* MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO : R/W; bitpos: [6]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO (BIT(6))
#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_M (MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V << MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S)
#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_V 0x00000001U
#define MODEM_LPCON_CLK_CHAN_FREQ_MEM_FO_S 6
/* MODEM_LPCON_CLK_PBUS_MEM_FO : R/W; bitpos: [7]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_PBUS_MEM_FO (BIT(7))
#define MODEM_LPCON_CLK_PBUS_MEM_FO_M (MODEM_LPCON_CLK_PBUS_MEM_FO_V << MODEM_LPCON_CLK_PBUS_MEM_FO_S)
#define MODEM_LPCON_CLK_PBUS_MEM_FO_V 0x00000001U
#define MODEM_LPCON_CLK_PBUS_MEM_FO_S 7
/* MODEM_LPCON_CLK_AGC_MEM_FO : R/W; bitpos: [8]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_AGC_MEM_FO (BIT(8))
#define MODEM_LPCON_CLK_AGC_MEM_FO_M (MODEM_LPCON_CLK_AGC_MEM_FO_V << MODEM_LPCON_CLK_AGC_MEM_FO_S)
#define MODEM_LPCON_CLK_AGC_MEM_FO_V 0x00000001U
#define MODEM_LPCON_CLK_AGC_MEM_FO_S 8
/* MODEM_LPCON_CLK_DC_MEM_FO : R/W; bitpos: [9]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_DC_MEM_FO (BIT(9))
#define MODEM_LPCON_CLK_DC_MEM_FO_M (MODEM_LPCON_CLK_DC_MEM_FO_V << MODEM_LPCON_CLK_DC_MEM_FO_S)
#define MODEM_LPCON_CLK_DC_MEM_FO_V 0x00000001U
#define MODEM_LPCON_CLK_DC_MEM_FO_S 9
#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20)
/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000FU
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0x0000000FU
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16
/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000FU
#define MODEM_LPCON_CLK_COEX_ST_MAP_M (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S)
#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0x0000000FU
#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20
/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000FU
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0x0000000FU
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24
/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */
/*description: */
#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000FU
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S)
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0x0000000FU
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28
#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24)
/* MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_LPCON_RST_WIFIPWR (BIT(0))
#define MODEM_LPCON_RST_WIFIPWR_M (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S)
#define MODEM_LPCON_RST_WIFIPWR_V 0x00000001U
#define MODEM_LPCON_RST_WIFIPWR_S 0
/* MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_LPCON_RST_COEX (BIT(1))
#define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S)
#define MODEM_LPCON_RST_COEX_V 0x00000001U
#define MODEM_LPCON_RST_COEX_S 1
/* MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0; */
/*description: */
#define MODEM_LPCON_RST_I2C_MST (BIT(2))
#define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S)
#define MODEM_LPCON_RST_I2C_MST_V 0x00000001U
#define MODEM_LPCON_RST_I2C_MST_S 2
/* MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0; */
/*description: */
#define MODEM_LPCON_RST_LP_TIMER (BIT(3))
#define MODEM_LPCON_RST_LP_TIMER_M (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S)
#define MODEM_LPCON_RST_LP_TIMER_V 0x00000001U
#define MODEM_LPCON_RST_LP_TIMER_S 3
#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
/* MODEM_LPCON_DC_MEM_FORCE_PU : R/W; bitpos: [0]; default: 1; */
/*description: */
#define MODEM_LPCON_DC_MEM_FORCE_PU (BIT(0))
#define MODEM_LPCON_DC_MEM_FORCE_PU_M (MODEM_LPCON_DC_MEM_FORCE_PU_V << MODEM_LPCON_DC_MEM_FORCE_PU_S)
#define MODEM_LPCON_DC_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_DC_MEM_FORCE_PU_S 0
/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_LPCON_DC_MEM_FORCE_PD (BIT(1))
#define MODEM_LPCON_DC_MEM_FORCE_PD_M (MODEM_LPCON_DC_MEM_FORCE_PD_V << MODEM_LPCON_DC_MEM_FORCE_PD_S)
#define MODEM_LPCON_DC_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_DC_MEM_FORCE_PD_S 1
/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; */
/*description: */
#define MODEM_LPCON_AGC_MEM_FORCE_PU (BIT(2))
#define MODEM_LPCON_AGC_MEM_FORCE_PU_M (MODEM_LPCON_AGC_MEM_FORCE_PU_V << MODEM_LPCON_AGC_MEM_FORCE_PU_S)
#define MODEM_LPCON_AGC_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_AGC_MEM_FORCE_PU_S 2
/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; */
/*description: */
#define MODEM_LPCON_AGC_MEM_FORCE_PD (BIT(3))
#define MODEM_LPCON_AGC_MEM_FORCE_PD_M (MODEM_LPCON_AGC_MEM_FORCE_PD_V << MODEM_LPCON_AGC_MEM_FORCE_PD_S)
#define MODEM_LPCON_AGC_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_AGC_MEM_FORCE_PD_S 3
/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; */
/*description: */
#define MODEM_LPCON_PBUS_MEM_FORCE_PU (BIT(4))
#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M (MODEM_LPCON_PBUS_MEM_FORCE_PU_V << MODEM_LPCON_PBUS_MEM_FORCE_PU_S)
#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S 4
/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; */
/*description: */
#define MODEM_LPCON_PBUS_MEM_FORCE_PD (BIT(5))
#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M (MODEM_LPCON_PBUS_MEM_FORCE_PD_V << MODEM_LPCON_PBUS_MEM_FORCE_PD_S)
#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S 5
/* MODEM_LPCON_BC_MEM_FORCE_PU : R/W; bitpos: [6]; default: 0; */
/*description: */
#define MODEM_LPCON_BC_MEM_FORCE_PU (BIT(6))
#define MODEM_LPCON_BC_MEM_FORCE_PU_M (MODEM_LPCON_BC_MEM_FORCE_PU_V << MODEM_LPCON_BC_MEM_FORCE_PU_S)
#define MODEM_LPCON_BC_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_BC_MEM_FORCE_PU_S 6
/* MODEM_LPCON_BC_MEM_FORCE_PD : R/W; bitpos: [7]; default: 0; */
/*description: */
#define MODEM_LPCON_BC_MEM_FORCE_PD (BIT(7))
#define MODEM_LPCON_BC_MEM_FORCE_PD_M (MODEM_LPCON_BC_MEM_FORCE_PD_V << MODEM_LPCON_BC_MEM_FORCE_PD_S)
#define MODEM_LPCON_BC_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_BC_MEM_FORCE_PD_S 7
/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W; bitpos: [8]; default: 0; */
/*description: */
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU (BIT(8))
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S)
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S 8
/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W; bitpos: [9]; default: 0; */
/*description: */
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD (BIT(9))
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M (MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V << MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S)
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S 9
/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W; bitpos: [10]; default: 0; */
/*description: */
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU (BIT(10))
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S)
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V 0x00000001U
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S 10
/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W; bitpos: [11]; default: 0; */
/*description: */
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD (BIT(11))
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S)
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V 0x00000001U
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S 11
/* MODEM_LPCON_MODEM_PWR_MEM_WP : R/W; bitpos: [14:12]; default: 0; */
/*description: */
#define MODEM_LPCON_MODEM_PWR_MEM_WP 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WP_M (MODEM_LPCON_MODEM_PWR_MEM_WP_V << MODEM_LPCON_MODEM_PWR_MEM_WP_S)
#define MODEM_LPCON_MODEM_PWR_MEM_WP_V 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WP_S 12
/* MODEM_LPCON_MODEM_PWR_MEM_WA : R/W; bitpos: [17:15]; default: 4; */
/*description: */
#define MODEM_LPCON_MODEM_PWR_MEM_WA 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WA_M (MODEM_LPCON_MODEM_PWR_MEM_WA_V << MODEM_LPCON_MODEM_PWR_MEM_WA_S)
#define MODEM_LPCON_MODEM_PWR_MEM_WA_V 0x00000007U
#define MODEM_LPCON_MODEM_PWR_MEM_WA_S 15
/* MODEM_LPCON_MODEM_PWR_MEM_RA : R/W; bitpos: [19:18]; default: 0; */
/*description: */
#define MODEM_LPCON_MODEM_PWR_MEM_RA 0x00000003U
#define MODEM_LPCON_MODEM_PWR_MEM_RA_M (MODEM_LPCON_MODEM_PWR_MEM_RA_V << MODEM_LPCON_MODEM_PWR_MEM_RA_S)
#define MODEM_LPCON_MODEM_PWR_MEM_RA_V 0x00000003U
#define MODEM_LPCON_MODEM_PWR_MEM_RA_S 18
#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x2c)
/* MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 35676736; */
/*description: */
#define MODEM_LPCON_DATE 0x0FFFFFFFU
#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S)
#define MODEM_LPCON_DATE_V 0x0FFFFFFFU
#define MODEM_LPCON_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t clk_en:1;
uint32_t clk_debug_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} modem_lpcon_test_conf_reg_t;
typedef union {
struct {
uint32_t clk_lp_timer_sel_osc_slow:1;
uint32_t clk_lp_timer_sel_osc_fast:1;
uint32_t clk_lp_timer_sel_xtal:1;
uint32_t clk_lp_timer_sel_xtal32k:1;
uint32_t clk_lp_timer_div_num:12;
uint32_t reserved_16:16;
};
uint32_t val;
} modem_lpcon_lp_timer_conf_reg_t;
typedef union {
struct {
uint32_t clk_coex_lp_sel_osc_slow:1;
uint32_t clk_coex_lp_sel_osc_fast:1;
uint32_t clk_coex_lp_sel_xtal:1;
uint32_t clk_coex_lp_sel_xtal32k:1;
uint32_t clk_coex_lp_div_num:12;
uint32_t reserved_16:16;
};
uint32_t val;
} modem_lpcon_coex_lp_clk_conf_reg_t;
typedef union {
struct {
uint32_t clk_wifipwr_lp_sel_osc_slow:1;
uint32_t clk_wifipwr_lp_sel_osc_fast:1;
uint32_t clk_wifipwr_lp_sel_xtal:1;
uint32_t clk_wifipwr_lp_sel_xtal32k:1;
uint32_t clk_wifipwr_lp_div_num:12;
uint32_t reserved_16:16;
};
uint32_t val;
} modem_lpcon_wifi_lp_clk_conf_reg_t;
typedef union {
struct {
uint32_t clk_i2c_mst_sel_160m:1;
uint32_t reserved_1:31;
};
uint32_t val;
} modem_lpcon_i2c_mst_clk_conf_reg_t;
typedef union {
struct {
uint32_t clk_modem_32k_sel:2;
uint32_t reserved_2:30;
};
uint32_t val;
} modem_lpcon_modem_32k_clk_conf_reg_t;
typedef union {
struct {
uint32_t clk_wifipwr_en:1;
uint32_t clk_coex_en:1;
uint32_t clk_i2c_mst_en:1;
uint32_t clk_lp_timer_en:1;
uint32_t reserved_4:28;
};
uint32_t val;
} modem_lpcon_clk_conf_reg_t;
typedef union {
struct {
uint32_t clk_wifipwr_fo:1;
uint32_t clk_coex_fo:1;
uint32_t clk_i2c_mst_fo:1;
uint32_t clk_lp_timer_fo:1;
uint32_t clk_bcmem_fo:1;
uint32_t clk_i2c_mst_mem_fo:1;
uint32_t clk_chan_freq_mem_fo:1;
uint32_t clk_pbus_mem_fo:1;
uint32_t clk_agc_mem_fo:1;
uint32_t clk_dc_mem_fo:1;
uint32_t reserved_10:22;
};
uint32_t val;
} modem_lpcon_clk_conf_force_on_reg_t;
typedef union {
struct {
uint32_t reserved_0:16;
uint32_t clk_wifipwr_st_map:4;
uint32_t clk_coex_st_map:4;
uint32_t clk_i2c_mst_st_map:4;
uint32_t clk_lp_apb_st_map:4;
};
uint32_t val;
} modem_lpcon_clk_conf_power_st_reg_t;
typedef union {
struct {
uint32_t rst_wifipwr:1;
uint32_t rst_coex:1;
uint32_t rst_i2c_mst:1;
uint32_t rst_lp_timer:1;
uint32_t reserved_4:28;
};
uint32_t val;
} modem_lpcon_rst_conf_reg_t;
typedef union {
struct {
uint32_t dc_mem_force_pu:1;
uint32_t dc_mem_force_pd:1;
uint32_t agc_mem_force_pu:1;
uint32_t agc_mem_force_pd:1;
uint32_t pbus_mem_force_pu:1;
uint32_t pbus_mem_force_pd:1;
uint32_t bc_mem_force_pu:1;
uint32_t bc_mem_force_pd:1;
uint32_t i2c_mst_mem_force_pu:1;
uint32_t i2c_mst_mem_force_pd:1;
uint32_t chan_freq_mem_force_pu:1;
uint32_t chan_freq_mem_force_pd:1;
uint32_t modem_pwr_mem_wp:3;
uint32_t modem_pwr_mem_wa:3;
uint32_t modem_pwr_mem_ra:2;
uint32_t reserved_20:12;
};
uint32_t val;
} modem_lpcon_mem_conf_reg_t;
typedef union {
struct {
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} modem_lpcon_date_reg_t;
typedef struct {
volatile modem_lpcon_test_conf_reg_t test_conf;
volatile modem_lpcon_lp_timer_conf_reg_t lp_timer_conf;
volatile modem_lpcon_coex_lp_clk_conf_reg_t coex_lp_clk_conf;
volatile modem_lpcon_wifi_lp_clk_conf_reg_t wifi_lp_clk_conf;
volatile modem_lpcon_i2c_mst_clk_conf_reg_t i2c_mst_clk_conf;
volatile modem_lpcon_modem_32k_clk_conf_reg_t modem_32k_clk_conf;
volatile modem_lpcon_clk_conf_reg_t clk_conf;
volatile modem_lpcon_clk_conf_force_on_reg_t clk_conf_force_on;
volatile modem_lpcon_clk_conf_power_st_reg_t clk_conf_power_st;
volatile modem_lpcon_rst_conf_reg_t rst_conf;
volatile modem_lpcon_mem_conf_reg_t mem_conf;
volatile modem_lpcon_date_reg_t date;
} modem_lpcon_dev_t;
extern modem_lpcon_dev_t MODEM_LPCON;
#ifndef __cplusplus
_Static_assert(sizeof(modem_lpcon_dev_t) == 0x30, "Invalid size of modem_lpcon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*//*description: */
#pragma once
#include <stdint.h>
#include "modem/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0)
/* MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_EN (BIT(0))
#define MODEM_SYSCON_CLK_EN_M (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S)
#define MODEM_SYSCON_CLK_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_EN_S 0
#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4)
/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W; bitpos: [21]; default: 1; */
/*description: */
#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21))
#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (MODEM_SYSCON_CLK_DATA_DUMP_MUX_V << MODEM_SYSCON_CLK_DATA_DUMP_MUX_S)
#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x00000001U
#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21
/* MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [22]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_ETM_EN (BIT(22))
#define MODEM_SYSCON_CLK_ETM_EN_M (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S)
#define MODEM_SYSCON_CLK_ETM_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_ETM_EN_S 22
/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [23]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23))
#define MODEM_SYSCON_CLK_ZB_APB_EN_M (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S)
#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23
/* MODEM_SYSCON_CLK_ZB_MAC_EN : R/W; bitpos: [24]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_ZB_MAC_EN (BIT(24))
#define MODEM_SYSCON_CLK_ZB_MAC_EN_M (MODEM_SYSCON_CLK_ZB_MAC_EN_V << MODEM_SYSCON_CLK_ZB_MAC_EN_S)
#define MODEM_SYSCON_CLK_ZB_MAC_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_ZB_MAC_EN_S 24
/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [25]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25))
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25
/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [26]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26))
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26
/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [27]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27))
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27
/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [28]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28))
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28
/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [29]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29))
#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29
/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S)
#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30
/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S)
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31
#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8)
/* MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [22]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_ETM_FO (BIT(22))
#define MODEM_SYSCON_CLK_ETM_FO_M (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S)
#define MODEM_SYSCON_CLK_ETM_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_ETM_FO_S 22
/* MODEM_SYSCON_CLK_ZB_APB_FO : R/W; bitpos: [23]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_ZB_APB_FO (BIT(23))
#define MODEM_SYSCON_CLK_ZB_APB_FO_M (MODEM_SYSCON_CLK_ZB_APB_FO_V << MODEM_SYSCON_CLK_ZB_APB_FO_S)
#define MODEM_SYSCON_CLK_ZB_APB_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_ZB_APB_FO_S 23
/* MODEM_SYSCON_CLK_ZB_MAC_FO : R/W; bitpos: [24]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_ZB_MAC_FO (BIT(24))
#define MODEM_SYSCON_CLK_ZB_MAC_FO_M (MODEM_SYSCON_CLK_ZB_MAC_FO_V << MODEM_SYSCON_CLK_ZB_MAC_FO_S)
#define MODEM_SYSCON_CLK_ZB_MAC_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_ZB_MAC_FO_S 24
/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO : R/W; bitpos: [25]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO (BIT(25))
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_FO_S 25
/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO : R/W; bitpos: [26]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO (BIT(26))
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_FO_S 26
/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO : R/W; bitpos: [27]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO (BIT(27))
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_FO_S 27
/* MODEM_SYSCON_CLK_MODEM_SEC_APB_FO : R/W; bitpos: [28]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO (BIT(28))
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_APB_FO_S 28
/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29))
#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S)
#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29
/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30))
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S)
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30
/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31))
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S)
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31
#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xc)
/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W; bitpos: [11:8]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000FU
#define MODEM_SYSCON_CLK_ZB_ST_MAP_M (MODEM_SYSCON_CLK_ZB_ST_MAP_V << MODEM_SYSCON_CLK_ZB_ST_MAP_S)
#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0x0000000FU
#define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8
/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W; bitpos: [15:12]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000FU
#define MODEM_SYSCON_CLK_FE_ST_MAP_M (MODEM_SYSCON_CLK_FE_ST_MAP_V << MODEM_SYSCON_CLK_FE_ST_MAP_S)
#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0x0000000FU
#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12
/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W; bitpos: [19:16]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000FU
#define MODEM_SYSCON_CLK_BT_ST_MAP_M (MODEM_SYSCON_CLK_BT_ST_MAP_V << MODEM_SYSCON_CLK_BT_ST_MAP_S)
#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0x0000000FU
#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16
/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W; bitpos: [23:20]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000FU
#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M (MODEM_SYSCON_CLK_WIFI_ST_MAP_V << MODEM_SYSCON_CLK_WIFI_ST_MAP_S)
#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0x0000000FU
#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20
/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W; bitpos: [27:24]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000FU
#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)
#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0x0000000FU
#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24
/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000FU
#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)
#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0x0000000FU
#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28
#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10)
/* MODEM_SYSCON_RST_WIFIBB : R/W; bitpos: [8]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_WIFIBB (BIT(8))
#define MODEM_SYSCON_RST_WIFIBB_M (MODEM_SYSCON_RST_WIFIBB_V << MODEM_SYSCON_RST_WIFIBB_S)
#define MODEM_SYSCON_RST_WIFIBB_V 0x00000001U
#define MODEM_SYSCON_RST_WIFIBB_S 8
/* MODEM_SYSCON_RST_WIFIMAC : R/W; bitpos: [10]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_WIFIMAC (BIT(10))
#define MODEM_SYSCON_RST_WIFIMAC_M (MODEM_SYSCON_RST_WIFIMAC_V << MODEM_SYSCON_RST_WIFIMAC_S)
#define MODEM_SYSCON_RST_WIFIMAC_V 0x00000001U
#define MODEM_SYSCON_RST_WIFIMAC_S 10
/* MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_FE (BIT(14))
#define MODEM_SYSCON_RST_FE_M (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S)
#define MODEM_SYSCON_RST_FE_V 0x00000001U
#define MODEM_SYSCON_RST_FE_S 14
/* MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15))
#define MODEM_SYSCON_RST_BTMAC_APB_M (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S)
#define MODEM_SYSCON_RST_BTMAC_APB_V 0x00000001U
#define MODEM_SYSCON_RST_BTMAC_APB_S 15
/* MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_BTMAC (BIT(16))
#define MODEM_SYSCON_RST_BTMAC_M (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S)
#define MODEM_SYSCON_RST_BTMAC_V 0x00000001U
#define MODEM_SYSCON_RST_BTMAC_S 16
/* MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_BTBB_APB (BIT(17))
#define MODEM_SYSCON_RST_BTBB_APB_M (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S)
#define MODEM_SYSCON_RST_BTBB_APB_V 0x00000001U
#define MODEM_SYSCON_RST_BTBB_APB_S 17
/* MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_BTBB (BIT(18))
#define MODEM_SYSCON_RST_BTBB_M (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S)
#define MODEM_SYSCON_RST_BTBB_V 0x00000001U
#define MODEM_SYSCON_RST_BTBB_S 18
/* MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_ETM (BIT(22))
#define MODEM_SYSCON_RST_ETM_M (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S)
#define MODEM_SYSCON_RST_ETM_V 0x00000001U
#define MODEM_SYSCON_RST_ETM_S 22
/* MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_ZBMAC (BIT(24))
#define MODEM_SYSCON_RST_ZBMAC_M (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S)
#define MODEM_SYSCON_RST_ZBMAC_V 0x00000001U
#define MODEM_SYSCON_RST_ZBMAC_S 24
/* MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25))
#define MODEM_SYSCON_RST_MODEM_ECB_M (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S)
#define MODEM_SYSCON_RST_MODEM_ECB_V 0x00000001U
#define MODEM_SYSCON_RST_MODEM_ECB_S 25
/* MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26))
#define MODEM_SYSCON_RST_MODEM_CCM_M (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S)
#define MODEM_SYSCON_RST_MODEM_CCM_V 0x00000001U
#define MODEM_SYSCON_RST_MODEM_CCM_S 26
/* MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27))
#define MODEM_SYSCON_RST_MODEM_BAH_M (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S)
#define MODEM_SYSCON_RST_MODEM_BAH_V 0x00000001U
#define MODEM_SYSCON_RST_MODEM_BAH_S 27
/* MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29))
#define MODEM_SYSCON_RST_MODEM_SEC_M (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S)
#define MODEM_SYSCON_RST_MODEM_SEC_V 0x00000001U
#define MODEM_SYSCON_RST_MODEM_SEC_S 29
/* MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30))
#define MODEM_SYSCON_RST_BLE_TIMER_M (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S)
#define MODEM_SYSCON_RST_BLE_TIMER_V 0x00000001U
#define MODEM_SYSCON_RST_BLE_TIMER_S 30
/* MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; */
/*description: */
#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31))
#define MODEM_SYSCON_RST_DATA_DUMP_M (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S)
#define MODEM_SYSCON_RST_DATA_DUMP_V 0x00000001U
#define MODEM_SYSCON_RST_DATA_DUMP_S 31
#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14)
/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0))
#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (MODEM_SYSCON_CLK_WIFIBB_22M_EN_V << MODEM_SYSCON_CLK_WIFIBB_22M_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0
/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1))
#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (MODEM_SYSCON_CLK_WIFIBB_40M_EN_V << MODEM_SYSCON_CLK_WIFIBB_40M_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1
/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W; bitpos: [2]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2))
#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (MODEM_SYSCON_CLK_WIFIBB_44M_EN_V << MODEM_SYSCON_CLK_WIFIBB_44M_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2
/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W; bitpos: [3]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3))
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (MODEM_SYSCON_CLK_WIFIBB_80M_EN_V << MODEM_SYSCON_CLK_WIFIBB_80M_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3
/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W; bitpos: [4]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4))
#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4
/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W; bitpos: [5]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5))
#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5
/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W; bitpos: [6]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6))
#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6
/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W; bitpos: [7]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7))
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7
/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W; bitpos: [8]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8))
#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8
/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W; bitpos: [9]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9))
#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (MODEM_SYSCON_CLK_WIFIMAC_EN_V << MODEM_SYSCON_CLK_WIFIMAC_EN_S)
#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9
/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W; bitpos: [10]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10))
#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (MODEM_SYSCON_CLK_WIFI_APB_EN_V << MODEM_SYSCON_CLK_WIFI_APB_EN_S)
#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10
/* MODEM_SYSCON_CLK_FE_20M_EN : R/W; bitpos: [11]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11))
#define MODEM_SYSCON_CLK_FE_20M_EN_M (MODEM_SYSCON_CLK_FE_20M_EN_V << MODEM_SYSCON_CLK_FE_20M_EN_S)
#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_20M_EN_S 11
/* MODEM_SYSCON_CLK_FE_40M_EN : R/W; bitpos: [12]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12))
#define MODEM_SYSCON_CLK_FE_40M_EN_M (MODEM_SYSCON_CLK_FE_40M_EN_V << MODEM_SYSCON_CLK_FE_40M_EN_S)
#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_40M_EN_S 12
/* MODEM_SYSCON_CLK_FE_80M_EN : R/W; bitpos: [13]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13))
#define MODEM_SYSCON_CLK_FE_80M_EN_M (MODEM_SYSCON_CLK_FE_80M_EN_V << MODEM_SYSCON_CLK_FE_80M_EN_S)
#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_80M_EN_S 13
/* MODEM_SYSCON_CLK_FE_160M_EN : R/W; bitpos: [14]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14))
#define MODEM_SYSCON_CLK_FE_160M_EN_M (MODEM_SYSCON_CLK_FE_160M_EN_V << MODEM_SYSCON_CLK_FE_160M_EN_S)
#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_160M_EN_S 14
/* MODEM_SYSCON_CLK_FE_CAL_160M_EN : R/W; bitpos: [15]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_CAL_160M_EN (BIT(15))
#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_M (MODEM_SYSCON_CLK_FE_CAL_160M_EN_V << MODEM_SYSCON_CLK_FE_CAL_160M_EN_S)
#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_CAL_160M_EN_S 15
/* MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [16]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(16))
#define MODEM_SYSCON_CLK_FE_APB_EN_M (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S)
#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_APB_EN_S 16
/* MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [17]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(17))
#define MODEM_SYSCON_CLK_BT_APB_EN_M (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S)
#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_BT_APB_EN_S 17
/* MODEM_SYSCON_CLK_BT_EN : R/W; bitpos: [18]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_BT_EN (BIT(18))
#define MODEM_SYSCON_CLK_BT_EN_M (MODEM_SYSCON_CLK_BT_EN_V << MODEM_SYSCON_CLK_BT_EN_S)
#define MODEM_SYSCON_CLK_BT_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_BT_EN_S 18
/* MODEM_SYSCON_CLK_WIFIBB_480M_EN : R/W; bitpos: [19]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_480M_EN (BIT(19))
#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_M (MODEM_SYSCON_CLK_WIFIBB_480M_EN_V << MODEM_SYSCON_CLK_WIFIBB_480M_EN_S)
#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_480M_EN_S 19
/* MODEM_SYSCON_CLK_FE_480M_EN : R/W; bitpos: [20]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_480M_EN (BIT(20))
#define MODEM_SYSCON_CLK_FE_480M_EN_M (MODEM_SYSCON_CLK_FE_480M_EN_V << MODEM_SYSCON_CLK_FE_480M_EN_S)
#define MODEM_SYSCON_CLK_FE_480M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_480M_EN_S 20
/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN : R/W; bitpos: [21]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN (BIT(21))
#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_M (MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S)
#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_EN_S 21
/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN : R/W; bitpos: [22]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN (BIT(22))
#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_M (MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S)
#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_EN_S 22
/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN : R/W; bitpos: [23]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN (BIT(23))
#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_M (MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S)
#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_EN_S 23
#define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x18)
/* MODEM_SYSCON_CLK_WIFIBB_22M_FO : R/W; bitpos: [0]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_22M_FO (BIT(0))
#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_M (MODEM_SYSCON_CLK_WIFIBB_22M_FO_V << MODEM_SYSCON_CLK_WIFIBB_22M_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_22M_FO_S 0
/* MODEM_SYSCON_CLK_WIFIBB_40M_FO : R/W; bitpos: [1]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_40M_FO (BIT(1))
#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_M (MODEM_SYSCON_CLK_WIFIBB_40M_FO_V << MODEM_SYSCON_CLK_WIFIBB_40M_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_40M_FO_S 1
/* MODEM_SYSCON_CLK_WIFIBB_44M_FO : R/W; bitpos: [2]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_44M_FO (BIT(2))
#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_M (MODEM_SYSCON_CLK_WIFIBB_44M_FO_V << MODEM_SYSCON_CLK_WIFIBB_44M_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_44M_FO_S 2
/* MODEM_SYSCON_CLK_WIFIBB_80M_FO : R/W; bitpos: [3]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_80M_FO (BIT(3))
#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_M (MODEM_SYSCON_CLK_WIFIBB_80M_FO_V << MODEM_SYSCON_CLK_WIFIBB_80M_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_80M_FO_S 3
/* MODEM_SYSCON_CLK_WIFIBB_40X_FO : R/W; bitpos: [4]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_40X_FO (BIT(4))
#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_M (MODEM_SYSCON_CLK_WIFIBB_40X_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_40X_FO_S 4
/* MODEM_SYSCON_CLK_WIFIBB_80X_FO : R/W; bitpos: [5]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_80X_FO (BIT(5))
#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_M (MODEM_SYSCON_CLK_WIFIBB_80X_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_80X_FO_S 5
/* MODEM_SYSCON_CLK_WIFIBB_40X1_FO : R/W; bitpos: [6]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO (BIT(6))
#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_M (MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_40X1_FO_S 6
/* MODEM_SYSCON_CLK_WIFIBB_80X1_FO : R/W; bitpos: [7]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO (BIT(7))
#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_M (MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_80X1_FO_S 7
/* MODEM_SYSCON_CLK_WIFIBB_160X1_FO : R/W; bitpos: [8]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO (BIT(8))
#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_M (MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V << MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_160X1_FO_S 8
/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W; bitpos: [9]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(9))
#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (MODEM_SYSCON_CLK_WIFIMAC_FO_V << MODEM_SYSCON_CLK_WIFIMAC_FO_S)
#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 9
/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W; bitpos: [10]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(10))
#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (MODEM_SYSCON_CLK_WIFI_APB_FO_V << MODEM_SYSCON_CLK_WIFI_APB_FO_S)
#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 10
/* MODEM_SYSCON_CLK_FE_20M_FO : R/W; bitpos: [11]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_20M_FO (BIT(11))
#define MODEM_SYSCON_CLK_FE_20M_FO_M (MODEM_SYSCON_CLK_FE_20M_FO_V << MODEM_SYSCON_CLK_FE_20M_FO_S)
#define MODEM_SYSCON_CLK_FE_20M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_20M_FO_S 11
/* MODEM_SYSCON_CLK_FE_40M_FO : R/W; bitpos: [12]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_40M_FO (BIT(12))
#define MODEM_SYSCON_CLK_FE_40M_FO_M (MODEM_SYSCON_CLK_FE_40M_FO_V << MODEM_SYSCON_CLK_FE_40M_FO_S)
#define MODEM_SYSCON_CLK_FE_40M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_40M_FO_S 12
/* MODEM_SYSCON_CLK_FE_80M_FO : R/W; bitpos: [13]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_80M_FO (BIT(13))
#define MODEM_SYSCON_CLK_FE_80M_FO_M (MODEM_SYSCON_CLK_FE_80M_FO_V << MODEM_SYSCON_CLK_FE_80M_FO_S)
#define MODEM_SYSCON_CLK_FE_80M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_80M_FO_S 13
/* MODEM_SYSCON_CLK_FE_160M_FO : R/W; bitpos: [14]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_160M_FO (BIT(14))
#define MODEM_SYSCON_CLK_FE_160M_FO_M (MODEM_SYSCON_CLK_FE_160M_FO_V << MODEM_SYSCON_CLK_FE_160M_FO_S)
#define MODEM_SYSCON_CLK_FE_160M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_160M_FO_S 14
/* MODEM_SYSCON_CLK_FE_CAL_160M_FO : R/W; bitpos: [15]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_CAL_160M_FO (BIT(15))
#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_M (MODEM_SYSCON_CLK_FE_CAL_160M_FO_V << MODEM_SYSCON_CLK_FE_CAL_160M_FO_S)
#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_CAL_160M_FO_S 15
/* MODEM_SYSCON_CLK_FE_APB_FO : R/W; bitpos: [16]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(16))
#define MODEM_SYSCON_CLK_FE_APB_FO_M (MODEM_SYSCON_CLK_FE_APB_FO_V << MODEM_SYSCON_CLK_FE_APB_FO_S)
#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_APB_FO_S 16
/* MODEM_SYSCON_CLK_BT_APB_FO : R/W; bitpos: [17]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(17))
#define MODEM_SYSCON_CLK_BT_APB_FO_M (MODEM_SYSCON_CLK_BT_APB_FO_V << MODEM_SYSCON_CLK_BT_APB_FO_S)
#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_BT_APB_FO_S 17
/* MODEM_SYSCON_CLK_BT_FO : R/W; bitpos: [18]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_BT_FO (BIT(18))
#define MODEM_SYSCON_CLK_BT_FO_M (MODEM_SYSCON_CLK_BT_FO_V << MODEM_SYSCON_CLK_BT_FO_S)
#define MODEM_SYSCON_CLK_BT_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_BT_FO_S 18
/* MODEM_SYSCON_CLK_WIFIBB_480M_FO : R/W; bitpos: [19]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_WIFIBB_480M_FO (BIT(19))
#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_M (MODEM_SYSCON_CLK_WIFIBB_480M_FO_V << MODEM_SYSCON_CLK_WIFIBB_480M_FO_S)
#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_WIFIBB_480M_FO_S 19
/* MODEM_SYSCON_CLK_FE_480M_FO : R/W; bitpos: [20]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_480M_FO (BIT(20))
#define MODEM_SYSCON_CLK_FE_480M_FO_M (MODEM_SYSCON_CLK_FE_480M_FO_V << MODEM_SYSCON_CLK_FE_480M_FO_S)
#define MODEM_SYSCON_CLK_FE_480M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_480M_FO_S 20
/* MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO : R/W; bitpos: [21]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO (BIT(21))
#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_M (MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S)
#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_ANAMODE_40M_FO_S 21
/* MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO : R/W; bitpos: [22]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO (BIT(22))
#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_M (MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S)
#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_ANAMODE_80M_FO_S 22
/* MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO : R/W; bitpos: [23]; default: 0; */
/*description: */
#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO (BIT(23))
#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_M (MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V << MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S)
#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_V 0x00000001U
#define MODEM_SYSCON_CLK_FE_ANAMODE_160M_FO_S 23
#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c)
/* MODEM_SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; */
/*description: */
#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFFU
#define MODEM_SYSCON_WIFI_BB_CFG_M (MODEM_SYSCON_WIFI_BB_CFG_V << MODEM_SYSCON_WIFI_BB_CFG_S)
#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFFU
#define MODEM_SYSCON_WIFI_BB_CFG_S 0
#define MODEM_SYSCON_MEM_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20)
/* MODEM_SYSCON_MODEM_MEM_WP : R/W; bitpos: [2:0]; default: 0; */
/*description: */
#define MODEM_SYSCON_MODEM_MEM_WP 0x00000007U
#define MODEM_SYSCON_MODEM_MEM_WP_M (MODEM_SYSCON_MODEM_MEM_WP_V << MODEM_SYSCON_MODEM_MEM_WP_S)
#define MODEM_SYSCON_MODEM_MEM_WP_V 0x00000007U
#define MODEM_SYSCON_MODEM_MEM_WP_S 0
/* MODEM_SYSCON_MODEM_MEM_WA : R/W; bitpos: [5:3]; default: 4; */
/*description: */
#define MODEM_SYSCON_MODEM_MEM_WA 0x00000007U
#define MODEM_SYSCON_MODEM_MEM_WA_M (MODEM_SYSCON_MODEM_MEM_WA_V << MODEM_SYSCON_MODEM_MEM_WA_S)
#define MODEM_SYSCON_MODEM_MEM_WA_V 0x00000007U
#define MODEM_SYSCON_MODEM_MEM_WA_S 3
/* MODEM_SYSCON_MODEM_MEM_RA : R/W; bitpos: [7:6]; default: 0; */
/*description: */
#define MODEM_SYSCON_MODEM_MEM_RA 0x00000003U
#define MODEM_SYSCON_MODEM_MEM_RA_M (MODEM_SYSCON_MODEM_MEM_RA_V << MODEM_SYSCON_MODEM_MEM_RA_S)
#define MODEM_SYSCON_MODEM_MEM_RA_V 0x00000003U
#define MODEM_SYSCON_MODEM_MEM_RA_S 6
#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24)
/* MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 35676928; */
/*description: */
#define MODEM_SYSCON_DATE 0x0FFFFFFFU
#define MODEM_SYSCON_DATE_M (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S)
#define MODEM_SYSCON_DATE_V 0x0FFFFFFFU
#define MODEM_SYSCON_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} modem_syscon_test_conf_reg_t;
typedef union {
struct {
uint32_t reserved_0:21;
uint32_t clk_data_dump_mux:1;
uint32_t clk_etm_en:1;
uint32_t clk_zb_apb_en:1;
uint32_t clk_zb_mac_en:1;
uint32_t clk_modem_sec_ecb_en:1;
uint32_t clk_modem_sec_ccm_en:1;
uint32_t clk_modem_sec_bah_en:1;
uint32_t clk_modem_sec_apb_en:1;
uint32_t clk_modem_sec_en:1;
uint32_t clk_ble_timer_en:1;
uint32_t clk_data_dump_en:1;
};
uint32_t val;
} modem_syscon_clk_conf_reg_t;
typedef union {
struct {
uint32_t reserved_0:22;
uint32_t clk_etm_fo:1;
uint32_t clk_zb_apb_fo:1;
uint32_t clk_zb_mac_fo:1;
uint32_t clk_modem_sec_ecb_fo:1;
uint32_t clk_modem_sec_ccm_fo:1;
uint32_t clk_modem_sec_bah_fo:1;
uint32_t clk_modem_sec_apb_fo:1;
uint32_t clk_modem_sec_fo:1;
uint32_t clk_ble_timer_fo:1;
uint32_t clk_data_dump_fo:1;
};
uint32_t val;
} modem_syscon_clk_conf_force_on_reg_t;
typedef union {
struct {
uint32_t reserved_0:8;
uint32_t clk_zb_st_map:4;
uint32_t clk_fe_st_map:4;
uint32_t clk_bt_st_map:4;
uint32_t clk_wifi_st_map:4;
uint32_t clk_modem_peri_st_map:4;
uint32_t clk_modem_apb_st_map:4;
};
uint32_t val;
} modem_syscon_clk_conf_power_st_reg_t;
typedef union {
struct {
uint32_t reserved_0:8;
uint32_t rst_wifibb:1;
uint32_t reserved_9:1;
uint32_t rst_wifimac:1;
uint32_t reserved_11:3;
uint32_t rst_fe:1;
uint32_t rst_btmac_apb:1;
uint32_t rst_btmac:1;
uint32_t rst_btbb_apb:1;
uint32_t rst_btbb:1;
uint32_t reserved_19:3;
uint32_t rst_etm:1;
uint32_t reserved_23:1;
uint32_t rst_zbmac:1;
uint32_t rst_modem_ecb:1;
uint32_t rst_modem_ccm:1;
uint32_t rst_modem_bah:1;
uint32_t reserved_28:1;
uint32_t rst_modem_sec:1;
uint32_t rst_ble_timer:1;
uint32_t rst_data_dump:1;
};
uint32_t val;
} modem_syscon_modem_rst_conf_reg_t;
typedef union {
struct {
uint32_t clk_wifibb_22m_en:1;
uint32_t clk_wifibb_40m_en:1;
uint32_t clk_wifibb_44m_en:1;
uint32_t clk_wifibb_80m_en:1;
uint32_t clk_wifibb_40x_en:1;
uint32_t clk_wifibb_80x_en:1;
uint32_t clk_wifibb_40x1_en:1;
uint32_t clk_wifibb_80x1_en:1;
uint32_t clk_wifibb_160x1_en:1;
uint32_t clk_wifimac_en:1;
uint32_t clk_wifi_apb_en:1;
uint32_t clk_fe_20m_en:1;
uint32_t clk_fe_40m_en:1;
uint32_t clk_fe_80m_en:1;
uint32_t clk_fe_160m_en:1;
uint32_t clk_fe_cal_160m_en:1;
uint32_t clk_fe_apb_en:1;
uint32_t clk_bt_apb_en:1;
uint32_t clk_bt_en:1;
uint32_t clk_wifibb_480m_en:1;
uint32_t clk_fe_480m_en:1;
uint32_t clk_fe_anamode_40m_en:1;
uint32_t clk_fe_anamode_80m_en:1;
uint32_t clk_fe_anamode_160m_en:1;
uint32_t reserved_24:8;
};
uint32_t val;
} modem_syscon_clk_conf1_reg_t;
typedef union {
struct {
uint32_t clk_wifibb_22m_fo:1;
uint32_t clk_wifibb_40m_fo:1;
uint32_t clk_wifibb_44m_fo:1;
uint32_t clk_wifibb_80m_fo:1;
uint32_t clk_wifibb_40x_fo:1;
uint32_t clk_wifibb_80x_fo:1;
uint32_t clk_wifibb_40x1_fo:1;
uint32_t clk_wifibb_80x1_fo:1;
uint32_t clk_wifibb_160x1_fo:1;
uint32_t clk_wifimac_fo:1;
uint32_t clk_wifi_apb_fo:1;
uint32_t clk_fe_20m_fo:1;
uint32_t clk_fe_40m_fo:1;
uint32_t clk_fe_80m_fo:1;
uint32_t clk_fe_160m_fo:1;
uint32_t clk_fe_cal_160m_fo:1;
uint32_t clk_fe_apb_fo:1;
uint32_t clk_bt_apb_fo:1;
uint32_t clk_bt_fo:1;
uint32_t clk_wifibb_480m_fo:1;
uint32_t clk_fe_480m_fo:1;
uint32_t clk_fe_anamode_40m_fo:1;
uint32_t clk_fe_anamode_80m_fo:1;
uint32_t clk_fe_anamode_160m_fo:1;
uint32_t reserved_24:8;
};
uint32_t val;
} modem_syscon_clk_conf1_force_on_reg_t;
typedef union {
struct {
uint32_t wifi_bb_cfg:32;
};
uint32_t val;
} modem_syscon_wifi_bb_cfg_reg_t;
typedef union {
struct {
uint32_t modem_mem_wp:3;
uint32_t modem_mem_wa:3;
uint32_t modem_mem_ra:2;
uint32_t reserved_8:24;
};
uint32_t val;
} modem_syscon_mem_conf_reg_t;
typedef union {
struct {
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} modem_syscon_date_reg_t;
typedef struct {
volatile modem_syscon_test_conf_reg_t test_conf;
volatile modem_syscon_clk_conf_reg_t clk_conf;
volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on;
volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st;
volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf;
volatile modem_syscon_clk_conf1_reg_t clk_conf1;
volatile modem_syscon_clk_conf1_force_on_reg_t clk_conf1_force_on;
volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg;
volatile modem_syscon_mem_conf_reg_t mem_conf;
volatile modem_syscon_date_reg_t date;
} modem_syscon_dev_t;
extern modem_syscon_dev_t MODEM_SYSCON;
#ifndef __cplusplus
_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define DR_REG_MODEM_SYSCON_BASE 0x600A9800
#define DR_REG_MODEM_LPCON_BASE 0x600AF000

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define ADC1_GPIO0_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 0
#define ADC1_GPIO1_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 3
#define ADC1_GPIO4_CHANNEL 4
#define ADC1_CHANNEL_4_GPIO_NUM 4
#define ADC1_GPIO5_CHANNEL 5
#define ADC1_CHANNEL_5_GPIO_NUM 5
#define ADC1_GPIO6_CHANNEL 6
#define ADC1_CHANNEL_6_GPIO_NUM 6

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** APB_SARADC_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
#define APB_SARADC_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U
#define APB_SARADC_SARADC_START_FORCE_S 0
/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
#define APB_SARADC_SARADC_START (BIT(1))
#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
#define APB_SARADC_SARADC_START_V 0x00000001U
#define APB_SARADC_SARADC_START_S 1
/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U
#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6
/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7
/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15
/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23
/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27
/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29))
#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U
#define APB_SARADC_SARADC2_PWDET_DRV_S 29
/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30
/** APB_SARADC_CTRL2_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0
/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1
/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR1_INV_S 9
/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR2_INV_S 10
/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_S 12
/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define APB_SARADC_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U
#define APB_SARADC_SARADC_TIMER_EN_S 24
/** APB_SARADC_FILTER_CTRL1_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26
/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29
/** APB_SARADC_FSM_WAIT_REG register
* digital saradc configure register
*/
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc)
/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8;
* saradc_xpd_wait
*/
#define APB_SARADC_SARADC_XPD_WAIT 0x000000FFU
#define APB_SARADC_SARADC_XPD_WAIT_M (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S)
#define APB_SARADC_SARADC_XPD_WAIT_V 0x000000FFU
#define APB_SARADC_SARADC_XPD_WAIT_S 0
/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8;
* saradc_rstb_wait
*/
#define APB_SARADC_SARADC_RSTB_WAIT 0x000000FFU
#define APB_SARADC_SARADC_RSTB_WAIT_M (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S)
#define APB_SARADC_SARADC_RSTB_WAIT_V 0x000000FFU
#define APB_SARADC_SARADC_RSTB_WAIT_S 8
/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255;
* saradc_standby_wait
*/
#define APB_SARADC_SARADC_STANDBY_WAIT 0x000000FFU
#define APB_SARADC_SARADC_STANDBY_WAIT_M (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S)
#define APB_SARADC_SARADC_STANDBY_WAIT_V 0x000000FFU
#define APB_SARADC_SARADC_STANDBY_WAIT_S 16
/** APB_SARADC_SAR1_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912;
* saradc1 status about data and channel
*/
#define APB_SARADC_SARADC_SAR1_STATUS 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR1_STATUS_M (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S)
#define APB_SARADC_SARADC_SAR1_STATUS_V 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR1_STATUS_S 0
/** APB_SARADC_SAR2_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912;
* saradc2 status about data and channel
*/
#define APB_SARADC_SARADC_SAR2_STATUS 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR2_STATUS_M (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S)
#define APB_SARADC_SARADC_SAR2_STATUS_V 0xFFFFFFFFU
#define APB_SARADC_SARADC_SAR2_STATUS_S 0
/** APB_SARADC_SAR_PATT_TAB1_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0
/** APB_SARADC_SAR_PATT_TAB2_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0
/** APB_SARADC_ONETIME_SAMPLE_REG register
* digital saradc configure register
*/
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23
/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25
/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
#define APB_SARADC_SARADC_ONETIME_START (BIT(29))
#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U
#define APB_SARADC_SARADC_ONETIME_START_S 29
/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30))
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30
/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31))
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31
/** APB_SARADC_ARB_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/** APB_SARADC_FILTER_CTRL0_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28)
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22
/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31))
#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U
#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31
/** APB_SARADC_SAR1DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c)
/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_S 0
/** APB_SARADC_SAR2DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30)
/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_S 0
/** APB_SARADC_THRES0_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34)
/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18
/** APB_SARADC_THRES1_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18
/** APB_SARADC_THRES_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c)
/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27
/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30))
#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_EN_S 30
/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31))
#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_EN_S 31
/** APB_SARADC_INT_ENA_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40)
/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31
/** APB_SARADC_INT_RAW_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44)
/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31
/** APB_SARADC_INT_ST_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48)
/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31
/** APB_SARADC_INT_CLR_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c)
/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31
/** APB_SARADC_DMA_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50)
/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U
#define APB_SARADC_APB_ADC_TRANS_S 31
/** APB_SARADC_CLKM_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54)
/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_S 0
/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
#define APB_SARADC_CLKM_DIV_B 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_S 8
/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
#define APB_SARADC_CLKM_DIV_A 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_S 14
/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
#define APB_SARADC_CLK_EN_V 0x00000001U
#define APB_SARADC_CLK_EN_S 20
/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
#define APB_SARADC_CLK_SEL 0x00000003U
#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
#define APB_SARADC_CLK_SEL_V 0x00000003U
#define APB_SARADC_CLK_SEL_S 21
/** APB_SARADC_APB_TSENS_CTRL_REG register
* digital tsens configure register
*/
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
#define APB_SARADC_TSENS_OUT 0x000000FFU
#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
#define APB_SARADC_TSENS_OUT_V 0x000000FFU
#define APB_SARADC_TSENS_OUT_S 0
/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
#define APB_SARADC_TSENS_IN_INV (BIT(13))
#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
#define APB_SARADC_TSENS_IN_INV_V 0x00000001U
#define APB_SARADC_TSENS_IN_INV_S 13
/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_S 14
/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
#define APB_SARADC_TSENS_PU (BIT(22))
#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
#define APB_SARADC_TSENS_PU_V 0x00000001U
#define APB_SARADC_TSENS_PU_S 22
/** APB_SARADC_TSENS_CTRL2_REG register
* digital tsens configure register
*/
#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c)
/** APB_SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2;
* the time that power up tsens need wait
*/
#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFFU
#define APB_SARADC_TSENS_XPD_WAIT_M (APB_SARADC_TSENS_XPD_WAIT_V << APB_SARADC_TSENS_XPD_WAIT_S)
#define APB_SARADC_TSENS_XPD_WAIT_V 0x00000FFFU
#define APB_SARADC_TSENS_XPD_WAIT_S 0
/** APB_SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0;
* force power up tsens
*/
#define APB_SARADC_TSENS_XPD_FORCE 0x00000003U
#define APB_SARADC_TSENS_XPD_FORCE_M (APB_SARADC_TSENS_XPD_FORCE_V << APB_SARADC_TSENS_XPD_FORCE_S)
#define APB_SARADC_TSENS_XPD_FORCE_V 0x00000003U
#define APB_SARADC_TSENS_XPD_FORCE_S 12
/** APB_SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1;
* inv tsens clk
*/
#define APB_SARADC_TSENS_CLK_INV (BIT(14))
#define APB_SARADC_TSENS_CLK_INV_M (APB_SARADC_TSENS_CLK_INV_V << APB_SARADC_TSENS_CLK_INV_S)
#define APB_SARADC_TSENS_CLK_INV_V 0x00000001U
#define APB_SARADC_TSENS_CLK_INV_S 14
/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U
#define APB_SARADC_TSENS_CLK_SEL_S 15
/** APB_SARADC_CALI_REG register
* digital saradc configure register
*/
#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60)
/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_S 0
/** APB_TSENS_WAKE_REG register
* digital tsens configure register
*/
#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64)
/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_S 0
/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_S 8
/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16))
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16
/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
#define APB_SARADC_WAKEUP_MODE (BIT(17))
#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
#define APB_SARADC_WAKEUP_MODE_V 0x00000001U
#define APB_SARADC_WAKEUP_MODE_S 17
/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
#define APB_SARADC_WAKEUP_EN (BIT(18))
#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
#define APB_SARADC_WAKEUP_EN_V 0x00000001U
#define APB_SARADC_WAKEUP_EN_S 18
/** APB_TSENS_SAMPLE_REG register
* digital tsens configure register
*/
#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68)
/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_S 0
/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16))
#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U
#define APB_SARADC_TSENS_SAMPLE_EN_S 16
/** APB_SARADC_CTRL_DATE_REG register
* version
*/
#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
#define APB_SARADC_DATE 0xFFFFFFFFU
#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
#define APB_SARADC_DATE_V 0xFFFFFFFFU
#define APB_SARADC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of saradc_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
uint32_t saradc_saradc_start_force:1;
/** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
uint32_t saradc_saradc_start:1;
uint32_t reserved_2:4;
/** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
uint32_t saradc_saradc_sar_clk_gated:1;
/** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
uint32_t saradc_saradc_sar_clk_div:8;
/** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t saradc_saradc_sar_patt_len:3;
uint32_t reserved_18:5;
/** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t saradc_saradc_sar_patt_p_clear:1;
uint32_t reserved_24:3;
/** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
uint32_t saradc_saradc_xpd_sar_force:2;
/** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
uint32_t saradc_saradc2_pwdet_drv:1;
/** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
uint32_t saradc_saradc_wait_arb_cycle:2;
};
uint32_t val;
} apb_saradc_ctrl_reg_t;
/** Type of saradc_ctrl2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
uint32_t saradc_saradc_meas_num_limit:1;
/** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
uint32_t saradc_saradc_max_meas_num:8;
/** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar1_inv:1;
/** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar2_inv:1;
uint32_t reserved_11:1;
/** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t saradc_saradc_timer_target:12;
/** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t saradc_saradc_timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} apb_saradc_ctrl2_reg_t;
/** Type of saradc_filter_ctrl1 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
uint32_t saradc_apb_saradc_filter_factor1:3;
/** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
uint32_t saradc_apb_saradc_filter_factor0:3;
};
uint32_t val;
} apb_saradc_filter_ctrl1_reg_t;
/** Type of saradc_fsm_wait register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8;
* saradc_xpd_wait
*/
uint32_t saradc_saradc_xpd_wait:8;
/** saradc_saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8;
* saradc_rstb_wait
*/
uint32_t saradc_saradc_rstb_wait:8;
/** saradc_saradc_standby_wait : R/W; bitpos: [23:16]; default: 255;
* saradc_standby_wait
*/
uint32_t saradc_saradc_standby_wait:8;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_fsm_wait_reg_t;
/** Type of saradc_sar1_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912;
* saradc1 status about data and channel
*/
uint32_t saradc_saradc_sar1_status:32;
};
uint32_t val;
} apb_saradc_sar1_status_reg_t;
/** Type of saradc_sar2_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912;
* saradc2 status about data and channel
*/
uint32_t saradc_saradc_sar2_status:32;
};
uint32_t val;
} apb_saradc_sar2_status_reg_t;
/** Type of saradc_sar_patt_tab1 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab1_reg_t;
/** Type of saradc_sar_patt_tab2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab2_reg_t;
/** Type of saradc_onetime_sample register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
uint32_t saradc_saradc_onetime_atten:2;
/** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
uint32_t saradc_saradc_onetime_channel:4;
/** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
uint32_t saradc_saradc_onetime_start:1;
/** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
uint32_t saradc_saradc2_onetime_sample:1;
/** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
uint32_t saradc_saradc1_onetime_sample:1;
};
uint32_t val;
} apb_saradc_onetime_sample_reg_t;
/** Type of saradc_arb_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
uint32_t saradc_adc_arb_apb_force:1;
/** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
uint32_t saradc_adc_arb_rtc_force:1;
/** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
uint32_t saradc_adc_arb_wifi_force:1;
/** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
uint32_t saradc_adc_arb_grant_force:1;
/** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
uint32_t saradc_adc_arb_apb_priority:2;
/** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
uint32_t saradc_adc_arb_rtc_priority:2;
/** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
uint32_t saradc_adc_arb_wifi_priority:2;
/** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
uint32_t saradc_adc_arb_fix_priority:1;
uint32_t reserved_13:19;
};
uint32_t val;
} apb_saradc_arb_ctrl_reg_t;
/** Type of saradc_filter_ctrl0 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:18;
/** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel1:4;
/** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel0:4;
uint32_t reserved_26:5;
/** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t saradc_apb_saradc_filter_reset:1;
};
uint32_t val;
} apb_saradc_filter_ctrl0_reg_t;
/** Type of saradc_sar1data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
uint32_t saradc_apb_saradc1_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar1data_status_reg_t;
/** Type of saradc_sar2data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
uint32_t saradc_apb_saradc2_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar2data_status_reg_t;
/** Type of saradc_thres0_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
uint32_t saradc_apb_saradc_thres0_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_high:13;
/** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres0_ctrl_reg_t;
/** Type of saradc_thres1_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
uint32_t saradc_apb_saradc_thres1_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_high:13;
/** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres1_ctrl_reg_t;
/** Type of saradc_thres_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
uint32_t saradc_apb_saradc_thres_all_en:1;
uint32_t reserved_28:2;
/** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
uint32_t saradc_apb_saradc_thres1_en:1;
/** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
uint32_t saradc_apb_saradc_thres0_en:1;
};
uint32_t val;
} apb_saradc_thres_ctrl_reg_t;
/** Type of saradc_int_ena register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
uint32_t saradc_apb_saradc_tsens_int_ena:1;
/** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
/** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
/** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
/** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
/** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
uint32_t saradc_apb_saradc2_done_int_ena:1;
/** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
uint32_t saradc_apb_saradc1_done_int_ena:1;
};
uint32_t val;
} apb_saradc_int_ena_reg_t;
/** Type of saradc_int_raw register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
uint32_t saradc_apb_saradc_tsens_int_raw:1;
/** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
/** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
/** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
/** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
/** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
uint32_t saradc_apb_saradc2_done_int_raw:1;
/** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
uint32_t saradc_apb_saradc1_done_int_raw:1;
};
uint32_t val;
} apb_saradc_int_raw_reg_t;
/** Type of saradc_int_st register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
uint32_t saradc_apb_saradc_tsens_int_st:1;
/** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
uint32_t saradc_apb_saradc_thres1_low_int_st:1;
/** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
uint32_t saradc_apb_saradc_thres0_low_int_st:1;
/** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
uint32_t saradc_apb_saradc_thres1_high_int_st:1;
/** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
uint32_t saradc_apb_saradc_thres0_high_int_st:1;
/** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
uint32_t saradc_apb_saradc2_done_int_st:1;
/** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
uint32_t saradc_apb_saradc1_done_int_st:1;
};
uint32_t val;
} apb_saradc_int_st_reg_t;
/** Type of saradc_int_clr register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
uint32_t saradc_apb_saradc_tsens_int_clr:1;
/** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
/** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
/** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
/** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
/** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
uint32_t saradc_apb_saradc2_done_int_clr:1;
/** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
uint32_t saradc_apb_saradc1_done_int_clr:1;
};
uint32_t val;
} apb_saradc_int_clr_reg_t;
/** Type of saradc_dma_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t saradc_apb_adc_eof_num:16;
uint32_t reserved_16:14;
/** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
uint32_t saradc_apb_adc_reset_fsm:1;
/** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t saradc_apb_adc_trans:1;
};
uint32_t val;
} apb_saradc_dma_conf_reg_t;
/** Type of saradc_clkm_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
uint32_t saradc_clkm_div_num:8;
/** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
uint32_t saradc_clkm_div_b:6;
/** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
uint32_t saradc_clkm_div_a:6;
/** saradc_clk_en : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
uint32_t saradc_clk_en:1;
/** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
uint32_t saradc_clk_sel:2;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_clkm_conf_reg_t;
/** Type of saradc_apb_tsens_ctrl register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
uint32_t saradc_tsens_out:8;
uint32_t reserved_8:5;
/** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
uint32_t saradc_tsens_in_inv:1;
/** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
uint32_t saradc_tsens_clk_div:8;
/** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
uint32_t saradc_tsens_pu:1;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_apb_tsens_ctrl_reg_t;
/** Type of saradc_tsens_ctrl2 register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2;
* the time that power up tsens need wait
*/
uint32_t saradc_tsens_xpd_wait:12;
/** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0;
* force power up tsens
*/
uint32_t saradc_tsens_xpd_force:2;
/** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1;
* inv tsens clk
*/
uint32_t saradc_tsens_clk_inv:1;
/** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
uint32_t saradc_tsens_clk_sel:1;
uint32_t reserved_16:16;
};
uint32_t val;
} apb_saradc_tsens_ctrl2_reg_t;
/** Type of saradc_cali register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
uint32_t saradc_apb_saradc_cali_cfg:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_cali_reg_t;
/** Type of tsens_wake register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
uint32_t saradc_wakeup_th_low:8;
/** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
uint32_t saradc_wakeup_th_high:8;
/** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
uint32_t saradc_wakeup_over_upper_th:1;
/** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
uint32_t saradc_wakeup_mode:1;
/** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
uint32_t saradc_wakeup_en:1;
uint32_t reserved_19:13;
};
uint32_t val;
} apb_tsens_wake_reg_t;
/** Type of tsens_sample register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
uint32_t saradc_tsens_sample_rate:16;
/** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
uint32_t saradc_tsens_sample_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_tsens_sample_reg_t;
/** Type of saradc_ctrl_date register
* version
*/
typedef union {
struct {
/** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
uint32_t saradc_date:32;
};
uint32_t val;
} apb_saradc_ctrl_date_reg_t;
typedef struct apb_dev_t {
volatile apb_saradc_ctrl_reg_t saradc_ctrl;
volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
volatile apb_saradc_fsm_wait_reg_t saradc_fsm_wait;
volatile apb_saradc_sar1_status_reg_t saradc_sar1_status;
volatile apb_saradc_sar2_status_reg_t saradc_sar2_status;
volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
volatile apb_saradc_int_ena_reg_t saradc_int_ena;
volatile apb_saradc_int_raw_reg_t saradc_int_raw;
volatile apb_saradc_int_st_reg_t saradc_int_st;
volatile apb_saradc_int_clr_reg_t saradc_int_clr;
volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
volatile apb_saradc_cali_reg_t saradc_cali;
volatile apb_tsens_wake_reg_t tsens_wake;
volatile apb_tsens_sample_reg_t tsens_sample;
uint32_t reserved_06c[228];
volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
} apb_dev_t;
extern apb_dev_t APB_SARADC;
#ifndef __cplusplus
_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/boot_mode.h Normal file
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_BOOT_MODE_H_
#define _SOC_BOOT_MODE_H_
#include "soc.h"
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, SPI(or SDIO_V2)/UART0*/
#define IS_00XX(v) (((v)&0x0c)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
#define IS_0000(v) (((v)&0x0f)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
#define IS_0001(v) (((v)&0x0f)==0x01)
/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
#define IS_0010(v) (((v)&0x0f)==0x02)
/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
#define IS_0011(v) (((v)&0x0f)==0x03)
/*legacy SPI Boot*/
#define IS_0100(v) (((v)&0x0f)==0x04)
/*ATE/ANALOG Mode*/
#define IS_0101(v) (((v)&0x0f)==0x05)
/*SPI(or SDIO_V1) download Mode*/
#define IS_0110(v) (((v)&0x0f)==0x06)
/*Diagnostic Mode+UART0 download Mode*/
#define IS_0111(v) (((v)&0x0f)==0x07)
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
/*do not include download mode*/
#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET())
/*all spi boot including spi/legacy*/
#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
/*all faster spi boot including spi*/
#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
#if SUPPORT_SDIO_DOWNLOAD
/*all sdio V2 of failing edge input, failing edge output*/
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET())
/*all sdio V2 of failing edge input, raising edge output*/
#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET())
/*all sdio V2 of raising edge input, raising edge output*/
#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET())
/*all sdio V1 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET())
/*do not include joint download mode*/
#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET())
#else
/*do not include joint download mode*/
#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET())
#endif
/*joint download boot*/
#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET())
/*ATE mode*/
#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET())
/*used by ETS_IS_SDIO_UART_BOOT*/
#define SEL_NO_BOOT 0
#define SEL_SDIO_BOOT BIT0
#define SEL_UART_BOOT BIT1
#define SEL_SPI_SLAVE_BOOT BIT2
#endif /* _SOC_BOOT_MODE_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define _CLIC_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define NLBITS 3
#define CLIC_EXT_INTR_NUM_OFFSET 16
#define DUALCORE_CLIC_CTRL_OFF 0x10000
#define DR_REG_CLIC_BASE ( 0x20800000 )
#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 )
#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0)
/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */
/*description: .*/
#define CLIC_INT_CONFIG_NMBITS 0x00000003
#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S))
#define CLIC_INT_CONFIG_NMBITS_V 0x3
#define CLIC_INT_CONFIG_NMBITS_S 5
/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
/*description: .*/
#define CLIC_INT_CONFIG_NLBITS 0x0000000F
#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S))
#define CLIC_INT_CONFIG_NLBITS_V 0xF
#define CLIC_INT_CONFIG_NLBITS_S 1
/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */
/*description: .*/
#define CLIC_INT_CONFIG_NVBITS (BIT(0))
#define CLIC_INT_CONFIG_NVBITS_M (BIT(0))
#define CLIC_INT_CONFIG_NVBITS_V 0x1
#define CLIC_INT_CONFIG_NVBITS_S 0
#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4)
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
/*description: .*/
#define CLIC_INT_INFO_CTLBITS 0x0000000F
#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S))
#define CLIC_INT_INFO_CTLBITS_V 0xF
#define CLIC_INT_INFO_CTLBITS_S 21
/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */
/*description: .*/
#define CLIC_INT_INFO_VERSION 0x000000FF
#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S))
#define CLIC_INT_INFO_VERSION_V 0xFF
#define CLIC_INT_INFO_VERSION_S 13
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */
/*description: .*/
#define CLIC_INT_INFO_NUM_INT 0x00001FFF
#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S))
#define CLIC_INT_INFO_NUM_INT_V 0x1FFF
#define CLIC_INT_INFO_NUM_INT_S 0
#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8)
/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
/*description: .*/
#define CLIC_CPU_INT_THRESH 0x000000FF
#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S))
#define CLIC_CPU_INT_THRESH_V 0xFF
#define CLIC_CPU_INT_THRESH_S 24
#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4)
/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
/*description: .*/
#define CLIC_INT_CTL 0x000000FF
#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S))
#define CLIC_INT_CTL_V 0xFF
#define CLIC_INT_CTL_S 24
/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
/*description: .*/
#define CLIC_INT_ATTR_MODE 0x00000003
#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S))
#define CLIC_INT_ATTR_MODE_V 0x3
#define CLIC_INT_ATTR_MODE_S 22
/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: .*/
#define CLIC_INT_ATTR_TRIG 0x00000003
#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S))
#define CLIC_INT_ATTR_TRIG_V 0x3
#define CLIC_INT_ATTR_TRIG_S 17
/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_ATTR_SHV (BIT(16))
#define CLIC_INT_ATTR_SHV_M (BIT(16))
#define CLIC_INT_ATTR_SHV_V 0x1
#define CLIC_INT_ATTR_SHV_S 16
/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_IE (BIT(8))
#define CLIC_INT_IE_M (BIT(8))
#define CLIC_INT_IE_V 0x1
#define CLIC_INT_IE_S 8
/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_IP (BIT(0))
#define CLIC_INT_IP_M (BIT(0))
#define CLIC_INT_IP_V 0x1
#define CLIC_INT_IP_S 0
#ifdef __cplusplus
}
#endif
#endif /*_CLIC_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DR_REG_CLINT_M_BASE(i) ( 0x20001800 + (i) * 0x100 )
#define DR_REG_CLINT_U_BASE(i) ( 0x20001C00 + (i) * 0x100 )
/*CLINT MINT*/
#define CLINT_MINT_SIP_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x0)
/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define CLINT_CPU_MINT_SIP 0xFFFFFFFF
#define CLINT_CPU_MINT_SIP_M ((CLINT_CPU_MINT_SIP_V)<<(CLINT_CPU_MINT_SIP_S))
#define CLINT_CPU_MINT_SIP_V 0xFFFFFFFF
#define CLINT_CPU_MINT_SIP_S 0
#define CLINT_MINT_TIMECTL_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x4)
/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
/*description: .*/
#define CLINT_MINT_SAMPLING_MODE 0x00000003
#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
#define CLINT_MINT_SAMPLING_MODE_V 0x3
#define CLINT_MINT_SAMPLING_MODE_S 4
/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3))
#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3))
#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1
#define CLINT_MINT_COUNTER_OVERFLOW_S 3
/* CLINT_MINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define CLINT_MINT_TIMERINT_PENDING (BIT(2))
#define CLINT_MINT_TIMERINT_PENDING_M (BIT(2))
#define CLINT_MINT_TIMERINT_PENDING_V 0x1
#define CLINT_MINT_TIMERINT_PENDING_S 2
/* CLINT_MINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define CLINT_MINT_TIMERINT_EN (BIT(1))
#define CLINT_MINT_TIMERINT_EN_M (BIT(1))
#define CLINT_MINT_TIMERINT_EN_V 0x1
#define CLINT_MINT_TIMERINT_EN_S 1
/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define CLINT_MINT_COUNTER_EN (BIT(0))
#define CLINT_MINT_COUNTER_EN_M (BIT(0))
#define CLINT_MINT_COUNTER_EN_V 0x1
#define CLINT_MINT_COUNTER_EN_S 0
#define CLINT_MINT_MTIME_L_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x8)
/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_S 0
#define CLINT_MINT_MTIME_H_REG(i) (DR_REG_CLINT_M_BASE(i) + 0xC)
/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_H_S 0
#define CLINT_MINT_MTIMECMP_L_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x10)
/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_L_S 0
#define CLINT_MINT_MTIMECMP_H_REG(i) (DR_REG_CLINT_M_BASE(i) + 0x14)
/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_S 0
/*CLINT UINT*/
#define CLINT_UINT_SIP_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x0)
/* CLINT_CPU_UINT_SIP : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: .*/
#define CLINT_CPU_UINT_SIP 0xFFFFFFFF
#define CLINT_CPU_UINT_SIP_M ((CLINT_CPU_UINT_SIP_V)<<(CLINT_CPU_UINT_SIP_S))
#define CLINT_CPU_UINT_SIP_V 0xFFFFFFFF
#define CLINT_CPU_UINT_SIP_S 0
#define CLINT_UINT_TIMECTL_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x4)
/* CLINT_UINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
/*description: .*/
#define CLINT_UINT_SAMPLING_MODE 0x00000003
#define CLINT_UINT_SAMPLING_MODE_M ((CLINT_CPU_UINT_TIMECTL_V)<<(CLINT_CPU_UINT_TIMECTL_S))
#define CLINT_UINT_SAMPLING_MODE_V 0x3
#define CLINT_UINT_SAMPLING_MODE_S 4
/* CLINT_UINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define CLINT_UINT_COUNTER_OVERFLOW (BIT(3))
#define CLINT_UINT_COUNTER_OVERFLOW_M (BIT(3))
#define CLINT_UINT_COUNTER_OVERFLOW_V 0x1
#define CLINT_UINT_COUNTER_OVERFLOW_S 3
/* CLINT_UINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define CLINT_UINT_TIMERINT_PENDING (BIT(2))
#define CLINT_UINT_TIMERINT_PENDING_M (BIT(2))
#define CLINT_UINT_TIMERINT_PENDING_V 0x1
#define CLINT_UINT_TIMERINT_PENDING_S 2
/* CLINT_UINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define CLINT_UINT_TIMERINT_EN (BIT(1))
#define CLINT_UINT_TIMERINT_EN_M (BIT(1))
#define CLINT_UINT_TIMERINT_EN_V 0x1
#define CLINT_UINT_TIMERINT_EN_S 1
/* CLINT_UINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define CLINT_UINT_COUNTER_EN (BIT(0))
#define CLINT_UINT_COUNTER_EN_M (BIT(0))
#define CLINT_UINT_COUNTER_EN_V 0x1
#define CLINT_UINT_COUNTER_EN_S 0
#define CLINT_UINT_UTIME_L_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x8)
/* CLINT_CPU_UINT_UTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_UINT_UTIME_L 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIME_L_M ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S))
#define CLINT_CPU_UINT_UTIME_L_V 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIME_L_S 0
#define CLINT_UINT_UTIME_H_REG(i) (DR_REG_CLINT_U_BASE(i) + 0xC)
/* CLINT_CPU_UINT_UTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_UINT_UTIME_H 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIME_H_M ((CLINT_CPU_UINT_UTIME_H_V)<<(CLINT_CPU_UINT_UTIME_H_S))
#define CLINT_CPU_UINT_UTIME_H_V 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIME_H_S 0
#define CLINT_UINT_UTIMECMP_L_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x10)
/* CLINT_CPU_UINT_UTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_UINT_UTIMECMP_L 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIMECMP_L_M ((CLINT_CPU_UINT_UTIMECMP_L_V)<<(CLINT_CPU_UINT_UTIMECMP_L_S))
#define CLINT_CPU_UINT_UTIMECMP_L_V 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIMECMP_L_S 0
#define CLINT_UINT_UTIMECMP_H_REG(i) (DR_REG_CLINT_U_BASE(i) + 0x14)
/* CLINT_CPU_UINT_UTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_UINT_UTIMECMP_H 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIMECMP_H_M ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S))
#define CLINT_CPU_UINT_UTIMECMP_H_V 0xFFFFFFFF
#define CLINT_CPU_UINT_UTIMECMP_H_S 0
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
************************* ESP32C6 Root Clock Source ****************************
* 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
*
* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
*
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
*
* 2) External 40MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
*
* 4) Internal 32kHz RC Oscillator: RC32K
*
* The exact frequency of this clock can be computed in runtime through calibration.
*
* 5) External 32kHz Crystal Clock (optional): XTAL32K
*
* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
* pins.
*
* XTAL32K_CLK can also be calibrated to get its exact frequency.
*
* 6) External Slow Clock (optional): OSC_SLOW
*
* A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the
* RTC_SLOW_CLK.
*
* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
*/
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
// {loc}: EXT, INT
// {type}: XTAL, RC
// [attr] - optional: [frequency], FAST, SLOW
/**
* @brief Root clock
*/
typedef enum {
SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */
SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */
SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */
} soc_root_clk_t;
/**
* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
} soc_cpu_clk_src_t;
/**
* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
} soc_rtc_slow_clk_src_t;
/**
* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
} soc_rtc_fast_clk_src_t;
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
/**
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
*
* @note enum starts from 1, to save 0 for special purpose
*/
typedef enum {
// For CPU domain
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
// For RTC domain
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
/**
* @brief Type of SYSTIMER clock source
*/
typedef enum {
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */
SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t;
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of GPTimer
*
* The following code can be used to iterate all possible clocks:
* @code{c}
* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
* // Test GPTimer with the clock `clk`
* }
* @endcode
*/
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of GPTimer clock source
*/
typedef enum {
GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of RMT
*/
#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of RMT clock source
*/
typedef enum {
RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_rmt_clk_src_t;
/**
* @brief Type of RMT clock source, reserved for the legacy RMT driver
*/
typedef enum {
RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Temperature Sensor
*/
#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of Temp Sensor clock source
*/
typedef enum {
TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
} soc_periph_temperature_sensor_clk_src_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
* @brief Type of UART clock source, reserved for the legacy UART driver
*/
typedef enum {
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
} soc_periph_uart_clk_src_legacy_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief I2S clock source enum
*/
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2C
*/
#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of I2C clock source.
*/
typedef enum {
I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
} soc_periph_i2c_clk_src_t;
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of SPI clock source.
*/
typedef enum {
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
} soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
*/
#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Sigma Delta Modulator clock source
*/
typedef enum {
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of TWAI
*/
#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL}
/**
* @brief TWAI clock source
*/
typedef enum {
TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of ADC digital controller
*/
#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief ADC digital controller clock source
*/
typedef enum {
ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
} soc_periph_adc_digi_clk_src_t;
//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MWDT
*/
#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief MWDT clock source
*/
typedef enum {
MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */
MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of LEDC
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of LEDC clock source, reserved for the legacy LEDC driver
*/
typedef enum {
LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PARLIO
*/
#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M}
/**
* @brief PARLIO clock source
*/
typedef enum {
PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
} soc_periph_parlio_clk_src_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// ESP32C6 CLKOUT signals has no corresponding iomux pins

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
#include <stdint.h>
#include "soc.h"
#include "uart_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
* @brief Read a sequence of DPORT registers to the buffer.
*
* @param[out] buff_out Contains the read data.
* @param[in] address Initial address for reading registers.
* @param[in] num_words The number of words.
*/
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
// Write value to DPORT register (does not require protecting)
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
//get bit or get bits from register
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
//set bit or set bits to register
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
//clear bit or clear bits of register
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
//set bits of register controlled by mask
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
//get field from register, uses field _S & _V to determine mask
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
//set field to register, used when _f is not left shifted by _f##_S
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
//get field value from a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
//write value to register
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
//clear bits of register controlled by mask
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
//set bits of register controlled by mask
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
//get bits of register controlled by mask
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
//get bits of register controlled by highest bit and lowest bit
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
//set bits of register controlled by mask and shift
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
//get field of register
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
//}}
#ifdef __cplusplus
}
#endif
#endif /* _DPORT_ACCESS_H_ */

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
* We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
* Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define IRAM0_CACHE_ADDRESS_LOW 0x40000000
#define IRAM0_CACHE_ADDRESS_HIGH 0x50000000
#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
#define DRAM0_CACHE_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
#define DRAM0_CACHE_OPERATION_HIGH 0x44000000
#define SINGLE_BANK_CACHE_ADDRESS_LOW 0x40000000
#define SINGLE_BANK_CACHE_ADDRESS_HIGH 0x44000000
#define DUAL_BANK_CACHE_ADDRESS_LOW 0x48000000
#define DUAL_BANK_CACHE_ADDRESS_HIGH 0x4C000000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
//TODO, remove these cache function dependencies
#define CACHE_IROM_MMU_START 0
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
#define CACHE_DROM_MMU_MAX_END 0x400
#define ICACHE_MMU_SIZE (0x400 * 4)
#define DCACHE_MMU_SIZE (0x400 * 4)
#define MMU_BUS_START(i) 0
#define MMU_BUS_SIZE(i) (0x400 * 4)
#define MMU_MSPI_ACCESS_FLASH 0
#define MMU_MSPI_ACCESS_SPIRAM BIT(10)
#define MMU_MSPI_VALID BIT(12)
#define MMU_MSPI_INVALID 0
#define MMU_MSPI_SENSITIVE BIT(13)
#define MMU_PSRAM_ACCESS_SPIRAM BIT(10)
#define MMU_PSRAM_VALID BIT(11)
#define MMU_PSRAM_SENSITIVE BIT(12)
#define MMU_ACCESS_FLASH MMU_MSPI_ACCESS_FLASH
#define MMU_ACCESS_SPIRAM MMU_MSPI_ACCESS_SPIRAM
#define MMU_VALID MMU_MSPI_VALID
#define MMU_SENSITIVE MMU_MSPI_SENSITIVE
#define DMMU_SENSITIVE MMU_PSRAM_SENSITIVE
#define MMU_INVALID_MASK MMU_MSPI_VALID
#define MMU_INVALID MMU_MSPI_INVALID
#define DMMU_INVALID_MASK MMU_PSRAM_VALID
#define DMMU_INVALID 0
#define CACHE_MAX_SYNC_NUM 0x400000
#define CACHE_MAX_LOCK_NUM 0x8000
/**
* MMU entry valid bit mask for mapping value. For an entry:
* valid bit + value bits
* valid bit is BIT(9), so value bits are 0x1ff
*/
#define MMU_VALID_VAL_MASK 0x3ff
/**
* Max MMU available paddr page num.
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can support 16MB paddr at most
*/
#define MMU_MAX_PADDR_PAGE_NUM 1024
//MMU entry num
#define MMU_ENTRY_NUM 1024
/**
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & MMU_VADDR_MASK
*/
#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
#define SOC_MMU_FLASH_VADDR_BASE 0x40000000
#define SOC_MMU_PSRAM_VADDR_BASE 0x48000000
#define SOC_MMU_FLASH_VADDR_START 0x40000000
#define SOC_MMU_FLASH_VADDR_END 0x44000000
#define SOC_MMU_PSRAM_VADDR_START 0x48000000
#define SOC_MMU_PSRAM_VADDR_END 0x4C000000
/*------------------------------------------------------------------------------
* MMU Linear Address
*----------------------------------------------------------------------------*/
/**
* - 64KB MMU page size: the last 0xFFFF, which is the offset
* - 1024 MMU entries, needs 0x3F to hold it.
*
* Therefore, 0x3F,FFFF
*/
#define SOC_MMU_MEM_PHYSICAL_LINEAR_CAP (SOC_MMU_FLASH_VADDR_BASE ^ SOC_MMU_PSRAM_VADDR_BASE)
#define SOC_MMU_LINEAR_FLASH_ADDR_MASK (0xBFFFFFF)
#define SOC_MMU_LINEAR_PARSM_ADDR_MASK (0xBFFFFFF | SOC_MMU_MEM_PHYSICAL_LINEAR_CAP)
/**
* - If high linear address isn't 0, this means MMU can recognize these addresses
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
* Under this condition, we use the max linear space.
*/
#define SOC_MMU_FLASH_LINEAR_ADDRESS_LOW (SOC_MMU_FLASH_VADDR_START & SOC_MMU_LINEAR_FLASH_ADDR_MASK)
#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_FLASH_ADDR_MASK + 1)
#define SOC_MMU_FLASH_LINEAR_ADDRESS_SIZE (SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH - SOC_MMU_FLASH_LINEAR_ADDRESS_LOW)
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW (SOC_MMU_PSRAM_VADDR_START & SOC_MMU_LINEAR_PARSM_ADDR_MASK)
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_PARSM_ADDR_MASK + 1)
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_SIZE (SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH - SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW)
/**
* I/D share the MMU linear address range
*/
_Static_assert((SOC_MMU_FLASH_LINEAR_ADDRESS_LOW & ~SOC_MMU_MEM_PHYSICAL_LINEAR_CAP) == (SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW & ~SOC_MMU_MEM_PHYSICAL_LINEAR_CAP), \
"IRAM0 and DRAM0 raw linear address should be same");
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define EXTMEM_L1_CACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4)
/* EXTMEM_L1_CACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
#define EXTMEM_L1_CACHE_SHUT_DBUS (BIT(1))
#define EXTMEM_L1_CACHE_SHUT_DBUS_M (BIT(1))
#define EXTMEM_L1_CACHE_SHUT_DBUS_V 0x1
#define EXTMEM_L1_CACHE_SHUT_DBUS_S 1
/* EXTMEM_L1_CACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
#define EXTMEM_L1_CACHE_SHUT_IBUS (BIT(0))
#define EXTMEM_L1_CACHE_SHUT_IBUS_M (BIT(0))
#define EXTMEM_L1_CACHE_SHUT_IBUS_V 0x1
#define EXTMEM_L1_CACHE_SHUT_IBUS_S 0
#define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20)
/* EXTMEM_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/
#define EXTMEM_L1_CACHE_WRAP (BIT(4))
#define EXTMEM_L1_CACHE_WRAP_M (BIT(4))
#define EXTMEM_L1_CACHE_WRAP_V 0x1
#define EXTMEM_L1_CACHE_WRAP_S 4
#define EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24)
/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU (BIT(18))
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_M (BIT(18))
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_V 0x1
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_S 18
/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power
down.*/
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD (BIT(17))
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_M (BIT(17))
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_V 0x1
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_S 17
/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: The bit is used to close clock gating of L1-Cache tag memory. 1: close gating,
0: open clock gating..*/
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON (BIT(16))
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_M (BIT(16))
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_V 0x1
#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_S 16
#define EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28)
/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u
p.*/
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU (BIT(18))
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_M (BIT(18))
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_V 0x1
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_S 18
/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
down.*/
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD (BIT(17))
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_M (BIT(17))
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_V 0x1
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_S 17
/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: The bit is used to close clock gating of L1-Cache data memory. 1: close gating,
0: open clock gating..*/
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON (BIT(16))
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_M (BIT(16))
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_V 0x1
#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_S 16
#define EXTMEM_L1_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C)
/* EXTMEM_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */
/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or
not. 0: not finished. 1: finished..*/
#define EXTMEM_L1_CACHE_FREEZE_DONE (BIT(18))
#define EXTMEM_L1_CACHE_FREEZE_DONE_M (BIT(18))
#define EXTMEM_L1_CACHE_FREEZE_DONE_V 0x1
#define EXTMEM_L1_CACHE_FREEZE_DONE_S 18
/* EXTMEM_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */
/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
will not stuck. 1: a miss-access will stuck..*/
#define EXTMEM_L1_CACHE_FREEZE_MODE (BIT(17))
#define EXTMEM_L1_CACHE_FREEZE_MODE_M (BIT(17))
#define EXTMEM_L1_CACHE_FREEZE_MODE_V 0x1
#define EXTMEM_L1_CACHE_FREEZE_MODE_S 17
/* EXTMEM_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof
tware..*/
#define EXTMEM_L1_CACHE_FREEZE_EN (BIT(16))
#define EXTMEM_L1_CACHE_FREEZE_EN_M (BIT(16))
#define EXTMEM_L1_CACHE_FREEZE_EN_V 0x1
#define EXTMEM_L1_CACHE_FREEZE_EN_S 16
#define EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30)
/* EXTMEM_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable,
1: enable..*/
#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN (BIT(17))
#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_M (BIT(17))
#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_V 0x1
#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_S 17
/* EXTMEM_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1
: enable..*/
#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN (BIT(16))
#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_M (BIT(16))
#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_V 0x1
#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_S 16
#define EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34)
/* EXTMEM_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1
: enable..*/
#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN (BIT(17))
#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_M (BIT(17))
#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_V 0x1
#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_S 17
/* EXTMEM_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
enable..*/
#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN (BIT(16))
#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_M (BIT(16))
#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_V 0x1
#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_S 16
#define EXTMEM_L1_CACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78)
/* EXTMEM_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN (BIT(1))
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_M (BIT(1))
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_V 0x1
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_S 1
/* EXTMEM_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN (BIT(0))
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_M (BIT(0))
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_V 0x1
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_S 0
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C)
/* EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the first section
of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0
_SIZE_REG.*/
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S))
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S 0
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80)
/* EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the second section
of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT
1_SIZE_REG.*/
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S))
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S 0
#define EXTMEM_L1_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84)
/* EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */
/*description: Those bits are used to configure the size of the second section of prelock on L1
-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFF
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S))
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V 0x3FFF
#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S 16
/* EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */
/*description: Those bits are used to configure the size of the first section of prelock on L1-
Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFF
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S))
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x3FFF
#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S 0
#define EXTMEM_L1_CACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88)
/* EXTMEM_L1_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */
/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0:
not finished. 1: finished..*/
#define EXTMEM_L1_CACHE_LOCK_DONE (BIT(2))
#define EXTMEM_L1_CACHE_LOCK_DONE_M (BIT(2))
#define EXTMEM_L1_CACHE_LOCK_DONE_V 0x1
#define EXTMEM_L1_CACHE_LOCK_DONE_S 2
/* EXTMEM_L1_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
unlock operation done.*/
#define EXTMEM_L1_CACHE_UNLOCK_ENA (BIT(1))
#define EXTMEM_L1_CACHE_UNLOCK_ENA_M (BIT(1))
#define EXTMEM_L1_CACHE_UNLOCK_ENA_V 0x1
#define EXTMEM_L1_CACHE_UNLOCK_ENA_S 1
/* EXTMEM_L1_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
ock operation done.*/
#define EXTMEM_L1_CACHE_LOCK_ENA (BIT(0))
#define EXTMEM_L1_CACHE_LOCK_ENA_M (BIT(0))
#define EXTMEM_L1_CACHE_LOCK_ENA_V 0x1
#define EXTMEM_L1_CACHE_LOCK_ENA_S 0
#define EXTMEM_L1_CACHE_LOCK_MAP_REG (DR_REG_EXTMEM_BASE + 0x8C)
/* EXTMEM_L1_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
/*description: Those bits are used to indicate which caches in the two-level cache structure wi
ll apply this lock/unlock operation. [4]: L1-Cache.*/
#define EXTMEM_L1_CACHE_LOCK_MAP 0x0000003F
#define EXTMEM_L1_CACHE_LOCK_MAP_M ((EXTMEM_L1_CACHE_LOCK_MAP_V)<<(EXTMEM_L1_CACHE_LOCK_MAP_S))
#define EXTMEM_L1_CACHE_LOCK_MAP_V 0x3F
#define EXTMEM_L1_CACHE_LOCK_MAP_S 0
#define EXTMEM_L1_CACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x90)
/* EXTMEM_L1_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the lock/unlock op
eration, which should be used together with CACHE_LOCK_SIZE_REG.*/
#define EXTMEM_L1_CACHE_LOCK_ADDR 0xFFFFFFFF
#define EXTMEM_L1_CACHE_LOCK_ADDR_M ((EXTMEM_L1_CACHE_LOCK_ADDR_V)<<(EXTMEM_L1_CACHE_LOCK_ADDR_S))
#define EXTMEM_L1_CACHE_LOCK_ADDR_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_LOCK_ADDR_S 0
#define EXTMEM_L1_CACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x94)
/* EXTMEM_L1_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: Those bits are used to configure the size of the lock/unlock operation, which sh
ould be used together with CACHE_LOCK_ADDR_REG.*/
#define EXTMEM_L1_CACHE_LOCK_SIZE 0x0000FFFF
#define EXTMEM_L1_CACHE_LOCK_SIZE_M ((EXTMEM_L1_CACHE_LOCK_SIZE_V)<<(EXTMEM_L1_CACHE_LOCK_SIZE_S))
#define EXTMEM_L1_CACHE_LOCK_SIZE_V 0xFFFF
#define EXTMEM_L1_CACHE_LOCK_SIZE_S 0
#define EXTMEM_L1_CACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x98)
/* EXTMEM_L1_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */
/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback
, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/
#define EXTMEM_L1_CACHE_SYNC_DONE (BIT(4))
#define EXTMEM_L1_CACHE_SYNC_DONE_M (BIT(4))
#define EXTMEM_L1_CACHE_SYNC_DONE_V 0x1
#define EXTMEM_L1_CACHE_SYNC_DONE_S 4
/* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
hardware after writeback-invalidate operation done. Note that this bit and the o
ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
, that is, those bits can not be set to 1 at the same time..*/
#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3))
#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3))
#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1
#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_S 3
/* EXTMEM_L1_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */
/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
ter writeback operation done. Note that this bit and the other sync-bits (invali
date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is,
those bits can not be set to 1 at the same time..*/
#define EXTMEM_L1_CACHE_WRITEBACK_ENA (BIT(2))
#define EXTMEM_L1_CACHE_WRITEBACK_ENA_M (BIT(2))
#define EXTMEM_L1_CACHE_WRITEBACK_ENA_V 0x1
#define EXTMEM_L1_CACHE_WRITEBACK_ENA_S 2
/* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
/*description: The bit is used to enable clean operation. It will be cleared by hardware after
clean operation done. Note that this bit and the other sync-bits (invalidate_ena
, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos
e bits can not be set to 1 at the same time..*/
#define EXTMEM_L1_CACHE_CLEAN_ENA (BIT(1))
#define EXTMEM_L1_CACHE_CLEAN_ENA_M (BIT(1))
#define EXTMEM_L1_CACHE_CLEAN_ENA_V 0x1
#define EXTMEM_L1_CACHE_CLEAN_ENA_S 1
/* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
fter invalidate operation done. Note that this bit and the other sync-bits (clea
n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
those bits can not be set to 1 at the same time..*/
#define EXTMEM_L1_CACHE_INVALIDATE_ENA (BIT(0))
#define EXTMEM_L1_CACHE_INVALIDATE_ENA_M (BIT(0))
#define EXTMEM_L1_CACHE_INVALIDATE_ENA_V 0x1
#define EXTMEM_L1_CACHE_INVALIDATE_ENA_S 0
#define EXTMEM_L1_CACHE_SYNC_MAP_REG (DR_REG_EXTMEM_BASE + 0x9C)
/* EXTMEM_L1_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
/*description: Those bits are used to indicate which caches in the two-level cache structure wi
ll apply the sync operation. [4]: L1-Cache.*/
#define EXTMEM_L1_CACHE_SYNC_MAP 0x0000003F
#define EXTMEM_L1_CACHE_SYNC_MAP_M ((EXTMEM_L1_CACHE_SYNC_MAP_V)<<(EXTMEM_L1_CACHE_SYNC_MAP_S))
#define EXTMEM_L1_CACHE_SYNC_MAP_V 0x3F
#define EXTMEM_L1_CACHE_SYNC_MAP_S 0
#define EXTMEM_L1_CACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA0)
/* EXTMEM_L1_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the sync operation
, which should be used together with CACHE_SYNC_SIZE_REG.*/
#define EXTMEM_L1_CACHE_SYNC_ADDR 0xFFFFFFFF
#define EXTMEM_L1_CACHE_SYNC_ADDR_M ((EXTMEM_L1_CACHE_SYNC_ADDR_V)<<(EXTMEM_L1_CACHE_SYNC_ADDR_S))
#define EXTMEM_L1_CACHE_SYNC_ADDR_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_SYNC_ADDR_S 0
#define EXTMEM_L1_CACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA4)
/* EXTMEM_L1_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Those bits are used to configure the size of the sync operation, which should be
used together with CACHE_SYNC_ADDR_REG.*/
#define EXTMEM_L1_CACHE_SYNC_SIZE 0x00FFFFFF
#define EXTMEM_L1_CACHE_SYNC_SIZE_M ((EXTMEM_L1_CACHE_SYNC_SIZE_V)<<(EXTMEM_L1_CACHE_SYNC_SIZE_S))
#define EXTMEM_L1_CACHE_SYNC_SIZE_V 0xFFFFFF
#define EXTMEM_L1_CACHE_SYNC_SIZE_S 0
#define EXTMEM_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xD8)
/* EXTMEM_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */
/*description: The bit is used to set the gid of l1 cache preload..*/
#define EXTMEM_L1_CACHE_PRELOAD_RGID 0x0000000F
#define EXTMEM_L1_CACHE_PRELOAD_RGID_M ((EXTMEM_L1_CACHE_PRELOAD_RGID_V)<<(EXTMEM_L1_CACHE_PRELOAD_RGID_S))
#define EXTMEM_L1_CACHE_PRELOAD_RGID_V 0xF
#define EXTMEM_L1_CACHE_PRELOAD_RGID_S 3
/* EXTMEM_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1
: descending..*/
#define EXTMEM_L1_CACHE_PRELOAD_ORDER (BIT(2))
#define EXTMEM_L1_CACHE_PRELOAD_ORDER_M (BIT(2))
#define EXTMEM_L1_CACHE_PRELOAD_ORDER_V 0x1
#define EXTMEM_L1_CACHE_PRELOAD_ORDER_S 2
/* EXTMEM_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
/*description: The bit is used to indicate whether preload operation is finished or not. 0: not
finished. 1: finished..*/
#define EXTMEM_L1_CACHE_PRELOAD_DONE (BIT(1))
#define EXTMEM_L1_CACHE_PRELOAD_DONE_M (BIT(1))
#define EXTMEM_L1_CACHE_PRELOAD_DONE_V 0x1
#define EXTMEM_L1_CACHE_PRELOAD_DONE_S 1
/* EXTMEM_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h
ardware automatically after preload operation is done..*/
#define EXTMEM_L1_CACHE_PRELOAD_ENA (BIT(0))
#define EXTMEM_L1_CACHE_PRELOAD_ENA_M (BIT(0))
#define EXTMEM_L1_CACHE_PRELOAD_ENA_V 0x1
#define EXTMEM_L1_CACHE_PRELOAD_ENA_S 0
#define EXTMEM_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0xDC)
/* EXTMEM_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of preload on L1-Cach
e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/
#define EXTMEM_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFF
#define EXTMEM_L1_CACHE_PRELOAD_ADDR_M ((EXTMEM_L1_CACHE_PRELOAD_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOAD_ADDR_S))
#define EXTMEM_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_PRELOAD_ADDR_S 0
#define EXTMEM_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0xE0)
/* EXTMEM_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
/*description: Those bits are used to configure the size of the first section of prelock on L1-
Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/
#define EXTMEM_L1_CACHE_PRELOAD_SIZE 0x00003FFF
#define EXTMEM_L1_CACHE_PRELOAD_SIZE_M ((EXTMEM_L1_CACHE_PRELOAD_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOAD_SIZE_S))
#define EXTMEM_L1_CACHE_PRELOAD_SIZE_V 0x3FFF
#define EXTMEM_L1_CACHE_PRELOAD_SIZE_S 0
#define EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134)
/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */
/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9))
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_M (BIT(9))
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x1
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9
/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8))
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_M (BIT(8))
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x1
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8
/* EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0
/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003
#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M ((EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S))
#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x3
#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3
/* EXTMEM_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0:
ascending. 1: descending..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER (BIT(2))
#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_M (BIT(2))
#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_V 0x1
#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_S 2
/* EXTMEM_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o
r not. 0: not finished. 1: finished..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_DONE (BIT(1))
#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_M (BIT(1))
#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_V 0x1
#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_S 1
/* EXTMEM_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: The bit is used to enable and disable autoload operation on L1-Cache. 1: enable
, 0: disable..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_ENA (BIT(0))
#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_M (BIT(0))
#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_V 0x1
#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_S 0
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x138)
/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the first section
for autoload operation on L1-Cache. Note that it should be used together with L1
_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S))
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x13C)
/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
/*description: Those bits are used to configure the size of the first section for autoload oper
ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S
CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFF
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S))
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFFF
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x140)
/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: Those bits are used to configure the start virtual address of the second section
for autoload operation on L1-Cache. Note that it should be used together with L
1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S))
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x144)
/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
/*description: Those bits are used to configure the size of the second section for autoload ope
ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_
SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFF
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S))
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFFF
#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0
#define EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x158)
/* EXTMEM_L1_DBUS_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
1-DCache due to bus1 accesses L1-DCache..*/
#define EXTMEM_L1_DBUS_OVF_INT_ENA (BIT(5))
#define EXTMEM_L1_DBUS_OVF_INT_ENA_M (BIT(5))
#define EXTMEM_L1_DBUS_OVF_INT_ENA_V 0x1
#define EXTMEM_L1_DBUS_OVF_INT_ENA_S 5
/* EXTMEM_L1_IBUS_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
1-DCache due to bus0 accesses L1-DCache..*/
#define EXTMEM_L1_IBUS_OVF_INT_ENA (BIT(4))
#define EXTMEM_L1_IBUS_OVF_INT_ENA_M (BIT(4))
#define EXTMEM_L1_IBUS_OVF_INT_ENA_V 0x1
#define EXTMEM_L1_IBUS_OVF_INT_ENA_S 4
#define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C)
/* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
ue to bus1 accesses L1-DCache..*/
#define EXTMEM_L1_DBUS_OVF_INT_CLR (BIT(5))
#define EXTMEM_L1_DBUS_OVF_INT_CLR_M (BIT(5))
#define EXTMEM_L1_DBUS_OVF_INT_CLR_V 0x1
#define EXTMEM_L1_DBUS_OVF_INT_CLR_S 5
/* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
ue to bus0 accesses L1-DCache..*/
#define EXTMEM_L1_IBUS_OVF_INT_CLR (BIT(4))
#define EXTMEM_L1_IBUS_OVF_INT_CLR_M (BIT(4))
#define EXTMEM_L1_IBUS_OVF_INT_CLR_V 0x1
#define EXTMEM_L1_IBUS_OVF_INT_CLR_S 4
#define EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x160)
/* EXTMEM_L1_DBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
e due to bus1 accesses L1-DCache..*/
#define EXTMEM_L1_DBUS_OVF_INT_RAW (BIT(5))
#define EXTMEM_L1_DBUS_OVF_INT_RAW_M (BIT(5))
#define EXTMEM_L1_DBUS_OVF_INT_RAW_V 0x1
#define EXTMEM_L1_DBUS_OVF_INT_RAW_S 5
/* EXTMEM_L1_IBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
e due to bus0 accesses L1-DCache..*/
#define EXTMEM_L1_IBUS_OVF_INT_RAW (BIT(4))
#define EXTMEM_L1_IBUS_OVF_INT_RAW_M (BIT(4))
#define EXTMEM_L1_IBUS_OVF_INT_RAW_V 0x1
#define EXTMEM_L1_IBUS_OVF_INT_RAW_S 4
#define EXTMEM_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x164)
/* EXTMEM_L1_DBUS_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
n L1-DCache due to bus1 accesses L1-DCache..*/
#define EXTMEM_L1_DBUS_OVF_INT_ST (BIT(5))
#define EXTMEM_L1_DBUS_OVF_INT_ST_M (BIT(5))
#define EXTMEM_L1_DBUS_OVF_INT_ST_V 0x1
#define EXTMEM_L1_DBUS_OVF_INT_ST_S 5
/* EXTMEM_L1_IBUS_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
n L1-DCache due to bus0 accesses L1-DCache..*/
#define EXTMEM_L1_IBUS_OVF_INT_ST (BIT(4))
#define EXTMEM_L1_IBUS_OVF_INT_ST_M (BIT(4))
#define EXTMEM_L1_IBUS_OVF_INT_ST_V 0x1
#define EXTMEM_L1_IBUS_OVF_INT_ST_S 4
#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x168)
/* EXTMEM_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due
to cpu accesses L1-DCache..*/
#define EXTMEM_L1_CACHE_FAIL_INT_ENA (BIT(4))
#define EXTMEM_L1_CACHE_FAIL_INT_ENA_M (BIT(4))
#define EXTMEM_L1_CACHE_FAIL_INT_ENA_V 0x1
#define EXTMEM_L1_CACHE_FAIL_INT_ENA_S 4
#define EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x16C)
/* EXTMEM_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t
o cpu accesses L1-DCache..*/
#define EXTMEM_L1_CACHE_FAIL_INT_CLR (BIT(4))
#define EXTMEM_L1_CACHE_FAIL_INT_CLR_M (BIT(4))
#define EXTMEM_L1_CACHE_FAIL_INT_CLR_V 0x1
#define EXTMEM_L1_CACHE_FAIL_INT_CLR_S 4
#define EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x170)
/* EXTMEM_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/
#define EXTMEM_L1_CACHE_FAIL_INT_RAW (BIT(4))
#define EXTMEM_L1_CACHE_FAIL_INT_RAW_M (BIT(4))
#define EXTMEM_L1_CACHE_FAIL_INT_RAW_V 0x1
#define EXTMEM_L1_CACHE_FAIL_INT_RAW_S 4
#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174)
/* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d
ue to cpu accesses L1-DCache..*/
#define EXTMEM_L1_CACHE_FAIL_INT_ST (BIT(4))
#define EXTMEM_L1_CACHE_FAIL_INT_ST_M (BIT(4))
#define EXTMEM_L1_CACHE_FAIL_INT_ST_V 0x1
#define EXTMEM_L1_CACHE_FAIL_INT_ST_S 4
#define EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x178)
/* EXTMEM_L1_DBUS_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */
/*description: The bit is used to clear dbus1 counter in L1-DCache..*/
#define EXTMEM_L1_DBUS_CNT_CLR (BIT(21))
#define EXTMEM_L1_DBUS_CNT_CLR_M (BIT(21))
#define EXTMEM_L1_DBUS_CNT_CLR_V 0x1
#define EXTMEM_L1_DBUS_CNT_CLR_S 21
/* EXTMEM_L1_IBUS_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
/*description: The bit is used to clear dbus0 counter in L1-DCache..*/
#define EXTMEM_L1_IBUS_CNT_CLR (BIT(20))
#define EXTMEM_L1_IBUS_CNT_CLR_M (BIT(20))
#define EXTMEM_L1_IBUS_CNT_CLR_V 0x1
#define EXTMEM_L1_IBUS_CNT_CLR_S 20
/* EXTMEM_L1_DBUS_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The bit is used to enable dbus1 counter in L1-DCache..*/
#define EXTMEM_L1_DBUS_CNT_ENA (BIT(5))
#define EXTMEM_L1_DBUS_CNT_ENA_M (BIT(5))
#define EXTMEM_L1_DBUS_CNT_ENA_V 0x1
#define EXTMEM_L1_DBUS_CNT_ENA_S 5
/* EXTMEM_L1_IBUS_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable dbus0 counter in L1-DCache..*/
#define EXTMEM_L1_IBUS_CNT_ENA (BIT(4))
#define EXTMEM_L1_IBUS_CNT_ENA_M (BIT(4))
#define EXTMEM_L1_IBUS_CNT_ENA_V 0x1
#define EXTMEM_L1_IBUS_CNT_ENA_S 4
#define EXTMEM_L1_IBUS_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1BC)
/* EXTMEM_L1_IBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of hits when bus0 accesses L1-Cache..*/
#define EXTMEM_L1_IBUS_HIT_CNT 0xFFFFFFFF
#define EXTMEM_L1_IBUS_HIT_CNT_M ((EXTMEM_L1_IBUS_HIT_CNT_V)<<(EXTMEM_L1_IBUS_HIT_CNT_S))
#define EXTMEM_L1_IBUS_HIT_CNT_V 0xFFFFFFFF
#define EXTMEM_L1_IBUS_HIT_CNT_S 0
#define EXTMEM_L1_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C0)
/* EXTMEM_L1_IBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of missing when bus0 accesses L1-Cache..*/
#define EXTMEM_L1_IBUS_MISS_CNT 0xFFFFFFFF
#define EXTMEM_L1_IBUS_MISS_CNT_M ((EXTMEM_L1_IBUS_MISS_CNT_V)<<(EXTMEM_L1_IBUS_MISS_CNT_S))
#define EXTMEM_L1_IBUS_MISS_CNT_V 0xFFFFFFFF
#define EXTMEM_L1_IBUS_MISS_CNT_S 0
#define EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C4)
/* EXTMEM_L1_IBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/
#define EXTMEM_L1_IBUS_CONFLICT_CNT 0xFFFFFFFF
#define EXTMEM_L1_IBUS_CONFLICT_CNT_M ((EXTMEM_L1_IBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_IBUS_CONFLICT_CNT_S))
#define EXTMEM_L1_IBUS_CONFLICT_CNT_V 0xFFFFFFFF
#define EXTMEM_L1_IBUS_CONFLICT_CNT_S 0
#define EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C8)
/* EXTMEM_L1_IBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
bus0 accessing L1-Cache..*/
#define EXTMEM_L1_IBUS_NXTLVL_CNT 0xFFFFFFFF
#define EXTMEM_L1_IBUS_NXTLVL_CNT_M ((EXTMEM_L1_IBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_IBUS_NXTLVL_CNT_S))
#define EXTMEM_L1_IBUS_NXTLVL_CNT_V 0xFFFFFFFF
#define EXTMEM_L1_IBUS_NXTLVL_CNT_S 0
#define EXTMEM_L1_DBUS_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1CC)
/* EXTMEM_L1_DBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of hits when bus1 accesses L1-Cache..*/
#define EXTMEM_L1_DBUS_HIT_CNT 0xFFFFFFFF
#define EXTMEM_L1_DBUS_HIT_CNT_M ((EXTMEM_L1_DBUS_HIT_CNT_V)<<(EXTMEM_L1_DBUS_HIT_CNT_S))
#define EXTMEM_L1_DBUS_HIT_CNT_V 0xFFFFFFFF
#define EXTMEM_L1_DBUS_HIT_CNT_S 0
#define EXTMEM_L1_DBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D0)
/* EXTMEM_L1_DBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of missing when bus1 accesses L1-Cache..*/
#define EXTMEM_L1_DBUS_MISS_CNT 0xFFFFFFFF
#define EXTMEM_L1_DBUS_MISS_CNT_M ((EXTMEM_L1_DBUS_MISS_CNT_V)<<(EXTMEM_L1_DBUS_MISS_CNT_S))
#define EXTMEM_L1_DBUS_MISS_CNT_V 0xFFFFFFFF
#define EXTMEM_L1_DBUS_MISS_CNT_S 0
#define EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D4)
/* EXTMEM_L1_DBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/
#define EXTMEM_L1_DBUS_CONFLICT_CNT 0xFFFFFFFF
#define EXTMEM_L1_DBUS_CONFLICT_CNT_M ((EXTMEM_L1_DBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_DBUS_CONFLICT_CNT_S))
#define EXTMEM_L1_DBUS_CONFLICT_CNT_V 0xFFFFFFFF
#define EXTMEM_L1_DBUS_CONFLICT_CNT_S 0
#define EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D8)
/* EXTMEM_L1_DBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
bus1 accessing L1-Cache..*/
#define EXTMEM_L1_DBUS_NXTLVL_CNT 0xFFFFFFFF
#define EXTMEM_L1_DBUS_NXTLVL_CNT_M ((EXTMEM_L1_DBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_DBUS_NXTLVL_CNT_S))
#define EXTMEM_L1_DBUS_NXTLVL_CNT_V 0xFFFFFFFF
#define EXTMEM_L1_DBUS_NXTLVL_CNT_S 0
#define EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x21C)
/* EXTMEM_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: The register records the attribution of fail-access when cache accesses L1-Cache
..*/
#define EXTMEM_L1_CACHE_FAIL_ATTR 0x0000FFFF
#define EXTMEM_L1_CACHE_FAIL_ATTR_M ((EXTMEM_L1_CACHE_FAIL_ATTR_V)<<(EXTMEM_L1_CACHE_FAIL_ATTR_S))
#define EXTMEM_L1_CACHE_FAIL_ATTR_V 0xFFFF
#define EXTMEM_L1_CACHE_FAIL_ATTR_S 16
/* EXTMEM_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/
#define EXTMEM_L1_CACHE_FAIL_ID 0x0000FFFF
#define EXTMEM_L1_CACHE_FAIL_ID_M ((EXTMEM_L1_CACHE_FAIL_ID_V)<<(EXTMEM_L1_CACHE_FAIL_ID_S))
#define EXTMEM_L1_CACHE_FAIL_ID_V 0xFFFF
#define EXTMEM_L1_CACHE_FAIL_ID_S 0
#define EXTMEM_L1_CACHE_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x220)
/* EXTMEM_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The register records the address of fail-access when cache accesses L1-Cache..*/
#define EXTMEM_L1_CACHE_FAIL_ADDR 0xFFFFFFFF
#define EXTMEM_L1_CACHE_FAIL_ADDR_M ((EXTMEM_L1_CACHE_FAIL_ADDR_V)<<(EXTMEM_L1_CACHE_FAIL_ADDR_S))
#define EXTMEM_L1_CACHE_FAIL_ADDR_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_FAIL_ADDR_S 0
#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x224)
/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of Cache sync-operation error..*/
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA (BIT(13))
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_M (BIT(13))
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_V 0x1
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_S 13
/* EXTMEM_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/
#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA (BIT(11))
#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_M (BIT(11))
#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_V 0x1
#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_S 11
/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of Cache sync-operation done..*/
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA (BIT(6))
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_M (BIT(6))
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_V 0x1
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_S 6
/* EXTMEM_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op
eration is done, interrupt occurs..*/
#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA (BIT(4))
#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_M (BIT(4))
#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_V 0x1
#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_S 4
#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x228)
/* EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt of Cache sync-operation error..*/
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR (BIT(13))
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_M (BIT(13))
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_V 0x1
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_S 13
/* EXTMEM_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/
#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR (BIT(11))
#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_M (BIT(11))
#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_V 0x1
#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_S 11
/* EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is
done..*/
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR (BIT(6))
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_M (BIT(6))
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_V 0x1
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_S 6
/* EXTMEM_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat
ion is done..*/
#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR (BIT(4))
#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_M (BIT(4))
#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_V 0x1
#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_S 4
#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x22C)
/* EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc
curs..*/
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW (BIT(13))
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_M (BIT(13))
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_V 0x1
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_S 13
/* EXTMEM_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er
ror occurs..*/
#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW (BIT(11))
#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_M (BIT(11))
#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_V 0x1
#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_S 11
/* EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW (BIT(6))
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_M (BIT(6))
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_V 0x1
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_S 6
/* EXTMEM_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
done..*/
#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW (BIT(4))
#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_M (BIT(4))
#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_V 0x1
#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_S 4
#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x230)
/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST (BIT(13))
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_M (BIT(13))
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V 0x1
#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S 13
/* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro
r..*/
#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST (BIT(11))
#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M (BIT(11))
#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_V 0x1
#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_S 11
/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o
peration is done..*/
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST (BIT(6))
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_M (BIT(6))
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_V 0x1
#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_S 6
/* EXTMEM_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre
load-operation is done..*/
#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST (BIT(4))
#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_M (BIT(4))
#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_V 0x1
#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_S 4
#define EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_EXTMEM_BASE + 0x234)
/* EXTMEM_L1_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: The values 0-2 are available which means sync map, command conflict and size are
error in Cache System..*/
#define EXTMEM_L1_CACHE_SYNC_ERR_CODE 0x00000003
#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_M ((EXTMEM_L1_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_L1_CACHE_SYNC_ERR_CODE_S))
#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_V 0x3
#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_S 12
/* EXTMEM_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/
#define EXTMEM_L1_CACHE_PLD_ERR_CODE 0x00000003
#define EXTMEM_L1_CACHE_PLD_ERR_CODE_M ((EXTMEM_L1_CACHE_PLD_ERR_CODE_V)<<(EXTMEM_L1_CACHE_PLD_ERR_CODE_S))
#define EXTMEM_L1_CACHE_PLD_ERR_CODE_V 0x3
#define EXTMEM_L1_CACHE_PLD_ERR_CODE_S 8
#define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238)
/* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl
y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
#define EXTMEM_L1_CACHE_SYNC_RST (BIT(4))
#define EXTMEM_L1_CACHE_SYNC_RST_M (BIT(4))
#define EXTMEM_L1_CACHE_SYNC_RST_V 0x1
#define EXTMEM_L1_CACHE_SYNC_RST_S 4
#define EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x23C)
/* EXTMEM_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should
only be used to initialize preload-logic when some fatal error of preload-logic
occurs..*/
#define EXTMEM_L1_CACHE_PLD_RST (BIT(4))
#define EXTMEM_L1_CACHE_PLD_RST_M (BIT(4))
#define EXTMEM_L1_CACHE_PLD_RST_V 0x1
#define EXTMEM_L1_CACHE_PLD_RST_S 4
#define EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_EXTMEM_BASE + 0x240)
/* EXTMEM_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au
toload will not work in L1-Cache. This bit should not be active when autoload wo
rks in L1-Cache..*/
#define EXTMEM_L1_CACHE_ALD_BUF_CLR (BIT(4))
#define EXTMEM_L1_CACHE_ALD_BUF_CLR_M (BIT(4))
#define EXTMEM_L1_CACHE_ALD_BUF_CLR_V 0x1
#define EXTMEM_L1_CACHE_ALD_BUF_CLR_S 4
#define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244)
/* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
llocate request is responsed but not completed..*/
#define EXTMEM_L1_CACHE_UNALLOC_CLR (BIT(4))
#define EXTMEM_L1_CACHE_UNALLOC_CLR_M (BIT(4))
#define EXTMEM_L1_CACHE_UNALLOC_CLR_V 0x1
#define EXTMEM_L1_CACHE_UNALLOC_CLR_S 4
#define EXTMEM_L1_CACHE_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x248)
/* EXTMEM_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi
th the others fields inside this register..*/
#define EXTMEM_L1_CACHE_MEM_OBJECT (BIT(10))
#define EXTMEM_L1_CACHE_MEM_OBJECT_M (BIT(10))
#define EXTMEM_L1_CACHE_MEM_OBJECT_V 0x1
#define EXTMEM_L1_CACHE_MEM_OBJECT_S 10
/* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit
h the others fields inside this register..*/
#define EXTMEM_L1_CACHE_TAG_OBJECT (BIT(4))
#define EXTMEM_L1_CACHE_TAG_OBJECT_M (BIT(4))
#define EXTMEM_L1_CACHE_TAG_OBJECT_V 0x1
#define EXTMEM_L1_CACHE_TAG_OBJECT_S 4
#define EXTMEM_L1_CACHE_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x24C)
/* EXTMEM_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
: way1, 2: way2, 3: way3, ?, 7: way7..*/
#define EXTMEM_L1_CACHE_WAY_OBJECT 0x00000007
#define EXTMEM_L1_CACHE_WAY_OBJECT_M ((EXTMEM_L1_CACHE_WAY_OBJECT_V)<<(EXTMEM_L1_CACHE_WAY_OBJECT_S))
#define EXTMEM_L1_CACHE_WAY_OBJECT_V 0x7
#define EXTMEM_L1_CACHE_WAY_OBJECT_S 0
#define EXTMEM_L1_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250)
/* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
/*description: Those bits stores the virtual address which will decide where inside the specifi
ed tag memory object will be accessed..*/
#define EXTMEM_L1_CACHE_VADDR 0xFFFFFFFF
#define EXTMEM_L1_CACHE_VADDR_M ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S))
#define EXTMEM_L1_CACHE_VADDR_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_VADDR_S 0
#define EXTMEM_L1_CACHE_DEBUG_BUS_REG (DR_REG_EXTMEM_BASE + 0x254)
/* EXTMEM_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */
/*description: This is a constant place where we can write data to or read data from the tag/da
ta memory on the specified cache..*/
#define EXTMEM_L1_CACHE_DEBUG_BUS 0xFFFFFFFF
#define EXTMEM_L1_CACHE_DEBUG_BUS_M ((EXTMEM_L1_CACHE_DEBUG_BUS_V)<<(EXTMEM_L1_CACHE_DEBUG_BUS_S))
#define EXTMEM_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFF
#define EXTMEM_L1_CACHE_DEBUG_BUS_S 0
#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC)
/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */
/*description: version control register. Note that this default value stored is the latest date
when the hardware logic was updated..*/
#define EXTMEM_DATE 0x0FFFFFFF
#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
#define EXTMEM_DATE_V 0xFFFFFFF
#define EXTMEM_DATE_S 0
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadeltan register
* Duty Cycle Configure Register of SDMn
*/
typedef union {
struct {
/** sd0_in : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t sd0_in:8;
/** sd0_prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t sd0_prescale:8;
uint32_t reserved_16:16;
};
uint32_t val;
} gpiosd_sigmadeltan_reg_t;
/** Type of sigmadelta_misc register
* MISC Register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** function_clk_en : R/W; bitpos: [30]; default: 0;
* Clock enable bit of sigma delta modulation.
*/
uint32_t function_clk_en:1;
/** spi_swap : R/W; bitpos: [31]; default: 0;
* Reserved.
*/
uint32_t spi_swap:1;
};
uint32_t val;
} gpiosd_sigmadelta_misc_reg_t;
/** Group: Glitch filter Configure Registers */
/** Type of glitch_filter_chn register
* Glitch Filter Configure Register of Channeln
*/
typedef union {
struct {
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t filter_ch0_en:1;
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t filter_ch0_input_io_num:6;
/** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t filter_ch0_window_thres:6;
/** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
* Glitch Filter window width.
*/
uint32_t filter_ch0_window_width:6;
uint32_t reserved_19:13;
};
uint32_t val;
} gpiosd_glitch_filter_chn_reg_t;
/** Group: Etm Configure Registers */
/** Type of etm_event_chn_cfg register
* Etm Config register of Channeln
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_ch0_event_sel:6;
uint32_t reserved_6:1;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_ch0_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpiosd_etm_event_chn_cfg_reg_t;
/** Type of etm_task_p0_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio0_en:1;
/** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio0_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio1_en:1;
/** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio1_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio2_en:1;
/** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio2_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio3_en:1;
/** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio3_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p0_cfg_reg_t;
/** Type of etm_task_p1_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio4_en:1;
/** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio4_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio5_en:1;
/** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio5_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio6_en:1;
/** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio6_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio7_en:1;
/** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio7_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p1_cfg_reg_t;
/** Type of etm_task_p2_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio8_en:1;
/** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio8_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio9_en:1;
/** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio9_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio10_en:1;
/** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio10_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio11_en:1;
/** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio11_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p2_cfg_reg_t;
/** Type of etm_task_p3_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio12_en:1;
/** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio12_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio13_en:1;
/** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio13_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio14_en:1;
/** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio14_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio15_en:1;
/** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio15_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p3_cfg_reg_t;
/** Type of etm_task_p4_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio16_en:1;
/** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio16_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio17_en:1;
/** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio17_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio18_en:1;
/** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio18_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio19_en:1;
/** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio19_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p4_cfg_reg_t;
/** Type of etm_task_p5_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio20_en:1;
/** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio20_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio21_en:1;
/** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio21_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio22_en:1;
/** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio22_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio23_en:1;
/** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio23_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p5_cfg_reg_t;
/** Type of etm_task_p6_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio24_en:1;
/** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio24_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio25_en:1;
/** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio25_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio26_en:1;
/** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio26_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio27_en:1;
/** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio27_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p6_cfg_reg_t;
/** Type of etm_task_p7_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio28_en:1;
/** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio28_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio29_en:1;
/** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio29_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio30_en:1;
/** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio30_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio31_en:1;
/** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio31_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p7_cfg_reg_t;
/** Type of etm_task_p8_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio32_en:1;
/** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio32_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio33_en:1;
/** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio33_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio34_en:1;
/** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio34_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio35_en:1;
/** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio35_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p8_cfg_reg_t;
/** Type of etm_task_p9_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio36_en:1;
/** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio36_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio37_en:1;
/** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio37_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio38_en:1;
/** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio38_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio39_en:1;
/** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio39_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p9_cfg_reg_t;
/** Type of etm_task_p10_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio40_en:1;
/** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio40_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio41_en:1;
/** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio41_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio42_en:1;
/** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio42_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio43_en:1;
/** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio43_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p10_cfg_reg_t;
/** Type of etm_task_p11_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio44_en:1;
/** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio44_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio45_en:1;
/** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio45_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio46_en:1;
/** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio46_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio47_en:1;
/** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio47_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p11_cfg_reg_t;
/** Type of etm_task_p12_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio48_en:1;
/** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio48_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio49_en:1;
/** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio49_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio50_en:1;
/** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio50_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio51_en:1;
/** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio51_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p12_cfg_reg_t;
/** Type of etm_task_p13_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio52_en:1;
/** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio52_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio53_en:1;
/** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio53_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio54_en:1;
/** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio54_sel:3;
uint32_t reserved_20:12;
};
uint32_t val;
} gpiosd_etm_task_p13_cfg_reg_t;
/** Group: Version Register */
/** Type of version register
* Version Control Register
*/
typedef union {
struct {
/** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
* Version control register.
*/
uint32_t gpio_sd_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_version_reg_t;
typedef struct {
volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
uint32_t reserved_020;
volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
uint32_t reserved_028[2];
volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
uint32_t reserved_050[4];
volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
uint32_t reserved_0d8[9];
volatile gpiosd_version_reg_t version;
} gpiosd_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/gpio_sig_map.h Normal file
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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define SD_CARD_CCLK_2_PAD_OUT_IDX 0
#define SD_CARD_CCMD_2_PAD_IN_IDX 1
#define SD_CARD_CCMD_2_PAD_OUT_IDX 1
#define SD_CARD_CDATA0_2_PAD_IN_IDX 2
#define SD_CARD_CDATA0_2_PAD_OUT_IDX 2
#define SD_CARD_CDATA1_2_PAD_IN_IDX 3
#define SD_CARD_CDATA1_2_PAD_OUT_IDX 3
#define SD_CARD_CDATA2_2_PAD_IN_IDX 4
#define SD_CARD_CDATA2_2_PAD_OUT_IDX 4
#define SD_CARD_CDATA3_2_PAD_IN_IDX 5
#define SD_CARD_CDATA3_2_PAD_OUT_IDX 5
#define SD_CARD_CDATA4_2_PAD_IN_IDX 6
#define SD_CARD_CDATA4_2_PAD_OUT_IDX 6
#define SD_CARD_CDATA5_2_PAD_IN_IDX 7
#define SD_CARD_CDATA5_2_PAD_OUT_IDX 7
#define SD_CARD_CDATA6_2_PAD_IN_IDX 8
#define SD_CARD_CDATA6_2_PAD_OUT_IDX 8
#define SD_CARD_CDATA7_2_PAD_IN_IDX 9
#define SD_CARD_CDATA7_2_PAD_OUT_IDX 9
#define UART0_RXD_PAD_IN_IDX 10
#define UART0_TXD_PAD_OUT_IDX 10
#define UART0_CTS_PAD_IN_IDX 11
#define UART0_RTS_PAD_OUT_IDX 11
#define UART0_DSR_PAD_IN_IDX 12
#define UART0_DTR_PAD_OUT_IDX 12
#define UART1_RXD_PAD_IN_IDX 13
#define UART1_TXD_PAD_OUT_IDX 13
#define UART1_CTS_PAD_IN_IDX 14
#define UART1_RTS_PAD_OUT_IDX 14
#define UART1_DSR_PAD_IN_IDX 15
#define UART1_DTR_PAD_OUT_IDX 15
#define UART2_RXD_PAD_IN_IDX 16
#define UART2_TXD_PAD_OUT_IDX 16
#define UART2_CTS_PAD_IN_IDX 17
#define UART2_RTS_PAD_OUT_IDX 17
#define UART2_DSR_PAD_IN_IDX 18
#define UART2_DTR_PAD_OUT_IDX 18
#define UART3_RXD_PAD_IN_IDX 19
#define UART3_TXD_PAD_OUT_IDX 19
#define UART3_CTS_PAD_IN_IDX 20
#define UART3_RTS_PAD_OUT_IDX 20
#define UART3_DSR_PAD_IN_IDX 21
#define UART3_DTR_PAD_OUT_IDX 21
#define UART4_RXD_PAD_IN_IDX 22
#define UART4_TXD_PAD_OUT_IDX 22
#define UART4_CTS_PAD_IN_IDX 23
#define UART4_RTS_PAD_OUT_IDX 23
#define UART4_DSR_PAD_IN_IDX 24
#define UART4_DTR_PAD_OUT_IDX 24
#define I2S0_O_BCK_PAD_IN_IDX 25
#define I2S0_O_BCK_PAD_OUT_IDX 25
#define I2S0_MCLK_PAD_IN_IDX 26
#define I2S0_MCLK_PAD_OUT_IDX 26
#define I2S0_O_WS_PAD_IN_IDX 27
#define I2S0_O_WS_PAD_OUT_IDX 27
#define I2S0_I_SD_PAD_IN_IDX 28
#define I2S0_O_SD_PAD_OUT_IDX 28
#define I2S0_I_BCK_PAD_IN_IDX 29
#define I2S0_I_BCK_PAD_OUT_IDX 29
#define I2S0_I_WS_PAD_IN_IDX 30
#define I2S0_I_WS_PAD_OUT_IDX 30
#define I2S1_O_BCK_PAD_IN_IDX 31
#define I2S1_O_BCK_PAD_OUT_IDX 31
#define I2S1_MCLK_PAD_IN_IDX 32
#define I2S1_MCLK_PAD_OUT_IDX 32
#define I2S1_O_WS_PAD_IN_IDX 33
#define I2S1_O_WS_PAD_OUT_IDX 33
#define I2S1_I_SD_PAD_IN_IDX 34
#define I2S1_O_SD_PAD_OUT_IDX 34
#define I2S1_I_BCK_PAD_IN_IDX 35
#define I2S1_I_BCK_PAD_OUT_IDX 35
#define I2S1_I_WS_PAD_IN_IDX 36
#define I2S1_I_WS_PAD_OUT_IDX 36
#define I2S2_O_BCK_PAD_IN_IDX 37
#define I2S2_O_BCK_PAD_OUT_IDX 37
#define I2S2_MCLK_PAD_IN_IDX 38
#define I2S2_MCLK_PAD_OUT_IDX 38
#define I2S2_O_WS_PAD_IN_IDX 39
#define I2S2_O_WS_PAD_OUT_IDX 39
#define I2S2_I_SD_PAD_IN_IDX 40
#define I2S2_O_SD_PAD_OUT_IDX 40
#define I2S2_I_BCK_PAD_IN_IDX 41
#define I2S2_I_BCK_PAD_OUT_IDX 41
#define I2S2_I_WS_PAD_IN_IDX 42
#define I2S2_I_WS_PAD_OUT_IDX 42
#define I2S0_I_SD1_PAD_IN_IDX 43
#define I2S0_O_SD1_PAD_OUT_IDX 43
#define I2S0_I_SD2_PAD_IN_IDX 44
#define SPI2_DQS_PAD_OUT_IDX 44
#define I2S0_I_SD3_PAD_IN_IDX 45
#define SPI3_CS2_PAD_OUT_IDX 45
#define SPI3_CS1_PAD_OUT_IDX 46
#define SPI3_CK_PAD_IN_IDX 47
#define SPI3_CK_PAD_OUT_IDX 47
#define SPI3_Q_PAD_IN_IDX 48
#define SPI3_QO_PAD_OUT_IDX 48
#define SPI3_D_PAD_IN_IDX 49
#define SPI3_D_PAD_OUT_IDX 49
#define SPI3_HOLD_PAD_IN_IDX 50
#define SPI3_HOLD_PAD_OUT_IDX 50
#define SPI3_WP_PAD_IN_IDX 51
#define SPI3_WP_PAD_OUT_IDX 51
#define SPI3_CS_PAD_IN_IDX 52
#define SPI3_CS_PAD_OUT_IDX 52
#define SPI2_CK_PAD_IN_IDX 53
#define SPI2_CK_PAD_OUT_IDX 53
#define SPI2_Q_PAD_IN_IDX 54
#define SPI2_Q_PAD_OUT_IDX 54
#define SPI2_D_PAD_IN_IDX 55
#define SPI2_D_PAD_OUT_IDX 55
#define SPI2_HOLD_PAD_IN_IDX 56
#define SPI2_HOLD_PAD_OUT_IDX 56
#define SPI2_WP_PAD_IN_IDX 57
#define SPI2_WP_PAD_OUT_IDX 57
#define SPI2_IO4_PAD_IN_IDX 58
#define SPI2_IO4_PAD_OUT_IDX 58
#define SPI2_IO5_PAD_IN_IDX 59
#define SPI2_IO5_PAD_OUT_IDX 59
#define SPI2_IO6_PAD_IN_IDX 60
#define SPI2_IO6_PAD_OUT_IDX 60
#define SPI2_IO7_PAD_IN_IDX 61
#define SPI2_IO7_PAD_OUT_IDX 61
#define SPI2_CS_PAD_IN_IDX 62
#define SPI2_CS_PAD_OUT_IDX 62
#define PCNT_RST_PAD_IN0_IDX 63
#define SPI2_CS1_PAD_OUT_IDX 63
#define PCNT_RST_PAD_IN1_IDX 64
#define SPI2_CS2_PAD_OUT_IDX 64
#define PCNT_RST_PAD_IN2_IDX 65
#define SPI2_CS3_PAD_OUT_IDX 65
#define PCNT_RST_PAD_IN3_IDX 66
#define SPI2_CS4_PAD_OUT_IDX 66
#define SPI2_CS5_PAD_OUT_IDX 67
#define I2C0_SCL_PAD_IN_IDX 68
#define I2C0_SCL_PAD_OUT_IDX 68
#define I2C0_SDA_PAD_IN_IDX 69
#define I2C0_SDA_PAD_OUT_IDX 69
#define I2C1_SCL_PAD_IN_IDX 70
#define I2C1_SCL_PAD_OUT_IDX 70
#define I2C1_SDA_PAD_IN_IDX 71
#define I2C1_SDA_PAD_OUT_IDX 71
#define GPIO_SD0_OUT_IDX 72
#define GPIO_SD1_OUT_IDX 73
#define UART0_SLP_CLK_PAD_IN_IDX 74
#define GPIO_SD2_OUT_IDX 74
#define UART1_SLP_CLK_PAD_IN_IDX 75
#define GPIO_SD3_OUT_IDX 75
#define UART2_SLP_CLK_PAD_IN_IDX 76
#define GPIO_SD4_OUT_IDX 76
#define UART3_SLP_CLK_PAD_IN_IDX 77
#define GPIO_SD5_OUT_IDX 77
#define UART4_SLP_CLK_PAD_IN_IDX 78
#define GPIO_SD6_OUT_IDX 78
#define GPIO_SD7_OUT_IDX 79
#define CAN0_RX_PAD_IN_IDX 80
#define CAN0_TX_PAD_OUT_IDX 80
#define CAN0_BUS_OFF_ON_PAD_OUT_IDX 81
#define CAN0_CLKOUT_PAD_OUT_IDX 82
#define CAN1_RX_PAD_IN_IDX 83
#define CAN1_TX_PAD_OUT_IDX 83
#define CAN1_BUS_OFF_ON_PAD_OUT_IDX 84
#define CAN1_CLKOUT_PAD_OUT_IDX 85
#define CAN2_RX_PAD_IN_IDX 86
#define CAN2_TX_PAD_OUT_IDX 86
#define CAN2_BUS_OFF_ON_PAD_OUT_IDX 87
#define CAN2_CLKOUT_PAD_OUT_IDX 88
#define PWM0_SYNC0_PAD_IN_IDX 89
#define PWM0_CH0_A_PAD_OUT_IDX 89
#define PWM0_SYNC1_PAD_IN_IDX 90
#define PWM0_CH0_B_PAD_OUT_IDX 90
#define PWM0_SYNC2_PAD_IN_IDX 91
#define PWM0_CH1_A_PAD_OUT_IDX 91
#define PWM0_F0_PAD_IN_IDX 92
#define PWM0_CH1_B_PAD_OUT_IDX 92
#define PWM0_F1_PAD_IN_IDX 93
#define PWM0_CH2_A_PAD_OUT_IDX 93
#define PWM0_F2_PAD_IN_IDX 94
#define PWM0_CH2_B_PAD_OUT_IDX 94
#define PWM0_CAP0_PAD_IN_IDX 95
#define PWM1_CH0_A_PAD_OUT_IDX 95
#define PWM0_CAP1_PAD_IN_IDX 96
#define PWM1_CH0_B_PAD_OUT_IDX 96
#define PWM0_CAP2_PAD_IN_IDX 97
#define PWM1_CH1_A_PAD_OUT_IDX 97
#define PWM1_SYNC0_PAD_IN_IDX 98
#define PWM1_CH1_B_PAD_OUT_IDX 98
#define PWM1_SYNC1_PAD_IN_IDX 99
#define PWM1_CH2_A_PAD_OUT_IDX 99
#define PWM1_SYNC2_PAD_IN_IDX 100
#define PWM1_CH2_B_PAD_OUT_IDX 100
#define PWM1_F0_PAD_IN_IDX 101
#define ADP_CHRG_PAD_OUT_IDX 101
#define PWM1_F1_PAD_IN_IDX 102
#define ADP_DISCHRG_PAD_OUT_IDX 102
#define PWM1_F2_PAD_IN_IDX 103
#define ADP_PRB_EN_PAD_OUT_IDX 103
#define PWM1_CAP0_PAD_IN_IDX 104
#define ADP_SNS_EN_PAD_OUT_IDX 104
#define PWM1_CAP1_PAD_IN_IDX 105
#define TWAI0_STANDBY_PAD_OUT_IDX 105
#define PWM1_CAP2_PAD_IN_IDX 106
#define TWAI1_STANDBY_PAD_OUT_IDX 106
#define GMII_MDI_PAD_IN_IDX 107
#define TWAI2_STANDBY_PAD_OUT_IDX 107
#define GMAC_PHY_COL_PAD_IN_IDX 108
#define GMII_MDC_PAD_OUT_IDX 108
#define GMAC_PHY_CRS_PAD_IN_IDX 109
#define GMII_MDO_PAD_OUT_IDX 109
#define USB_OTG11_IDDIG_PAD_IN_IDX 110
#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX 110
#define USB_OTG11_AVALID_PAD_IN_IDX 111
#define USB_OTG11_IDPULLUP_PAD_OUT_IDX 111
#define USB_SRP_BVALID_PAD_IN_IDX 112
#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX 112
#define USB_OTG11_VBUSVALID_PAD_IN_IDX 113
#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX 113
#define USB_SRP_SESSEND_PAD_IN_IDX 114
#define USB_OTG11_DRVVBUS_PAD_OUT_IDX 114
#define USB_SRP_CHRGVBUS_PAD_OUT_IDX 115
#define OTG_DRVVBUS_PAD_OUT_IDX 116
#define ULPI_CLK_PAD_IN_IDX 117
#define RNG_CHAIN_CLK_PAD_OUT_IDX 117
#define USB_HSPHY_REFCLK_IN_IDX 118
#define HP_PROBE_TOP_OUT0_IDX 118
#define HP_PROBE_TOP_OUT1_IDX 119
#define HP_PROBE_TOP_OUT2_IDX 120
#define HP_PROBE_TOP_OUT3_IDX 121
#define HP_PROBE_TOP_OUT4_IDX 122
#define HP_PROBE_TOP_OUT5_IDX 123
#define HP_PROBE_TOP_OUT6_IDX 124
#define HP_PROBE_TOP_OUT7_IDX 125
#define SD_CARD_DETECT_N_1_PAD_IN_IDX 126
#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX 126
#define SD_CARD_DETECT_N_2_PAD_IN_IDX 127
#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX 127
#define SD_CARD_INT_N_1_PAD_IN_IDX 128
#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX 128
#define SD_CARD_INT_N_2_PAD_IN_IDX 129
#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX 129
#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX 130
#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX 130
#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX 131
#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX 131
#define SD_DATA_STROBE_1_PAD_IN_IDX 132
#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX 132
#define SD_DATA_STROBE_2_PAD_IN_IDX 133
#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX 133
#define I3C_MST_SCL_PAD_IN_IDX 134
#define I3C_MST_SCL_PAD_OUT_IDX 134
#define I3C_MST_SDA_PAD_IN_IDX 135
#define I3C_MST_SDA_PAD_OUT_IDX 135
#define I3C_SLV_SCL_PAD_IN_IDX 136
#define I3C_SLV_SCL_PAD_OUT_IDX 136
#define I3C_SLV_SDA_PAD_IN_IDX 137
#define I3C_SLV_SDA_PAD_OUT_IDX 137
#define ADP_PRB_PAD_IN_IDX 138
#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX 138
#define ADP_SNS_PAD_IN_IDX 139
#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX 139
#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX 140
#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX 140
#define PCNT_SIG_CH0_PAD_IN0_IDX 141
#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX 141
#define PCNT_SIG_CH0_PAD_IN1_IDX 142
#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX 142
#define PCNT_SIG_CH0_PAD_IN2_IDX 143
#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX 143
#define PCNT_SIG_CH0_PAD_IN3_IDX 144
#define LCD_CS_PAD_OUT_IDX 144
#define PCNT_SIG_CH1_PAD_IN0_IDX 145
#define LCD_DC_PAD_OUT_IDX 145
#define PCNT_SIG_CH1_PAD_IN1_IDX 146
#define SD_RST_N_1_PAD_OUT_IDX 146
#define PCNT_SIG_CH1_PAD_IN2_IDX 147
#define SD_RST_N_2_PAD_OUT_IDX 147
#define PCNT_SIG_CH1_PAD_IN3_IDX 148
#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX 148
#define PCNT_CTRL_CH0_PAD_IN0_IDX 149
#define LCD_PCLK_PAD_OUT_IDX 149
#define PCNT_CTRL_CH0_PAD_IN1_IDX 150
#define CAM_CLK_PAD_OUT_IDX 150
#define PCNT_CTRL_CH0_PAD_IN2_IDX 151
#define LCD_H_ENABLE_PAD_OUT_IDX 151
#define PCNT_CTRL_CH0_PAD_IN3_IDX 152
#define LCD_H_SYNC_PAD_OUT_IDX 152
#define PCNT_CTRL_CH1_PAD_IN0_IDX 153
#define LCD_V_SYNC_PAD_OUT_IDX 153
#define PCNT_CTRL_CH1_PAD_IN1_IDX 154
#define LCD_DATA_OUT_PAD_OUT0_IDX 154
#define PCNT_CTRL_CH1_PAD_IN2_IDX 155
#define LCD_DATA_OUT_PAD_OUT1_IDX 155
#define PCNT_CTRL_CH1_PAD_IN3_IDX 156
#define LCD_DATA_OUT_PAD_OUT2_IDX 156
#define LCD_DATA_OUT_PAD_OUT3_IDX 157
#define CAM_PCLK_PAD_IN_IDX 158
#define LCD_DATA_OUT_PAD_OUT4_IDX 158
#define CAM_H_ENABLE_PAD_IN_IDX 159
#define LCD_DATA_OUT_PAD_OUT5_IDX 159
#define CAM_H_SYNC_PAD_IN_IDX 160
#define LCD_DATA_OUT_PAD_OUT6_IDX 160
#define CAM_V_SYNC_PAD_IN_IDX 161
#define LCD_DATA_OUT_PAD_OUT7_IDX 161
#define CAM_DATA_IN_PAD_IN0_IDX 162
#define LCD_DATA_OUT_PAD_OUT8_IDX 162
#define CAM_DATA_IN_PAD_IN1_IDX 163
#define LCD_DATA_OUT_PAD_OUT9_IDX 163
#define CAM_DATA_IN_PAD_IN2_IDX 164
#define LCD_DATA_OUT_PAD_OUT10_IDX 164
#define CAM_DATA_IN_PAD_IN3_IDX 165
#define LCD_DATA_OUT_PAD_OUT11_IDX 165
#define CAM_DATA_IN_PAD_IN4_IDX 166
#define LCD_DATA_OUT_PAD_OUT12_IDX 166
#define CAM_DATA_IN_PAD_IN5_IDX 167
#define LCD_DATA_OUT_PAD_OUT13_IDX 167
#define CAM_DATA_IN_PAD_IN6_IDX 168
#define LCD_DATA_OUT_PAD_OUT14_IDX 168
#define CAM_DATA_IN_PAD_IN7_IDX 169
#define LCD_DATA_OUT_PAD_OUT15_IDX 169
#define CAM_DATA_IN_PAD_IN8_IDX 170
#define LCD_DATA_OUT_PAD_OUT16_IDX 170
#define CAM_DATA_IN_PAD_IN9_IDX 171
#define LCD_DATA_OUT_PAD_OUT17_IDX 171
#define CAM_DATA_IN_PAD_IN10_IDX 172
#define LCD_DATA_OUT_PAD_OUT18_IDX 172
#define CAM_DATA_IN_PAD_IN11_IDX 173
#define LCD_DATA_OUT_PAD_OUT19_IDX 173
#define CAM_DATA_IN_PAD_IN12_IDX 174
#define LCD_DATA_OUT_PAD_OUT20_IDX 174
#define CAM_DATA_IN_PAD_IN13_IDX 175
#define LCD_DATA_OUT_PAD_OUT21_IDX 175
#define CAM_DATA_IN_PAD_IN14_IDX 176
#define LCD_DATA_OUT_PAD_OUT22_IDX 176
#define CAM_DATA_IN_PAD_IN15_IDX 177
#define LCD_DATA_OUT_PAD_OUT23_IDX 177
#define GMAC_PHY_RXDV_PAD_IN_IDX 178
#define GMAC_PHY_TXEN_PAD_OUT_IDX 178
#define GMAC_PHY_RXD0_PAD_IN_IDX 179
#define GMAC_PHY_TXD0_PAD_OUT_IDX 179
#define GMAC_PHY_RXD1_PAD_IN_IDX 180
#define GMAC_PHY_TXD1_PAD_OUT_IDX 180
#define GMAC_PHY_RXD2_PAD_IN_IDX 181
#define GMAC_PHY_TXD2_PAD_OUT_IDX 181
#define GMAC_PHY_RXD3_PAD_IN_IDX 182
#define GMAC_PHY_TXD3_PAD_OUT_IDX 182
#define GMAC_PHY_RXER_PAD_IN_IDX 183
#define GMAC_PHY_TXER_PAD_OUT_IDX 183
#define GMAC_RX_CLK_PAD_IN_IDX 184
#define DBG_CH0_CLK_IDX 184
#define GMAC_TX_CLK_PAD_IN_IDX 185
#define DBG_CH1_CLK_IDX 185
#define PARLIO_RX_CLK_PAD_IN_IDX 186
#define PARLIO_RX_CLK_PAD_OUT_IDX 186
#define PARLIO_TX_CLK_PAD_IN_IDX 187
#define PARLIO_TX_CLK_PAD_OUT_IDX 187
#define PARLIO_RX_DATA0_PAD_IN_IDX 188
#define PARLIO_TX_DATA0_PAD_OUT_IDX 188
#define PARLIO_RX_DATA1_PAD_IN_IDX 189
#define PARLIO_TX_DATA1_PAD_OUT_IDX 189
#define PARLIO_RX_DATA2_PAD_IN_IDX 190
#define PARLIO_TX_DATA2_PAD_OUT_IDX 190
#define PARLIO_RX_DATA3_PAD_IN_IDX 191
#define PARLIO_TX_DATA3_PAD_OUT_IDX 191
#define PARLIO_RX_DATA4_PAD_IN_IDX 192
#define PARLIO_TX_DATA4_PAD_OUT_IDX 192
#define PARLIO_RX_DATA5_PAD_IN_IDX 193
#define PARLIO_TX_DATA5_PAD_OUT_IDX 193
#define PARLIO_RX_DATA6_PAD_IN_IDX 194
#define PARLIO_TX_DATA6_PAD_OUT_IDX 194
#define PARLIO_RX_DATA7_PAD_IN_IDX 195
#define PARLIO_TX_DATA7_PAD_OUT_IDX 195
#define PARLIO_RX_DATA8_PAD_IN_IDX 196
#define PARLIO_TX_DATA8_PAD_OUT_IDX 196
#define PARLIO_RX_DATA9_PAD_IN_IDX 197
#define PARLIO_TX_DATA9_PAD_OUT_IDX 197
#define PARLIO_RX_DATA10_PAD_IN_IDX 198
#define PARLIO_TX_DATA10_PAD_OUT_IDX 198
#define PARLIO_RX_DATA11_PAD_IN_IDX 199
#define PARLIO_TX_DATA11_PAD_OUT_IDX 199
#define PARLIO_RX_DATA12_PAD_IN_IDX 200
#define PARLIO_TX_DATA12_PAD_OUT_IDX 200
#define PARLIO_RX_DATA13_PAD_IN_IDX 201
#define PARLIO_TX_DATA13_PAD_OUT_IDX 201
#define PARLIO_RX_DATA14_PAD_IN_IDX 202
#define PARLIO_TX_DATA14_PAD_OUT_IDX 202
#define PARLIO_RX_DATA15_PAD_IN_IDX 203
#define PARLIO_TX_DATA15_PAD_OUT_IDX 203
#define HP_PROBE_TOP_OUT8_IDX 204
#define HP_PROBE_TOP_OUT9_IDX 205
#define HP_PROBE_TOP_OUT10_IDX 206
#define HP_PROBE_TOP_OUT11_IDX 207
#define HP_PROBE_TOP_OUT12_IDX 208
#define HP_PROBE_TOP_OUT13_IDX 209
#define HP_PROBE_TOP_OUT14_IDX 210
#define HP_PROBE_TOP_OUT15_IDX 211
#define CONSTANT0_PAD_OUT_IDX 212
#define CONSTANT1_PAD_OUT_IDX 213
#define CORE_GPIO_IN_PAD_IN0_IDX 214
#define CORE_GPIO_OUT_PAD_OUT0_IDX 214
#define CORE_GPIO_IN_PAD_IN1_IDX 215
#define CORE_GPIO_OUT_PAD_OUT1_IDX 215
#define CORE_GPIO_IN_PAD_IN2_IDX 216
#define CORE_GPIO_OUT_PAD_OUT2_IDX 216
#define CORE_GPIO_IN_PAD_IN3_IDX 217
#define CORE_GPIO_OUT_PAD_OUT3_IDX 217
#define CORE_GPIO_IN_PAD_IN4_IDX 218
#define CORE_GPIO_OUT_PAD_OUT4_IDX 218
#define CORE_GPIO_IN_PAD_IN5_IDX 219
#define CORE_GPIO_OUT_PAD_OUT5_IDX 219
#define CORE_GPIO_IN_PAD_IN6_IDX 220
#define CORE_GPIO_OUT_PAD_OUT6_IDX 220
#define CORE_GPIO_IN_PAD_IN7_IDX 221
#define CORE_GPIO_OUT_PAD_OUT7_IDX 221
#define CORE_GPIO_IN_PAD_IN8_IDX 222
#define CORE_GPIO_OUT_PAD_OUT8_IDX 222
#define CORE_GPIO_IN_PAD_IN9_IDX 223
#define CORE_GPIO_OUT_PAD_OUT9_IDX 223
#define CORE_GPIO_IN_PAD_IN10_IDX 224
#define CORE_GPIO_OUT_PAD_OUT10_IDX 224
#define CORE_GPIO_IN_PAD_IN11_IDX 225
#define CORE_GPIO_OUT_PAD_OUT11_IDX 225
#define CORE_GPIO_IN_PAD_IN12_IDX 226
#define CORE_GPIO_OUT_PAD_OUT12_IDX 226
#define CORE_GPIO_IN_PAD_IN13_IDX 227
#define CORE_GPIO_OUT_PAD_OUT13_IDX 227
#define CORE_GPIO_IN_PAD_IN14_IDX 228
#define CORE_GPIO_OUT_PAD_OUT14_IDX 228
#define CORE_GPIO_IN_PAD_IN15_IDX 229
#define CORE_GPIO_OUT_PAD_OUT15_IDX 229
#define CORE_GPIO_IN_PAD_IN16_IDX 230
#define CORE_GPIO_OUT_PAD_OUT16_IDX 230
#define CORE_GPIO_IN_PAD_IN17_IDX 231
#define CORE_GPIO_OUT_PAD_OUT17_IDX 231
#define CORE_GPIO_IN_PAD_IN18_IDX 232
#define CORE_GPIO_OUT_PAD_OUT18_IDX 232
#define CORE_GPIO_IN_PAD_IN19_IDX 233
#define CORE_GPIO_OUT_PAD_OUT19_IDX 233
#define CORE_GPIO_IN_PAD_IN20_IDX 234
#define CORE_GPIO_OUT_PAD_OUT20_IDX 234
#define CORE_GPIO_IN_PAD_IN21_IDX 235
#define CORE_GPIO_OUT_PAD_OUT21_IDX 235
#define CORE_GPIO_IN_PAD_IN22_IDX 236
#define CORE_GPIO_OUT_PAD_OUT22_IDX 236
#define CORE_GPIO_IN_PAD_IN23_IDX 237
#define CORE_GPIO_OUT_PAD_OUT23_IDX 237
#define CORE_GPIO_IN_PAD_IN24_IDX 238
#define CORE_GPIO_OUT_PAD_OUT24_IDX 238
#define CORE_GPIO_IN_PAD_IN25_IDX 239
#define CORE_GPIO_OUT_PAD_OUT25_IDX 239
#define CORE_GPIO_IN_PAD_IN26_IDX 240
#define CORE_GPIO_OUT_PAD_OUT26_IDX 240
#define CORE_GPIO_IN_PAD_IN27_IDX 241
#define CORE_GPIO_OUT_PAD_OUT27_IDX 241
#define CORE_GPIO_IN_PAD_IN28_IDX 242
#define CORE_GPIO_OUT_PAD_OUT28_IDX 242
#define CORE_GPIO_IN_PAD_IN29_IDX 243
#define CORE_GPIO_OUT_PAD_OUT29_IDX 243
#define CORE_GPIO_IN_PAD_IN30_IDX 244
#define CORE_GPIO_OUT_PAD_OUT30_IDX 244
#define CORE_GPIO_IN_PAD_IN31_IDX 245
#define CORE_GPIO_OUT_PAD_OUT31_IDX 245
#define RMT_SIG_PAD_IN0_IDX 246
#define RMT_SIG_PAD_OUT0_IDX 246
#define RMT_SIG_PAD_IN1_IDX 247
#define RMT_SIG_PAD_OUT1_IDX 247
#define RMT_SIG_PAD_IN2_IDX 248
#define RMT_SIG_PAD_OUT2_IDX 248
#define RMT_SIG_PAD_IN3_IDX 249
#define RMT_SIG_PAD_OUT3_IDX 249
#define SIG_IN_FUNC250_IDX 250
#define SIG_IN_FUNC250_IDX 250
#define SIG_IN_FUNC251_IDX 251
#define SIG_IN_FUNC251_IDX 251
#define SIG_IN_FUNC252_IDX 252
#define SIG_IN_FUNC252_IDX 252
#define SIG_IN_FUNC253_IDX 253
#define SIG_IN_FUNC253_IDX 253
#define SIG_IN_FUNC254_IDX 254
#define SIG_IN_FUNC254_IDX 254
#define SIG_IN_FUNC255_IDX 255
#define SIG_IN_FUNC255_IDX 255
#endif /* _SOC_GPIO_SIG_MAP_H_ */

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components/soc/esp32p4/include/soc/hardware_lock_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ATOMIC_ADDR_LOCK_REG register
* hardware lock regsiter
*/
#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
* read to acquire hardware lock, write to release hardware lock
*/
#define ATOMIC_LOCK 0x00000003U
#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATOMIC_LOCK_S)
#define ATOMIC_LOCK_V 0x00000003U
#define ATOMIC_LOCK_S 0
/** ATOMIC_LR_ADDR_REG register
* gloable lr address regsiter
*/
#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
* backup gloable address
*/
#define ATOMIC_GLOABLE_LR_ADDR 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_ADDR_M (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S)
#define ATOMIC_GLOABLE_LR_ADDR_V 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_ADDR_S 0
/** ATOMIC_LR_VALUE_REG register
* gloable lr value regsiter
*/
#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
* backup gloable value
*/
#define ATOMIC_GLOABLE_LR_VALUE 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_VALUE_M (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S)
#define ATOMIC_GLOABLE_LR_VALUE_V 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_VALUE_S 0
/** ATOMIC_LOCK_STATUS_REG register
* lock status regsiter
*/
#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
* read hareware lock status for debug
*/
#define ATOMIC_LOCK_STATUS 0x00000003U
#define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
#define ATOMIC_LOCK_STATUS_V 0x00000003U
#define ATOMIC_LOCK_STATUS_S 0
/** ATOMIC_COUNTER_REG register
* wait counter register
*/
#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10)
/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0;
* delay counter
*/
#define ATOMIC_WAIT_COUNTER 0x0000FFFFU
#define ATOMIC_WAIT_COUNTER_M (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S)
#define ATOMIC_WAIT_COUNTER_V 0x0000FFFFU
#define ATOMIC_WAIT_COUNTER_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of addr_lock register
* hardware lock regsiter
*/
typedef union {
struct {
/** lock : R/W; bitpos: [1:0]; default: 0;
* read to acquire hardware lock, write to release hardware lock
*/
uint32_t lock:2;
uint32_t reserved_2:30;
};
uint32_t val;
} atomic_addr_lock_reg_t;
/** Type of lr_addr register
* gloable lr address regsiter
*/
typedef union {
struct {
/** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0;
* backup gloable address
*/
uint32_t gloable_lr_addr:32;
};
uint32_t val;
} atomic_lr_addr_reg_t;
/** Type of lr_value register
* gloable lr value regsiter
*/
typedef union {
struct {
/** gloable_lr_value : R/W; bitpos: [31:0]; default: 0;
* backup gloable value
*/
uint32_t gloable_lr_value:32;
};
uint32_t val;
} atomic_lr_value_reg_t;
/** Type of lock_status register
* lock status regsiter
*/
typedef union {
struct {
/** lock_status : RO; bitpos: [1:0]; default: 0;
* read hareware lock status for debug
*/
uint32_t lock_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} atomic_lock_status_reg_t;
/** Type of counter register
* wait counter register
*/
typedef union {
struct {
/** wait_counter : R/W; bitpos: [15:0]; default: 0;
* delay counter
*/
uint32_t wait_counter:16;
uint32_t reserved_16:16;
};
uint32_t val;
} atomic_counter_reg_t;
typedef struct atomic_dev_t {
volatile atomic_addr_lock_reg_t addr_lock;
volatile atomic_lr_addr_reg_t lr_addr;
volatile atomic_lr_value_reg_t lr_value;
volatile atomic_lock_status_reg_t lock_status;
volatile atomic_counter_reg_t counter;
} atomic_dev_t;
extern atomic_dev_t ATOMIC_LOCKER;
#ifndef __cplusplus
_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HINF_CFG_DATA0_REG register
* Configure sdio cis content
*/
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
#define HINF_DEVICE_ID_FN1 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S)
#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_S 0
/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
#define HINF_USER_ID_FN1 0x0000FFFFU
#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S)
#define HINF_USER_ID_FN1_V 0x0000FFFFU
#define HINF_USER_ID_FN1_S 16
/** HINF_CFG_DATA1_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
#define HINF_SDIO_ENABLE (BIT(0))
#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S)
#define HINF_SDIO_ENABLE_V 0x00000001U
#define HINF_SDIO_ENABLE_S 0
/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY1 (BIT(1))
#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S)
#define HINF_SDIO_IOREADY1_V 0x00000001U
#define HINF_SDIO_IOREADY1_S 1
/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
#define HINF_HIGHSPEED_ENABLE (BIT(2))
#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S)
#define HINF_HIGHSPEED_ENABLE_V 0x00000001U
#define HINF_HIGHSPEED_ENABLE_S 2
/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
#define HINF_HIGHSPEED_MODE (BIT(3))
#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S)
#define HINF_HIGHSPEED_MODE_V 0x00000001U
#define HINF_HIGHSPEED_MODE_S 3
/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
#define HINF_SDIO_CD_ENABLE (BIT(4))
#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S)
#define HINF_SDIO_CD_ENABLE_V 0x00000001U
#define HINF_SDIO_CD_ENABLE_S 4
/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY2 (BIT(5))
#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S)
#define HINF_SDIO_IOREADY2_V 0x00000001U
#define HINF_SDIO_IOREADY2_S 5
/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
#define HINF_SDIO_INT_MASK (BIT(6))
#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S)
#define HINF_SDIO_INT_MASK_V 0x00000001U
#define HINF_SDIO_INT_MASK_S 6
/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
#define HINF_IOENABLE2 (BIT(7))
#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S)
#define HINF_IOENABLE2_V 0x00000001U
#define HINF_IOENABLE2_S 7
/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
#define HINF_CD_DISABLE (BIT(8))
#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S)
#define HINF_CD_DISABLE_V 0x00000001U
#define HINF_CD_DISABLE_S 8
/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
#define HINF_FUNC1_EPS (BIT(9))
#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S)
#define HINF_FUNC1_EPS_V 0x00000001U
#define HINF_FUNC1_EPS_S 9
/** HINF_EMP : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
#define HINF_EMP (BIT(10))
#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S)
#define HINF_EMP_V 0x00000001U
#define HINF_EMP_S 10
/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
#define HINF_IOENABLE1 (BIT(11))
#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S)
#define HINF_IOENABLE1_V 0x00000001U
#define HINF_IOENABLE1_S 11
/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
#define HINF_SDIO_VER 0x00000FFFU
#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S)
#define HINF_SDIO_VER_V 0x00000FFFU
#define HINF_SDIO_VER_S 12
/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
#define HINF_FUNC2_EPS (BIT(24))
#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S)
#define HINF_FUNC2_EPS_V 0x00000001U
#define HINF_FUNC2_EPS_S 24
/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
#define HINF_SDIO20_CONF 0x0000007FU
#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S)
#define HINF_SDIO20_CONF_V 0x0000007FU
#define HINF_SDIO20_CONF_S 25
/** HINF_CFG_TIMING_REG register
* Timing configuration registers
*/
#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
#define HINF_NCRC 0x00000007U
#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S)
#define HINF_NCRC_V 0x00000007U
#define HINF_NCRC_S 0
/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S)
#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_S 3
/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S)
#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_S 10
/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
#define HINF_SDCLK_STOP_THRES 0x000007FFU
#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S)
#define HINF_SDCLK_STOP_THRES_V 0x000007FFU
#define HINF_SDCLK_STOP_THRES_S 16
/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S)
#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_S 28
/** HINF_CFG_UPDATE_REG register
* update sdio configurations
*/
#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
#define HINF_CONF_UPDATE (BIT(0))
#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S)
#define HINF_CONF_UPDATE_V 0x00000001U
#define HINF_CONF_UPDATE_S 0
/** HINF_CFG_DATA7_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
#define HINF_PIN_STATE 0x000000FFU
#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S)
#define HINF_PIN_STATE_V 0x000000FFU
#define HINF_PIN_STATE_S 0
/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
#define HINF_CHIP_STATE 0x000000FFU
#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S)
#define HINF_CHIP_STATE_V 0x000000FFU
#define HINF_CHIP_STATE_S 8
/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
#define HINF_SDIO_RST (BIT(16))
#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S)
#define HINF_SDIO_RST_V 0x00000001U
#define HINF_SDIO_RST_S 16
/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
#define HINF_SDIO_IOREADY0 (BIT(17))
#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S)
#define HINF_SDIO_IOREADY0_V 0x00000001U
#define HINF_SDIO_IOREADY0_S 17
/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
#define HINF_SDIO_MEM_PD (BIT(18))
#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S)
#define HINF_SDIO_MEM_PD_V 0x00000001U
#define HINF_SDIO_MEM_PD_S 18
/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
#define HINF_ESDIO_DATA1_INT_EN (BIT(19))
#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S)
#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U
#define HINF_ESDIO_DATA1_INT_EN_S 19
/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20))
#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S)
#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_SW_S 20
/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21))
#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S)
#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U
#define HINF_DDR50_BLK_LEN_FIX_EN_S 21
/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
#define HINF_CLK_EN (BIT(22))
#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S)
#define HINF_CLK_EN_V 0x00000001U
#define HINF_CLK_EN_S 22
/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
#define HINF_SDDR50 (BIT(23))
#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S)
#define HINF_SDDR50_V 0x00000001U
#define HINF_SDDR50_S 23
/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
#define HINF_SSDR104 (BIT(24))
#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S)
#define HINF_SSDR104_V 0x00000001U
#define HINF_SSDR104_S 24
/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
#define HINF_SSDR50 (BIT(25))
#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S)
#define HINF_SSDR50_V 0x00000001U
#define HINF_SSDR50_S 25
/** HINF_SDTD : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
#define HINF_SDTD (BIT(26))
#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S)
#define HINF_SDTD_V 0x00000001U
#define HINF_SDTD_S 26
/** HINF_SDTA : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
#define HINF_SDTA (BIT(27))
#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S)
#define HINF_SDTA_V 0x00000001U
#define HINF_SDTA_S 27
/** HINF_SDTC : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
#define HINF_SDTC (BIT(28))
#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S)
#define HINF_SDTC_V 0x00000001U
#define HINF_SDTC_S 28
/** HINF_SAI : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
#define HINF_SAI (BIT(29))
#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S)
#define HINF_SAI_V 0x00000001U
#define HINF_SAI_S 29
/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
#define HINF_SDIO_WAKEUP_CLR (BIT(30))
#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S)
#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U
#define HINF_SDIO_WAKEUP_CLR_S 30
/** HINF_CIS_CONF_W0_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
#define HINF_CIS_CONF_W0 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S)
#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_S 0
/** HINF_CIS_CONF_W1_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
#define HINF_CIS_CONF_W1 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S)
#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_S 0
/** HINF_CIS_CONF_W2_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
#define HINF_CIS_CONF_W2 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S)
#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_S 0
/** HINF_CIS_CONF_W3_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
#define HINF_CIS_CONF_W3 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S)
#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_S 0
/** HINF_CIS_CONF_W4_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
#define HINF_CIS_CONF_W4 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S)
#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_S 0
/** HINF_CIS_CONF_W5_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34)
/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
#define HINF_CIS_CONF_W5 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S)
#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_S 0
/** HINF_CIS_CONF_W6_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38)
/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
#define HINF_CIS_CONF_W6 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S)
#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_S 0
/** HINF_CIS_CONF_W7_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c)
/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
#define HINF_CIS_CONF_W7 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S)
#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_S 0
/** HINF_CFG_DATA16_REG register
* SDIO cis configuration register
*/
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
#define HINF_DEVICE_ID_FN2 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S)
#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_S 0
/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
#define HINF_USER_ID_FN2 0x0000FFFFU
#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S)
#define HINF_USER_ID_FN2_V 0x0000FFFFU
#define HINF_USER_ID_FN2_S 16
/** HINF_CFG_UHS1_INT_MODE_REG register
* configure int to start and end ahead of time in uhs1 mode
*/
#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44)
/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_END_AHEAD_MODE 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S)
#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_S 0
/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_END_AHEAD_MODE 0x00000003U
#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S)
#define HINF_INT_END_AHEAD_MODE_V 0x00000003U
#define HINF_INT_END_AHEAD_MODE_S 2
/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S)
#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_S 4
/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_ST_AHEAD_MODE 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S)
#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_S 6
/** HINF_CONF_STATUS_REG register
* func0 config0 status
*/
#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54)
/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
#define HINF_FUNC0_CONFIG0 0x000000FFU
#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S)
#define HINF_FUNC0_CONFIG0_V 0x000000FFU
#define HINF_FUNC0_CONFIG0_S 0
/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
#define HINF_SDR25_ST (BIT(8))
#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S)
#define HINF_SDR25_ST_V 0x00000001U
#define HINF_SDR25_ST_S 8
/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
#define HINF_SDR50_ST (BIT(9))
#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S)
#define HINF_SDR50_ST_V 0x00000001U
#define HINF_SDR50_ST_S 9
/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
#define HINF_SDR104_ST (BIT(10))
#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S)
#define HINF_SDR104_ST_V 0x00000001U
#define HINF_SDR104_ST_S 10
/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
#define HINF_DDR50_ST (BIT(11))
#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S)
#define HINF_DDR50_ST_V 0x00000001U
#define HINF_DDR50_ST_S 11
/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
#define HINF_TUNE_ST 0x00000007U
#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S)
#define HINF_TUNE_ST_V 0x00000007U
#define HINF_TUNE_ST_S 12
/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15))
#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S)
#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_ST_S 15
/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
#define HINF_SDIO_SWITCH_END (BIT(16))
#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S)
#define HINF_SDIO_SWITCH_END_V 0x00000001U
#define HINF_SDIO_SWITCH_END_S 16
/** HINF_SDIO_SLAVE_ECO_LOW_REG register
* sdio_slave redundant control registers
*/
#define HINF_SDIO_SLAVE_ECO_LOW_REG (DR_REG_HINF_BASE + 0xa4)
/** HINF_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_RDN_ECO_LOW 0xFFFFFFFFU
#define HINF_RDN_ECO_LOW_M (HINF_RDN_ECO_LOW_V << HINF_RDN_ECO_LOW_S)
#define HINF_RDN_ECO_LOW_V 0xFFFFFFFFU
#define HINF_RDN_ECO_LOW_S 0
/** HINF_SDIO_SLAVE_ECO_HIGH_REG register
* sdio_slave redundant control registers
*/
#define HINF_SDIO_SLAVE_ECO_HIGH_REG (DR_REG_HINF_BASE + 0xa8)
/** HINF_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* redundant registers for sdio_slave
*/
#define HINF_RDN_ECO_HIGH 0xFFFFFFFFU
#define HINF_RDN_ECO_HIGH_M (HINF_RDN_ECO_HIGH_V << HINF_RDN_ECO_HIGH_S)
#define HINF_RDN_ECO_HIGH_V 0xFFFFFFFFU
#define HINF_RDN_ECO_HIGH_S 0
/** HINF_SDIO_SLAVE_ECO_CONF_REG register
* sdio_slave redundant control registers
*/
#define HINF_SDIO_SLAVE_ECO_CONF_REG (DR_REG_HINF_BASE + 0xac)
/** HINF_SDIO_SLAVE_RDN_RESULT : RO; bitpos: [0]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_RDN_RESULT (BIT(0))
#define HINF_SDIO_SLAVE_RDN_RESULT_M (HINF_SDIO_SLAVE_RDN_RESULT_V << HINF_SDIO_SLAVE_RDN_RESULT_S)
#define HINF_SDIO_SLAVE_RDN_RESULT_V 0x00000001U
#define HINF_SDIO_SLAVE_RDN_RESULT_S 0
/** HINF_SDIO_SLAVE_RDN_ENA : R/W; bitpos: [1]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_RDN_ENA (BIT(1))
#define HINF_SDIO_SLAVE_RDN_ENA_M (HINF_SDIO_SLAVE_RDN_ENA_V << HINF_SDIO_SLAVE_RDN_ENA_S)
#define HINF_SDIO_SLAVE_RDN_ENA_V 0x00000001U
#define HINF_SDIO_SLAVE_RDN_ENA_S 1
/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT : RO; bitpos: [2]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT (BIT(2))
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_M (HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S)
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_V 0x00000001U
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_RESULT_S 2
/** HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA : R/W; bitpos: [3]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA (BIT(3))
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_M (HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V << HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S)
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_V 0x00000001U
#define HINF_SDIO_SLAVE_SDIO_CLK_RDN_ENA_S 3
/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT : RO; bitpos: [4]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT (BIT(4))
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_M (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S)
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_V 0x00000001U
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_S 4
/** HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA : R/W; bitpos: [5]; default: 0;
* redundant registers for sdio_slave
*/
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA (BIT(5))
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_M (HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V << HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S)
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_V 0x00000001U
#define HINF_SDIO_SLAVE_SDCLK_PAD_RDN_ENA_S 5
/** HINF_SDIO_SLAVE_LDO_CONF_REG register
* sdio slave ldo control register
*/
#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0)
/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
#define HINF_LDO_READY_CTL_IN_EN (BIT(0))
#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S)
#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U
#define HINF_LDO_READY_CTL_IN_EN_S 0
/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
#define HINF_LDO_READY_THRES 0x0000001FU
#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S)
#define HINF_LDO_READY_THRES_V 0x0000001FU
#define HINF_LDO_READY_THRES_S 1
/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
#define HINF_LDO_READY_IGNORE_EN (BIT(6))
#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S)
#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U
#define HINF_LDO_READY_IGNORE_EN_S 6
/** HINF_SDIO_DATE_REG register
* ******* Description ***********
*/
#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc)
/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208;
* sdio version date.
*/
#define HINF_SDIO_DATE 0xFFFFFFFFU
#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S)
#define HINF_SDIO_DATE_V 0xFFFFFFFFU
#define HINF_SDIO_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/hinf_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration registers */
/** Type of cfg_data0 register
* Configure sdio cis content
*/
typedef union {
struct {
/** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
uint32_t device_id_fn1:16;
/** user_id_fn1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
uint32_t user_id_fn1:16;
};
uint32_t val;
} hinf_cfg_data0_reg_t;
/** Type of cfg_data1 register
* SDIO configuration register
*/
typedef union {
struct {
/** sdio_enable : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
uint32_t sdio_enable:1;
/** sdio_ioready1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready1:1;
/** highspeed_enable : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
uint32_t highspeed_enable:1;
/** highspeed_mode : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
uint32_t highspeed_mode:1;
/** sdio_cd_enable : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
uint32_t sdio_cd_enable:1;
/** sdio_ioready2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready2:1;
/** sdio_int_mask : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
uint32_t sdio_int_mask:1;
/** ioenable2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
uint32_t ioenable2:1;
/** cd_disable : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
uint32_t cd_disable:1;
/** func1_eps : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
uint32_t func1_eps:1;
/** emp : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
uint32_t emp:1;
/** ioenable1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
uint32_t ioenable1:1;
/** sdio_ver : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
uint32_t sdio_ver:12;
/** func2_eps : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
uint32_t func2_eps:1;
/** sdio20_conf : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
uint32_t sdio20_conf:7;
};
uint32_t val;
} hinf_cfg_data1_reg_t;
/** Type of cfg_timing register
* Timing configuration registers
*/
typedef union {
struct {
/** ncrc : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
uint32_t ncrc:3;
/** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
uint32_t pst_end_cmd_low_value:7;
/** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
uint32_t pst_end_data_low_value:6;
/** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
uint32_t sdclk_stop_thres:11;
uint32_t reserved_27:1;
/** sample_clk_divider : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
uint32_t sample_clk_divider:4;
};
uint32_t val;
} hinf_cfg_timing_reg_t;
/** Type of cfg_update register
* update sdio configurations
*/
typedef union {
struct {
/** conf_update : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
uint32_t conf_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hinf_cfg_update_reg_t;
/** Type of cfg_data7 register
* SDIO configuration register
*/
typedef union {
struct {
/** pin_state : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
uint32_t pin_state:8;
/** chip_state : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
uint32_t chip_state:8;
/** sdio_rst : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
uint32_t sdio_rst:1;
/** sdio_ioready0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
uint32_t sdio_ioready0:1;
/** sdio_mem_pd : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
uint32_t sdio_mem_pd:1;
/** esdio_data1_int_en : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
uint32_t esdio_data1_int_en:1;
/** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
uint32_t sdio_switch_volt_sw:1;
/** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
uint32_t ddr50_blk_len_fix_en:1;
/** clk_en : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
uint32_t clk_en:1;
/** sddr50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
uint32_t sddr50:1;
/** ssdr104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
uint32_t ssdr104:1;
/** ssdr50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
uint32_t ssdr50:1;
/** sdtd : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
uint32_t sdtd:1;
/** sdta : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
uint32_t sdta:1;
/** sdtc : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
uint32_t sdtc:1;
/** sai : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
uint32_t sai:1;
/** sdio_wakeup_clr : WT; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
uint32_t sdio_wakeup_clr:1;
uint32_t reserved_31:1;
};
uint32_t val;
} hinf_cfg_data7_reg_t;
/** Type of cis_conf_w0 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
uint32_t cis_conf_w0:32;
};
uint32_t val;
} hinf_cis_conf_w0_reg_t;
/** Type of cis_conf_w1 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
uint32_t cis_conf_w1:32;
};
uint32_t val;
} hinf_cis_conf_w1_reg_t;
/** Type of cis_conf_w2 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
uint32_t cis_conf_w2:32;
};
uint32_t val;
} hinf_cis_conf_w2_reg_t;
/** Type of cis_conf_w3 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
uint32_t cis_conf_w3:32;
};
uint32_t val;
} hinf_cis_conf_w3_reg_t;
/** Type of cis_conf_w4 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
uint32_t cis_conf_w4:32;
};
uint32_t val;
} hinf_cis_conf_w4_reg_t;
/** Type of cis_conf_w5 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
uint32_t cis_conf_w5:32;
};
uint32_t val;
} hinf_cis_conf_w5_reg_t;
/** Type of cis_conf_w6 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
uint32_t cis_conf_w6:32;
};
uint32_t val;
} hinf_cis_conf_w6_reg_t;
/** Type of cis_conf_w7 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
uint32_t cis_conf_w7:32;
};
uint32_t val;
} hinf_cis_conf_w7_reg_t;
/** Type of cfg_data16 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
uint32_t device_id_fn2:16;
/** user_id_fn2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
uint32_t user_id_fn2:16;
};
uint32_t val;
} hinf_cfg_data16_reg_t;
/** Type of cfg_uhs1_int_mode register
* configure int to start and end ahead of time in uhs1 mode
*/
typedef union {
struct {
/** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_end_ahead_mode:2;
/** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_end_ahead_mode:2;
/** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_st_ahead_mode:2;
/** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_st_ahead_mode:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hinf_cfg_uhs1_int_mode_reg_t;
/** Type of sdio_slave_eco_low register
* sdio_slave redundant control registers
*/
typedef union {
struct {
/** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t rdn_eco_low:32;
};
uint32_t val;
} hinf_sdio_slave_eco_low_reg_t;
/** Type of sdio_slave_eco_high register
* sdio_slave redundant control registers
*/
typedef union {
struct {
/** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
* redundant registers for sdio_slave
*/
uint32_t rdn_eco_high:32;
};
uint32_t val;
} hinf_sdio_slave_eco_high_reg_t;
/** Type of sdio_slave_eco_conf register
* sdio_slave redundant control registers
*/
typedef union {
struct {
/** sdio_slave_rdn_result : RO; bitpos: [0]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_rdn_result:1;
/** sdio_slave_rdn_ena : R/W; bitpos: [1]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_rdn_ena:1;
/** sdio_slave_sdio_clk_rdn_result : RO; bitpos: [2]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_sdio_clk_rdn_result:1;
/** sdio_slave_sdio_clk_rdn_ena : R/W; bitpos: [3]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_sdio_clk_rdn_ena:1;
/** sdio_slave_sdclk_pad_rdn_result : RO; bitpos: [4]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_sdclk_pad_rdn_result:1;
/** sdio_slave_sdclk_pad_rdn_ena : R/W; bitpos: [5]; default: 0;
* redundant registers for sdio_slave
*/
uint32_t sdio_slave_sdclk_pad_rdn_ena:1;
uint32_t reserved_6:26;
};
uint32_t val;
} hinf_sdio_slave_eco_conf_reg_t;
/** Type of sdio_slave_ldo_conf register
* sdio slave ldo control register
*/
typedef union {
struct {
/** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
uint32_t ldo_ready_ctl_in_en:1;
/** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
uint32_t ldo_ready_thres:5;
/** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
uint32_t ldo_ready_ignore_en:1;
uint32_t reserved_7:25;
};
uint32_t val;
} hinf_sdio_slave_ldo_conf_reg_t;
/** Group: Status registers */
/** Type of conf_status register
* func0 config0 status
*/
typedef union {
struct {
/** func0_config0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
uint32_t func0_config0:8;
/** sdr25_st : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
uint32_t sdr25_st:1;
/** sdr50_st : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
uint32_t sdr50_st:1;
/** sdr104_st : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
uint32_t sdr104_st:1;
/** ddr50_st : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
uint32_t ddr50_st:1;
/** tune_st : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
uint32_t tune_st:3;
/** sdio_switch_volt_st : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
uint32_t sdio_switch_volt_st:1;
/** sdio_switch_end : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
uint32_t sdio_switch_end:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hinf_conf_status_reg_t;
/** Group: Version register */
/** Type of sdio_date register
* ******* Description ***********
*/
typedef union {
struct {
/** sdio_date : R/W; bitpos: [31:0]; default: 35664208;
* sdio version date.
*/
uint32_t sdio_date:32;
};
uint32_t val;
} hinf_sdio_date_reg_t;
typedef struct hinf_dev_t {
volatile hinf_cfg_data0_reg_t cfg_data0;
volatile hinf_cfg_data1_reg_t cfg_data1;
volatile hinf_cfg_timing_reg_t cfg_timing;
volatile hinf_cfg_update_reg_t cfg_update;
uint32_t reserved_010[3];
volatile hinf_cfg_data7_reg_t cfg_data7;
volatile hinf_cis_conf_w0_reg_t cis_conf_w0;
volatile hinf_cis_conf_w1_reg_t cis_conf_w1;
volatile hinf_cis_conf_w2_reg_t cis_conf_w2;
volatile hinf_cis_conf_w3_reg_t cis_conf_w3;
volatile hinf_cis_conf_w4_reg_t cis_conf_w4;
volatile hinf_cis_conf_w5_reg_t cis_conf_w5;
volatile hinf_cis_conf_w6_reg_t cis_conf_w6;
volatile hinf_cis_conf_w7_reg_t cis_conf_w7;
volatile hinf_cfg_data16_reg_t cfg_data16;
volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode;
uint32_t reserved_048[3];
volatile hinf_conf_status_reg_t conf_status;
uint32_t reserved_058[19];
volatile hinf_sdio_slave_eco_low_reg_t sdio_slave_eco_low;
volatile hinf_sdio_slave_eco_high_reg_t sdio_slave_eco_high;
volatile hinf_sdio_slave_eco_conf_reg_t sdio_slave_eco_conf;
volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf;
uint32_t reserved_0b4[18];
volatile hinf_sdio_date_reg_t sdio_date;
} hinf_dev_t;
extern hinf_dev_t HINF;
#ifndef __cplusplus
_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_HP_CLKRST_REG_H_
#define _SOC_HP_CLKRST_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define HP_CLKRST_VER_DATE_REG (DR_REG_HP_CLKRST_BASE + 0x0)
/* HP_CLKRST_VER_DATE : R/W ;bitpos:[31:0] ;default: 32'h20201229 ; */
/*description: .*/
#define HP_CLKRST_VER_DATE 0xFFFFFFFF
#define HP_CLKRST_VER_DATE_M ((HP_CLKRST_VER_DATE_V)<<(HP_CLKRST_VER_DATE_S))
#define HP_CLKRST_VER_DATE_V 0xFFFFFFFF
#define HP_CLKRST_VER_DATE_S 0
#define HP_CLKRST_HP_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x4)
/* HP_CLKRST_HP_CPU_ROOT_CLK_SEL : R/W ;bitpos:[3:2] ;default: 2'h1 ; */
/*description: Hp cpu root clock source select; 2'h0: 20M RC OSC; 2'h1: 40M XTAL; 2'h2: HP CPU
PLL clock; 2'h3: HP system PLL clock.*/
#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL 0x00000003
#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_M ((HP_CLKRST_HP_CPU_ROOT_CLK_SEL_V)<<(HP_CLKRST_HP_CPU_ROOT_CLK_SEL_S))
#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_V 0x3
#define HP_CLKRST_HP_CPU_ROOT_CLK_SEL_S 2
/* HP_CLKRST_HP_SYS_ROOT_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'h1 ; */
/*description: Hp system root clock source select; 2'h0: 20M RC OSC; 2'h1: 40M XTAL; 2'h2: HP s
ystem PLL clock; 2'h3: HP CPU PLL clock.*/
#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL 0x00000003
#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_M ((HP_CLKRST_HP_SYS_ROOT_CLK_SEL_V)<<(HP_CLKRST_HP_SYS_ROOT_CLK_SEL_S))
#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_V 0x3
#define HP_CLKRST_HP_SYS_ROOT_CLK_SEL_S 0
#define HP_CLKRST_CPU_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x8)
/* HP_CLKRST_CPU_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: current clock divider number.*/
#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM 0x000000FF
#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_M ((HP_CLKRST_CPU_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_CPU_CLK_CUR_DIV_NUM_S))
#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_V 0xFF
#define HP_CLKRST_CPU_CLK_CUR_DIV_NUM_S 24
/* HP_CLKRST_CPU_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: clock divider number.*/
#define HP_CLKRST_CPU_CLK_DIV_NUM 0x000000FF
#define HP_CLKRST_CPU_CLK_DIV_NUM_M ((HP_CLKRST_CPU_CLK_DIV_NUM_V)<<(HP_CLKRST_CPU_CLK_DIV_NUM_S))
#define HP_CLKRST_CPU_CLK_DIV_NUM_V 0xFF
#define HP_CLKRST_CPU_CLK_DIV_NUM_S 8
/* HP_CLKRST_CPU_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: clock output enable.*/
#define HP_CLKRST_CPU_CLK_EN (BIT(0))
#define HP_CLKRST_CPU_CLK_EN_M (BIT(0))
#define HP_CLKRST_CPU_CLK_EN_V 0x1
#define HP_CLKRST_CPU_CLK_EN_S 0
#define HP_CLKRST_SYS_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0xC)
/* HP_CLKRST_SYS_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: current clock divider number.*/
#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM 0x000000FF
#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_M ((HP_CLKRST_SYS_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_SYS_CLK_CUR_DIV_NUM_S))
#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_V 0xFF
#define HP_CLKRST_SYS_CLK_CUR_DIV_NUM_S 24
/* HP_CLKRST_SYS_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: phase offset compare to clock sync signal.*/
#define HP_CLKRST_SYS_CLK_PHASE_OFFSET 0x000000FF
#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_M ((HP_CLKRST_SYS_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_SYS_CLK_PHASE_OFFSET_S))
#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_V 0xFF
#define HP_CLKRST_SYS_CLK_PHASE_OFFSET_S 16
/* HP_CLKRST_SYS_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: clock divider number.*/
#define HP_CLKRST_SYS_CLK_DIV_NUM 0x000000FF
#define HP_CLKRST_SYS_CLK_DIV_NUM_M ((HP_CLKRST_SYS_CLK_DIV_NUM_V)<<(HP_CLKRST_SYS_CLK_DIV_NUM_S))
#define HP_CLKRST_SYS_CLK_DIV_NUM_V 0xFF
#define HP_CLKRST_SYS_CLK_DIV_NUM_S 8
/* HP_CLKRST_SYS_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: clock force sync enable : clock output only available when clock is synced.*/
#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN (BIT(2))
#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_M (BIT(2))
#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_V 0x1
#define HP_CLKRST_SYS_CLK_FORCE_SYNC_EN_S 2
/* HP_CLKRST_SYS_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
#define HP_CLKRST_SYS_CLK_SYNC_EN (BIT(1))
#define HP_CLKRST_SYS_CLK_SYNC_EN_M (BIT(1))
#define HP_CLKRST_SYS_CLK_SYNC_EN_V 0x1
#define HP_CLKRST_SYS_CLK_SYNC_EN_S 1
/* HP_CLKRST_SYS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: clock output enable.*/
#define HP_CLKRST_SYS_CLK_EN (BIT(0))
#define HP_CLKRST_SYS_CLK_EN_M (BIT(0))
#define HP_CLKRST_SYS_CLK_EN_V 0x1
#define HP_CLKRST_SYS_CLK_EN_S 0
#define HP_CLKRST_PERI1_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x10)
/* HP_CLKRST_PERI1_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: current clock divider number.*/
#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM 0x000000FF
#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_M ((HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_S))
#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_V 0xFF
#define HP_CLKRST_PERI1_CLK_CUR_DIV_NUM_S 24
/* HP_CLKRST_PERI1_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: phase offset compare to clock sync signal.*/
#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET 0x000000FF
#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_M ((HP_CLKRST_PERI1_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_PERI1_CLK_PHASE_OFFSET_S))
#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_V 0xFF
#define HP_CLKRST_PERI1_CLK_PHASE_OFFSET_S 16
/* HP_CLKRST_PERI1_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: clock divider number.*/
#define HP_CLKRST_PERI1_CLK_DIV_NUM 0x000000FF
#define HP_CLKRST_PERI1_CLK_DIV_NUM_M ((HP_CLKRST_PERI1_CLK_DIV_NUM_V)<<(HP_CLKRST_PERI1_CLK_DIV_NUM_S))
#define HP_CLKRST_PERI1_CLK_DIV_NUM_V 0xFF
#define HP_CLKRST_PERI1_CLK_DIV_NUM_S 8
/* HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: clock force sync enable : clock output only available when clock is synced.*/
#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN (BIT(2))
#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_M (BIT(2))
#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_V 0x1
#define HP_CLKRST_PERI1_CLK_FORCE_SYNC_EN_S 2
/* HP_CLKRST_PERI1_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
#define HP_CLKRST_PERI1_CLK_SYNC_EN (BIT(1))
#define HP_CLKRST_PERI1_CLK_SYNC_EN_M (BIT(1))
#define HP_CLKRST_PERI1_CLK_SYNC_EN_V 0x1
#define HP_CLKRST_PERI1_CLK_SYNC_EN_S 1
/* HP_CLKRST_PERI1_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: clock output enable.*/
#define HP_CLKRST_PERI1_CLK_EN (BIT(0))
#define HP_CLKRST_PERI1_CLK_EN_M (BIT(0))
#define HP_CLKRST_PERI1_CLK_EN_V 0x1
#define HP_CLKRST_PERI1_CLK_EN_S 0
#define HP_CLKRST_PERI2_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x14)
/* HP_CLKRST_PERI2_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: current clock divider number.*/
#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM 0x000000FF
#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_M ((HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_S))
#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_V 0xFF
#define HP_CLKRST_PERI2_CLK_CUR_DIV_NUM_S 24
/* HP_CLKRST_PERI2_CLK_PHASE_OFFSET : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
/*description: phase offset compare to clock sync signal.*/
#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET 0x000000FF
#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_M ((HP_CLKRST_PERI2_CLK_PHASE_OFFSET_V)<<(HP_CLKRST_PERI2_CLK_PHASE_OFFSET_S))
#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_V 0xFF
#define HP_CLKRST_PERI2_CLK_PHASE_OFFSET_S 16
/* HP_CLKRST_PERI2_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: clock divider number.*/
#define HP_CLKRST_PERI2_CLK_DIV_NUM 0x000000FF
#define HP_CLKRST_PERI2_CLK_DIV_NUM_M ((HP_CLKRST_PERI2_CLK_DIV_NUM_V)<<(HP_CLKRST_PERI2_CLK_DIV_NUM_S))
#define HP_CLKRST_PERI2_CLK_DIV_NUM_V 0xFF
#define HP_CLKRST_PERI2_CLK_DIV_NUM_S 8
/* HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: clock force sync enable : clock output only available when clock is synced.*/
#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN (BIT(2))
#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_M (BIT(2))
#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_V 0x1
#define HP_CLKRST_PERI2_CLK_FORCE_SYNC_EN_S 2
/* HP_CLKRST_PERI2_CLK_SYNC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: clock sync enable : will adjust clock phase when receive clock sync signal.*/
#define HP_CLKRST_PERI2_CLK_SYNC_EN (BIT(1))
#define HP_CLKRST_PERI2_CLK_SYNC_EN_M (BIT(1))
#define HP_CLKRST_PERI2_CLK_SYNC_EN_V 0x1
#define HP_CLKRST_PERI2_CLK_SYNC_EN_S 1
/* HP_CLKRST_PERI2_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: clock output enable.*/
#define HP_CLKRST_PERI2_CLK_EN (BIT(0))
#define HP_CLKRST_PERI2_CLK_EN_M (BIT(0))
#define HP_CLKRST_PERI2_CLK_EN_V 0x1
#define HP_CLKRST_PERI2_CLK_EN_S 0
#define HP_CLKRST_PSRAM_PHY_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x18)
/* HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: current clock divider number.*/
#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM 0x000000FF
#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_M ((HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_S))
#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_V 0xFF
#define HP_CLKRST_PSRAM_PHY_CLK_CUR_DIV_NUM_S 24
/* HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: .*/
#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM 0x000000FF
#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_M ((HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_V)<<(HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_S))
#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_V 0xFF
#define HP_CLKRST_PSRAM_PHY_CLK_DIV_NUM_S 8
/* HP_CLKRST_PSRAM_PHY_CLK_SEL : R/W ;bitpos:[2:1] ;default: 2'h1 ; */
/*description: .*/
#define HP_CLKRST_PSRAM_PHY_CLK_SEL 0x00000003
#define HP_CLKRST_PSRAM_PHY_CLK_SEL_M ((HP_CLKRST_PSRAM_PHY_CLK_SEL_V)<<(HP_CLKRST_PSRAM_PHY_CLK_SEL_S))
#define HP_CLKRST_PSRAM_PHY_CLK_SEL_V 0x3
#define HP_CLKRST_PSRAM_PHY_CLK_SEL_S 1
/* HP_CLKRST_PSRAM_PHY_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: .*/
#define HP_CLKRST_PSRAM_PHY_CLK_EN (BIT(0))
#define HP_CLKRST_PSRAM_PHY_CLK_EN_M (BIT(0))
#define HP_CLKRST_PSRAM_PHY_CLK_EN_V 0x1
#define HP_CLKRST_PSRAM_PHY_CLK_EN_S 0
#define HP_CLKRST_DDR_PHY_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x1C)
/* HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: current clock divider number.*/
#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM 0x000000FF
#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_M ((HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_V)<<(HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_S))
#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_V 0xFF
#define HP_CLKRST_DDR_PHY_CLK_CUR_DIV_NUM_S 24
/* HP_CLKRST_DDR_PHY_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: .*/
#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM 0x000000FF
#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_M ((HP_CLKRST_DDR_PHY_CLK_DIV_NUM_V)<<(HP_CLKRST_DDR_PHY_CLK_DIV_NUM_S))
#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_V 0xFF
#define HP_CLKRST_DDR_PHY_CLK_DIV_NUM_S 8
/* HP_CLKRST_DDR_PHY_CLK_SEL : R/W ;bitpos:[2:1] ;default: 2'h1 ; */
/*description: .*/
#define HP_CLKRST_DDR_PHY_CLK_SEL 0x00000003
#define HP_CLKRST_DDR_PHY_CLK_SEL_M ((HP_CLKRST_DDR_PHY_CLK_SEL_V)<<(HP_CLKRST_DDR_PHY_CLK_SEL_S))
#define HP_CLKRST_DDR_PHY_CLK_SEL_V 0x3
#define HP_CLKRST_DDR_PHY_CLK_SEL_S 1
/* HP_CLKRST_DDR_PHY_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: .*/
#define HP_CLKRST_DDR_PHY_CLK_EN (BIT(0))
#define HP_CLKRST_DDR_PHY_CLK_EN_M (BIT(0))
#define HP_CLKRST_DDR_PHY_CLK_EN_V 0x1
#define HP_CLKRST_DDR_PHY_CLK_EN_S 0
#define HP_CLKRST_MSPI_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x20)
/* HP_CLKRST_MSPI_SRC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h2 ; */
/*description: 2'b00:480MHz PLL; 2'b01: MSPI DLL CLK; 2'b1x: HP XTAL CLK.*/
#define HP_CLKRST_MSPI_SRC_CLK_SEL 0x00000003
#define HP_CLKRST_MSPI_SRC_CLK_SEL_M ((HP_CLKRST_MSPI_SRC_CLK_SEL_V)<<(HP_CLKRST_MSPI_SRC_CLK_SEL_S))
#define HP_CLKRST_MSPI_SRC_CLK_SEL_V 0x3
#define HP_CLKRST_MSPI_SRC_CLK_SEL_S 16
/* HP_CLKRST_MSPI_CLK_DIV_NUM : R/W ;bitpos:[11:8] ;default: 4'h1 ; */
/*description: clock divider number.*/
#define HP_CLKRST_MSPI_CLK_DIV_NUM 0x0000000F
#define HP_CLKRST_MSPI_CLK_DIV_NUM_M ((HP_CLKRST_MSPI_CLK_DIV_NUM_V)<<(HP_CLKRST_MSPI_CLK_DIV_NUM_S))
#define HP_CLKRST_MSPI_CLK_DIV_NUM_V 0xF
#define HP_CLKRST_MSPI_CLK_DIV_NUM_S 8
/* HP_CLKRST_MSPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: clock output enable.*/
#define HP_CLKRST_MSPI_CLK_EN (BIT(0))
#define HP_CLKRST_MSPI_CLK_EN_M (BIT(0))
#define HP_CLKRST_MSPI_CLK_EN_V 0x1
#define HP_CLKRST_MSPI_CLK_EN_S 0
#define HP_CLKRST_DUAL_MSPI_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x24)
/* HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h2 ; */
/*description: 2'b00:480MHz PLL; 2'b01: MSPI DLL CLK; 2'b1x: HP XTAL CLK.*/
#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL 0x00000003
#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_M ((HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_V)<<(HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_S))
#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_V 0x3
#define HP_CLKRST_DUAL_MSPI_SRC_CLK_SEL_S 16
/* HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM : R/W ;bitpos:[11:8] ;default: 4'h1 ; */
/*description: clock divider number.*/
#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM 0x0000000F
#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_M ((HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_V)<<(HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_S))
#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_V 0xF
#define HP_CLKRST_DUAL_MSPI_CLK_DIV_NUM_S 8
/* HP_CLKRST_DUAL_MSPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: clock output enable.*/
#define HP_CLKRST_DUAL_MSPI_CLK_EN (BIT(0))
#define HP_CLKRST_DUAL_MSPI_CLK_EN_M (BIT(0))
#define HP_CLKRST_DUAL_MSPI_CLK_EN_V 0x1
#define HP_CLKRST_DUAL_MSPI_CLK_EN_S 0
#define HP_CLKRST_REF_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x28)
/* HP_CLKRST_REF_CLK2_DIV_NUM : R/W ;bitpos:[27:24] ;default: 4'h3 ; */
/*description: 120MHz reference clock divider number, used by i3c master.*/
#define HP_CLKRST_REF_CLK2_DIV_NUM 0x0000000F
#define HP_CLKRST_REF_CLK2_DIV_NUM_M ((HP_CLKRST_REF_CLK2_DIV_NUM_V)<<(HP_CLKRST_REF_CLK2_DIV_NUM_S))
#define HP_CLKRST_REF_CLK2_DIV_NUM_V 0xF
#define HP_CLKRST_REF_CLK2_DIV_NUM_S 24
/* HP_CLKRST_USBPHY_CLK_DIV_NUM : R/W ;bitpos:[23:20] ;default: 4'h9 ; */
/*description: usbphy clock divider number.*/
#define HP_CLKRST_USBPHY_CLK_DIV_NUM 0x0000000F
#define HP_CLKRST_USBPHY_CLK_DIV_NUM_M ((HP_CLKRST_USBPHY_CLK_DIV_NUM_V)<<(HP_CLKRST_USBPHY_CLK_DIV_NUM_S))
#define HP_CLKRST_USBPHY_CLK_DIV_NUM_V 0xF
#define HP_CLKRST_USBPHY_CLK_DIV_NUM_S 20
/* HP_CLKRST_LEDC_REF_CLK_DIV_NUM : R/W ;bitpos:[19:16] ;default: 4'h1 ; */
/*description: ledc reference clock divider number.*/
#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM 0x0000000F
#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_M ((HP_CLKRST_LEDC_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_LEDC_REF_CLK_DIV_NUM_S))
#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_V 0xF
#define HP_CLKRST_LEDC_REF_CLK_DIV_NUM_S 16
/* HP_CLKRST_USB2_REF_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h27 ; */
/*description: usb2 phy reference clock divider number.*/
#define HP_CLKRST_USB2_REF_CLK_DIV_NUM 0x000000FF
#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_M ((HP_CLKRST_USB2_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_USB2_REF_CLK_DIV_NUM_S))
#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_V 0xFF
#define HP_CLKRST_USB2_REF_CLK_DIV_NUM_S 8
/* HP_CLKRST_REF_CLK_DIV_NUM : R/W ;bitpos:[4:1] ;default: 4'h2 ; */
/*description: reference clock divider number.*/
#define HP_CLKRST_REF_CLK_DIV_NUM 0x0000000F
#define HP_CLKRST_REF_CLK_DIV_NUM_M ((HP_CLKRST_REF_CLK_DIV_NUM_V)<<(HP_CLKRST_REF_CLK_DIV_NUM_S))
#define HP_CLKRST_REF_CLK_DIV_NUM_V 0xF
#define HP_CLKRST_REF_CLK_DIV_NUM_S 1
/* HP_CLKRST_REF_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: reference clock output enable.*/
#define HP_CLKRST_REF_CLK_EN (BIT(0))
#define HP_CLKRST_REF_CLK_EN_M (BIT(0))
#define HP_CLKRST_REF_CLK_EN_V 0x1
#define HP_CLKRST_REF_CLK_EN_S 0
#define HP_CLKRST_TM_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x2C)
/* HP_CLKRST_TM_240M_CLK_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: 240M test mode clock enable.*/
#define HP_CLKRST_TM_240M_CLK_EN (BIT(7))
#define HP_CLKRST_TM_240M_CLK_EN_M (BIT(7))
#define HP_CLKRST_TM_240M_CLK_EN_V 0x1
#define HP_CLKRST_TM_240M_CLK_EN_S 7
/* HP_CLKRST_TM_200M_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: 200M test mode clock enable.*/
#define HP_CLKRST_TM_200M_CLK_EN (BIT(6))
#define HP_CLKRST_TM_200M_CLK_EN_M (BIT(6))
#define HP_CLKRST_TM_200M_CLK_EN_V 0x1
#define HP_CLKRST_TM_200M_CLK_EN_S 6
/* HP_CLKRST_TM_160M_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: 160M test mode clock enable.*/
#define HP_CLKRST_TM_160M_CLK_EN (BIT(5))
#define HP_CLKRST_TM_160M_CLK_EN_M (BIT(5))
#define HP_CLKRST_TM_160M_CLK_EN_V 0x1
#define HP_CLKRST_TM_160M_CLK_EN_S 5
/* HP_CLKRST_TM_120M_CLK_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: 120M test mode clock enable.*/
#define HP_CLKRST_TM_120M_CLK_EN (BIT(4))
#define HP_CLKRST_TM_120M_CLK_EN_M (BIT(4))
#define HP_CLKRST_TM_120M_CLK_EN_V 0x1
#define HP_CLKRST_TM_120M_CLK_EN_S 4
/* HP_CLKRST_TM_80M_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: 80M test mode clock enable.*/
#define HP_CLKRST_TM_80M_CLK_EN (BIT(3))
#define HP_CLKRST_TM_80M_CLK_EN_M (BIT(3))
#define HP_CLKRST_TM_80M_CLK_EN_V 0x1
#define HP_CLKRST_TM_80M_CLK_EN_S 3
/* HP_CLKRST_TM_48M_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: 48M test mode clock enable.*/
#define HP_CLKRST_TM_48M_CLK_EN (BIT(2))
#define HP_CLKRST_TM_48M_CLK_EN_M (BIT(2))
#define HP_CLKRST_TM_48M_CLK_EN_V 0x1
#define HP_CLKRST_TM_48M_CLK_EN_S 2
/* HP_CLKRST_TM_40M_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: 40M test mode clock enable.*/
#define HP_CLKRST_TM_40M_CLK_EN (BIT(1))
#define HP_CLKRST_TM_40M_CLK_EN_M (BIT(1))
#define HP_CLKRST_TM_40M_CLK_EN_V 0x1
#define HP_CLKRST_TM_40M_CLK_EN_S 1
/* HP_CLKRST_TM_20M_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: 20M test mode clock enabl.*/
#define HP_CLKRST_TM_20M_CLK_EN (BIT(0))
#define HP_CLKRST_TM_20M_CLK_EN_M (BIT(0))
#define HP_CLKRST_TM_20M_CLK_EN_V 0x1
#define HP_CLKRST_TM_20M_CLK_EN_S 0
#define HP_CLKRST_CORE_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x30)
/* HP_CLKRST_CORE0_GLOBAL_RSTN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: core0 software global reset.*/
#define HP_CLKRST_CORE0_GLOBAL_RSTN (BIT(9))
#define HP_CLKRST_CORE0_GLOBAL_RSTN_M (BIT(9))
#define HP_CLKRST_CORE0_GLOBAL_RSTN_V 0x1
#define HP_CLKRST_CORE0_GLOBAL_RSTN_S 9
/* HP_CLKRST_CORE1_GLOBAL_RSTN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: core1 software global reset.*/
#define HP_CLKRST_CORE1_GLOBAL_RSTN (BIT(8))
#define HP_CLKRST_CORE1_GLOBAL_RSTN_M (BIT(8))
#define HP_CLKRST_CORE1_GLOBAL_RSTN_V 0x1
#define HP_CLKRST_CORE1_GLOBAL_RSTN_S 8
/* HP_CLKRST_CORE0_FORCE_NORST : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: software force no reset.*/
#define HP_CLKRST_CORE0_FORCE_NORST (BIT(7))
#define HP_CLKRST_CORE0_FORCE_NORST_M (BIT(7))
#define HP_CLKRST_CORE0_FORCE_NORST_V 0x1
#define HP_CLKRST_CORE0_FORCE_NORST_S 7
/* HP_CLKRST_CORE1_FORCE_NORST : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: software force no reset.*/
#define HP_CLKRST_CORE1_FORCE_NORST (BIT(6))
#define HP_CLKRST_CORE1_FORCE_NORST_M (BIT(6))
#define HP_CLKRST_CORE1_FORCE_NORST_V 0x1
#define HP_CLKRST_CORE1_FORCE_NORST_S 6
/* HP_CLKRST_CORE2_FORCE_NORST : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: software force no reset.*/
#define HP_CLKRST_CORE2_FORCE_NORST (BIT(5))
#define HP_CLKRST_CORE2_FORCE_NORST_M (BIT(5))
#define HP_CLKRST_CORE2_FORCE_NORST_V 0x1
#define HP_CLKRST_CORE2_FORCE_NORST_S 5
/* HP_CLKRST_CORE3_FORCE_NORST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: software force no reset.*/
#define HP_CLKRST_CORE3_FORCE_NORST (BIT(4))
#define HP_CLKRST_CORE3_FORCE_NORST_M (BIT(4))
#define HP_CLKRST_CORE3_FORCE_NORST_V 0x1
#define HP_CLKRST_CORE3_FORCE_NORST_S 4
/* HP_CLKRST_CORE0_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: hp core0 clock enable.*/
#define HP_CLKRST_CORE0_CLK_EN (BIT(3))
#define HP_CLKRST_CORE0_CLK_EN_M (BIT(3))
#define HP_CLKRST_CORE0_CLK_EN_V 0x1
#define HP_CLKRST_CORE0_CLK_EN_S 3
/* HP_CLKRST_CORE1_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: hp core1 clock enable.*/
#define HP_CLKRST_CORE1_CLK_EN (BIT(2))
#define HP_CLKRST_CORE1_CLK_EN_M (BIT(2))
#define HP_CLKRST_CORE1_CLK_EN_V 0x1
#define HP_CLKRST_CORE1_CLK_EN_S 2
/* HP_CLKRST_CORE2_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: hp core2 clock enable.*/
#define HP_CLKRST_CORE2_CLK_EN (BIT(1))
#define HP_CLKRST_CORE2_CLK_EN_M (BIT(1))
#define HP_CLKRST_CORE2_CLK_EN_V 0x1
#define HP_CLKRST_CORE2_CLK_EN_S 1
/* HP_CLKRST_CORE3_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: hp core3 clock enable.*/
#define HP_CLKRST_CORE3_CLK_EN (BIT(0))
#define HP_CLKRST_CORE3_CLK_EN_M (BIT(0))
#define HP_CLKRST_CORE3_CLK_EN_V 0x1
#define HP_CLKRST_CORE3_CLK_EN_S 0
#define HP_CLKRST_CACHE_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x34)
/* HP_CLKRST_CACHE_CLK_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
/*description: L2 cache clock divider number.*/
#define HP_CLKRST_CACHE_CLK_DIV_NUM 0x000000FF
#define HP_CLKRST_CACHE_CLK_DIV_NUM_M ((HP_CLKRST_CACHE_CLK_DIV_NUM_V)<<(HP_CLKRST_CACHE_CLK_DIV_NUM_S))
#define HP_CLKRST_CACHE_CLK_DIV_NUM_V 0xFF
#define HP_CLKRST_CACHE_CLK_DIV_NUM_S 8
/* HP_CLKRST_HP_CACHE_RSTN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: cache software reset: low active.*/
#define HP_CLKRST_HP_CACHE_RSTN (BIT(2))
#define HP_CLKRST_HP_CACHE_RSTN_M (BIT(2))
#define HP_CLKRST_HP_CACHE_RSTN_V 0x1
#define HP_CLKRST_HP_CACHE_RSTN_S 2
/* HP_CLKRST_CACHE_APB_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: cache apb clock enable.*/
#define HP_CLKRST_CACHE_APB_CLK_EN (BIT(1))
#define HP_CLKRST_CACHE_APB_CLK_EN_M (BIT(1))
#define HP_CLKRST_CACHE_APB_CLK_EN_V 0x1
#define HP_CLKRST_CACHE_APB_CLK_EN_S 1
/* HP_CLKRST_CACHE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: cache clock enable.*/
#define HP_CLKRST_CACHE_CLK_EN (BIT(0))
#define HP_CLKRST_CACHE_CLK_EN_M (BIT(0))
#define HP_CLKRST_CACHE_CLK_EN_V 0x1
#define HP_CLKRST_CACHE_CLK_EN_S 0
#define HP_CLKRST_CPU_PERI_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x38)
/* HP_CLKRST_L2_MEM_RSTN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: l2 memory software reset: low active.*/
#define HP_CLKRST_L2_MEM_RSTN (BIT(4))
#define HP_CLKRST_L2_MEM_RSTN_M (BIT(4))
#define HP_CLKRST_L2_MEM_RSTN_V 0x1
#define HP_CLKRST_L2_MEM_RSTN_S 4
/* HP_CLKRST_L2_MEM_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: l2 memory clock enable.*/
#define HP_CLKRST_L2_MEM_CLK_EN (BIT(3))
#define HP_CLKRST_L2_MEM_CLK_EN_M (BIT(3))
#define HP_CLKRST_L2_MEM_CLK_EN_V 0x1
#define HP_CLKRST_L2_MEM_CLK_EN_S 3
/* HP_CLKRST_TCM_RSTN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: tcm software reset: low active.*/
#define HP_CLKRST_TCM_RSTN (BIT(2))
#define HP_CLKRST_TCM_RSTN_M (BIT(2))
#define HP_CLKRST_TCM_RSTN_V 0x1
#define HP_CLKRST_TCM_RSTN_S 2
/* HP_CLKRST_TCM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: tcm clock enable.*/
#define HP_CLKRST_TCM_CLK_EN (BIT(1))
#define HP_CLKRST_TCM_CLK_EN_M (BIT(1))
#define HP_CLKRST_TCM_CLK_EN_V 0x1
#define HP_CLKRST_TCM_CLK_EN_S 1
/* HP_CLKRST_CPU_CTRL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: cpu control logic clock enable.*/
#define HP_CLKRST_CPU_CTRL_CLK_EN (BIT(0))
#define HP_CLKRST_CPU_CTRL_CLK_EN_M (BIT(0))
#define HP_CLKRST_CPU_CTRL_CLK_EN_V 0x1
#define HP_CLKRST_CPU_CTRL_CLK_EN_S 0
#define HP_CLKRST_SYNC_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x3C)
/* HP_CLKRST_CLK_EN : R/W ;bitpos:[17] ;default: 1'b1 ; */
/*description: .*/
#define HP_CLKRST_CLK_EN (BIT(17))
#define HP_CLKRST_CLK_EN_M (BIT(17))
#define HP_CLKRST_CLK_EN_V 0x1
#define HP_CLKRST_CLK_EN_S 17
/* HP_CLKRST_HP_ROOT_CLK_SYNC_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
/*description: clock sync signal output enable.*/
#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN (BIT(16))
#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_M (BIT(16))
#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_V 0x1
#define HP_CLKRST_HP_ROOT_CLK_SYNC_EN_S 16
/* HP_CLKRST_HP_ROOT_CLK_SYNC_PERID : R/W ;bitpos:[15:0] ;default: 16'h347 ; */
/*description: clock sync signal generation period.*/
#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID 0x0000FFFF
#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_M ((HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_V)<<(HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_S))
#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_V 0xFFFF
#define HP_CLKRST_HP_ROOT_CLK_SYNC_PERID_S 0
#define HP_CLKRST_WFI_GATE_CLK_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x40)
/* HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON : R/W ;bitpos:[18] ;default: 1'b1 ; */
/*description: force group3(L2 Memory) clock on after WFI.*/
#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON (BIT(18))
#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_M (BIT(18))
#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_V 0x1
#define HP_CLKRST_CPU_WFI_FORCE_CLKG3_ON_S 18
/* HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON : R/W ;bitpos:[17] ;default: 1'b1 ; */
/*description: force group2(HP TCM) clock on after WFI.*/
#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON (BIT(17))
#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_M (BIT(17))
#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_V 0x1
#define HP_CLKRST_CPU_WFI_FORCE_CLKG2_ON_S 17
/* HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON : R/W ;bitpos:[16] ;default: 1'b1 ; */
/*description: force group1(L1/L2 cache & trace & cpu_icm_ibus) clock on after WFI.*/
#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON (BIT(16))
#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_M (BIT(16))
#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_V 0x1
#define HP_CLKRST_CPU_WFI_FORCE_CLKG1_ON_S 16
/* HP_CLKRST_CPU_WFI_DELAY_NUM : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
/*description: This register indicates delayed clock cycles before auto gating HP cache/trace c
lock once WFI asserted.*/
#define HP_CLKRST_CPU_WFI_DELAY_NUM 0x0000000F
#define HP_CLKRST_CPU_WFI_DELAY_NUM_M ((HP_CLKRST_CPU_WFI_DELAY_NUM_V)<<(HP_CLKRST_CPU_WFI_DELAY_NUM_S))
#define HP_CLKRST_CPU_WFI_DELAY_NUM_V 0xF
#define HP_CLKRST_CPU_WFI_DELAY_NUM_S 0
#define HP_CLKRST_PVT_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x44)
/* HP_CLKRST_PVT_APB_RSTN : R/W ;bitpos:[21] ;default: 1'h1 ; */
/*description: pvt apb resetn.*/
#define HP_CLKRST_PVT_APB_RSTN (BIT(21))
#define HP_CLKRST_PVT_APB_RSTN_M (BIT(21))
#define HP_CLKRST_PVT_APB_RSTN_V 0x1
#define HP_CLKRST_PVT_APB_RSTN_S 21
/* HP_CLKRST_PVT_PERI_GROUP2_RSTN : R/W ;bitpos:[20] ;default: 1'h1 ; */
/*description: pvt peri group2 resetn.*/
#define HP_CLKRST_PVT_PERI_GROUP2_RSTN (BIT(20))
#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_M (BIT(20))
#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_V 0x1
#define HP_CLKRST_PVT_PERI_GROUP2_RSTN_S 20
/* HP_CLKRST_PVT_PERI_GROUP1_RSTN : R/W ;bitpos:[19] ;default: 1'h1 ; */
/*description: pvt peri group1 resetn.*/
#define HP_CLKRST_PVT_PERI_GROUP1_RSTN (BIT(19))
#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_M (BIT(19))
#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_V 0x1
#define HP_CLKRST_PVT_PERI_GROUP1_RSTN_S 19
/* HP_CLKRST_PVT_CPU_GROUP2_RSTN : R/W ;bitpos:[18] ;default: 1'h1 ; */
/*description: pvt cpu group2 resetn.*/
#define HP_CLKRST_PVT_CPU_GROUP2_RSTN (BIT(18))
#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_M (BIT(18))
#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_V 0x1
#define HP_CLKRST_PVT_CPU_GROUP2_RSTN_S 18
/* HP_CLKRST_PVT_CPU_GROUP1_RSTN : R/W ;bitpos:[17] ;default: 1'h1 ; */
/*description: pvt cpu group1 resetn.*/
#define HP_CLKRST_PVT_CPU_GROUP1_RSTN (BIT(17))
#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_M (BIT(17))
#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_V 0x1
#define HP_CLKRST_PVT_CPU_GROUP1_RSTN_S 17
/* HP_CLKRST_PVT_TOP_RSTN : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: pvt top resetn.*/
#define HP_CLKRST_PVT_TOP_RSTN (BIT(16))
#define HP_CLKRST_PVT_TOP_RSTN_M (BIT(16))
#define HP_CLKRST_PVT_TOP_RSTN_V 0x1
#define HP_CLKRST_PVT_TOP_RSTN_S 16
/* HP_CLKRST_PVT_APB_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: pvt apb clk en.*/
#define HP_CLKRST_PVT_APB_CLK_EN (BIT(13))
#define HP_CLKRST_PVT_APB_CLK_EN_M (BIT(13))
#define HP_CLKRST_PVT_APB_CLK_EN_V 0x1
#define HP_CLKRST_PVT_APB_CLK_EN_S 13
/* HP_CLKRST_PVT_PERI_GROUP2_CLK_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
/*description: pvt peri group2 clk en.*/
#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN (BIT(12))
#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_M (BIT(12))
#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_V 0x1
#define HP_CLKRST_PVT_PERI_GROUP2_CLK_EN_S 12
/* HP_CLKRST_PVT_PERI_GROUP1_CLK_EN : R/W ;bitpos:[11] ;default: 1'b1 ; */
/*description: pvt peri group1 clk en.*/
#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN (BIT(11))
#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_M (BIT(11))
#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_V 0x1
#define HP_CLKRST_PVT_PERI_GROUP1_CLK_EN_S 11
/* HP_CLKRST_PVT_CPU_GROUP2_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: pvt cpu group2 clk en.*/
#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN (BIT(10))
#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_M (BIT(10))
#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_V 0x1
#define HP_CLKRST_PVT_CPU_GROUP2_CLK_EN_S 10
/* HP_CLKRST_PVT_CPU_GROUP1_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: pvt cpu group1 clk en.*/
#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN (BIT(9))
#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_M (BIT(9))
#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_V 0x1
#define HP_CLKRST_PVT_CPU_GROUP1_CLK_EN_S 9
/* HP_CLKRST_PVT_TOP_CLK_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: pvt top clock en.*/
#define HP_CLKRST_PVT_TOP_CLK_EN (BIT(8))
#define HP_CLKRST_PVT_TOP_CLK_EN_M (BIT(8))
#define HP_CLKRST_PVT_TOP_CLK_EN_V 0x1
#define HP_CLKRST_PVT_TOP_CLK_EN_S 8
/* HP_CLKRST_PVT_CLK_DIV_NUM : R/W ;bitpos:[7:4] ;default: 4'h1 ; */
/*description: pvt clock div number.*/
#define HP_CLKRST_PVT_CLK_DIV_NUM 0x0000000F
#define HP_CLKRST_PVT_CLK_DIV_NUM_M ((HP_CLKRST_PVT_CLK_DIV_NUM_V)<<(HP_CLKRST_PVT_CLK_DIV_NUM_S))
#define HP_CLKRST_PVT_CLK_DIV_NUM_V 0xF
#define HP_CLKRST_PVT_CLK_DIV_NUM_S 4
/* HP_CLKRST_PVT_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'h1 ; */
/*description: pvt clock sel.*/
#define HP_CLKRST_PVT_CLK_SEL 0x00000003
#define HP_CLKRST_PVT_CLK_SEL_M ((HP_CLKRST_PVT_CLK_SEL_V)<<(HP_CLKRST_PVT_CLK_SEL_S))
#define HP_CLKRST_PVT_CLK_SEL_V 0x3
#define HP_CLKRST_PVT_CLK_SEL_S 0
#define HP_CLKRST_TEST_PLL_CTRL_REG (DR_REG_HP_CLKRST_BASE + 0x48)
/* HP_CLKRST_TEST_PLL_DIV_NUM : R/W ;bitpos:[27:16] ;default: 12'h3e7 ; */
/*description: test pll divider number.*/
#define HP_CLKRST_TEST_PLL_DIV_NUM 0x00000FFF
#define HP_CLKRST_TEST_PLL_DIV_NUM_M ((HP_CLKRST_TEST_PLL_DIV_NUM_V)<<(HP_CLKRST_TEST_PLL_DIV_NUM_S))
#define HP_CLKRST_TEST_PLL_DIV_NUM_V 0xFFF
#define HP_CLKRST_TEST_PLL_DIV_NUM_S 16
/* HP_CLKRST_TEST_PLL_SEL : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
/*description: test pll source select; 3'h0: RSVD; 3'h1: system PLL; 3'h2: CPU PLL; 3'h3: MPSI
DLL; 3'h4: SDIO PLL CK0; 3'h5: SDIO PLL CK1; 3'h6: SDIO PLL CK2; 3'h7: AUDIO APL
L.*/
#define HP_CLKRST_TEST_PLL_SEL 0x00000007
#define HP_CLKRST_TEST_PLL_SEL_M ((HP_CLKRST_TEST_PLL_SEL_V)<<(HP_CLKRST_TEST_PLL_SEL_S))
#define HP_CLKRST_TEST_PLL_SEL_V 0x7
#define HP_CLKRST_TEST_PLL_SEL_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_HP_CLKRST_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __HWCRYPTO_REG_H__
#define __HWCRYPTO_REG_H__
#include "soc/soc.h"
/* registers for RSA acceleration via Multiple Precision Integer ops */
#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000)
/* RB & Z use the same memory block, depending on phase of operation */
#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400)
#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600)
/* Configuration registers */
#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800)
#define RSA_LENGTH_REG (DR_REG_RSA_BASE + 0x804)
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
/* Initialization registers */
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/* Calculation start registers */
#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c)
#define RSA_MOD_MULT_START_REG (DR_REG_RSA_BASE + 0x810)
#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814)
/* Interrupt registers */
#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818)
#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C)
#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C)
#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x82C)
#define SHA_MODE_SHA1 0
#define SHA_MODE_SHA224 1
#define SHA_MODE_SHA256 2
/* SHA acceleration registers */
#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28)
#define SHA_DATE_REG ((DR_REG_SHA_BASE) + 0x2C)
#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40)
#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80)
/* AES Block operation modes */
#define AES_BLOCK_MODE_ECB 0
#define AES_BLOCK_MODE_CBC 1
#define AES_BLOCK_MODE_OFB 2
#define AES_BLOCK_MODE_CTR 3
#define AES_BLOCK_MODE_CFB8 4
#define AES_BLOCK_MODE_CFB128 5
/* AES Block operation modes (used with DMA) */
#define AES_BLOCK_MODE_ECB 0
#define AES_BLOCK_MODE_CBC 1
#define AES_BLOCK_MODE_OFB 2
#define AES_BLOCK_MODE_CTR 3
#define AES_BLOCK_MODE_CFB8 4
#define AES_BLOCK_MODE_CFB128 5
/* AES acceleration registers */
#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC)
#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00)
#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20)
#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30)
#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50)
#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60)
#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70)
#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80)
#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC)
#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
/* AES_STATE_REG values */
#define AES_STATE_IDLE 0
#define AES_STATE_BUSY 1
#define AES_STATE_DONE 2
/* HMAC Module */
#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40)
#define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44)
#define HMAC_SET_PARA_KEY_REG ((DR_REG_HMAC_BASE) + 0x48)
#define HMAC_SET_PARA_FINISH_REG ((DR_REG_HMAC_BASE) + 0x4c)
#define HMAC_SET_MESSAGE_ONE_REG ((DR_REG_HMAC_BASE) + 0x50)
#define HMAC_SET_MESSAGE_ING_REG ((DR_REG_HMAC_BASE) + 0x54)
#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58)
#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c)
#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60)
#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64)
#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68)
#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c)
#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80)
#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0)
#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0)
#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4)
#define HMAC_SOFT_JTAG_CTRL_REG ((DR_REG_HMAC_BASE) + 0xF8)
#define HMAC_WR_JTAG_REG ((DR_REG_HMAC_BASE) + 0xFC)
#define HMAC_DATE_REG ((DR_REG_HMAC_BASE) + 0xF8)
/* AES-XTS registers */
#define AES_XTS_PLAIN_BASE ((DR_REG_AES_XTS_BASE) + 0x00)
#define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40)
#define AES_XTS_DESTINATION_REG ((DR_REG_AES_XTS_BASE) + 0x44)
#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
#define AES_XTS_TRIGGER_REG ((DR_REG_AES_XTS_BASE) + 0x4C)
#define AES_XTS_RELEASE_REG ((DR_REG_AES_XTS_BASE) + 0x50)
#define AES_XTS_DESTROY_REG ((DR_REG_AES_XTS_BASE) + 0x54)
#define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58)
#define AES_XTS_DATE_REG ((DR_REG_AES_XTS_BASE) + 0x5C)
/* Digital Signature registers and memory blocks */
#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
#define DS_C_Y_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
#define DS_C_M_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x200 )
#define DS_C_RB_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x400 )
#define DS_C_BOX_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x600 )
#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 )
#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 )
#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 )
#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00)
#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04)
#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08)
#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C)
#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10)
#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14)
#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0)
#define DS_QUERY_CHECK_INVALID_PADDING (1<<1)
#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20)
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
/** INTMTX_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_M (INTMTX_CORE0_WIFI_MAC_INTR_MAP_V << INTMTX_CORE0_WIFI_MAC_INTR_MAP_S)
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_S 0
/** INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
/** INTMTX_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP 0x0000001FU
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_M (INTMTX_CORE0_WIFI_MAC_NMI_MAP_V << INTMTX_CORE0_WIFI_MAC_NMI_MAP_S)
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_V 0x0000001FU
#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_S 0
/** INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
/** INTMTX_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_M (INTMTX_CORE0_WIFI_PWR_INTR_MAP_V << INTMTX_CORE0_WIFI_PWR_INTR_MAP_S)
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_S 0
/** INTMTX_CORE0_WIFI_BB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
/** INTMTX_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_WIFI_BB_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_WIFI_BB_INTR_MAP_M (INTMTX_CORE0_WIFI_BB_INTR_MAP_V << INTMTX_CORE0_WIFI_BB_INTR_MAP_S)
#define INTMTX_CORE0_WIFI_BB_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_WIFI_BB_INTR_MAP_S 0
/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BT_MAC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BT_MAC_INTR_MAP_M (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S)
#define INTMTX_CORE0_BT_MAC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BT_MAC_INTR_MAP_S 0
/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BT_BB_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BT_BB_INTR_MAP_M (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S)
#define INTMTX_CORE0_BT_BB_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BT_BB_INTR_MAP_S 0
/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BT_BB_NMI_MAP 0x0000001FU
#define INTMTX_CORE0_BT_BB_NMI_MAP_M (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S)
#define INTMTX_CORE0_BT_BB_NMI_MAP_V 0x0000001FU
#define INTMTX_CORE0_BT_BB_NMI_MAP_S 0
/** INTMTX_CORE0_LP_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
/** INTMTX_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_TIMER_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_TIMER_INTR_MAP_S)
#define INTMTX_CORE0_LP_TIMER_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_TIMER_INTR_MAP_S 0
/** INTMTX_CORE0_COEX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_COEX_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_COEX_INTR_MAP_M (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S)
#define INTMTX_CORE0_COEX_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_COEX_INTR_MAP_S 0
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S)
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S 0
/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_BLE_SEC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S)
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S 0
/** INTMTX_CORE0_I2C_MST_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
/** INTMTX_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_I2C_MST_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2C_MST_INTR_MAP_M (INTMTX_CORE0_I2C_MST_INTR_MAP_V << INTMTX_CORE0_I2C_MST_INTR_MAP_S)
#define INTMTX_CORE0_I2C_MST_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2C_MST_INTR_MAP_S 0
/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_ZB_MAC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S)
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S 0
/** INTMTX_CORE0_PMU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PMU_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PMU_INTR_MAP_M (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S)
#define INTMTX_CORE0_PMU_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PMU_INTR_MAP_S 0
/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_EFUSE_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_EFUSE_INTR_MAP_M (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S)
#define INTMTX_CORE0_EFUSE_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_EFUSE_INTR_MAP_S 0
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S)
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S 0
/** INTMTX_CORE0_LP_UART_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
/** INTMTX_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_UART_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_UART_INTR_MAP_M (INTMTX_CORE0_LP_UART_INTR_MAP_V << INTMTX_CORE0_LP_UART_INTR_MAP_S)
#define INTMTX_CORE0_LP_UART_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_UART_INTR_MAP_S 0
/** INTMTX_CORE0_LP_I2C_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
/** INTMTX_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_I2C_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_I2C_INTR_MAP_M (INTMTX_CORE0_LP_I2C_INTR_MAP_V << INTMTX_CORE0_LP_I2C_INTR_MAP_S)
#define INTMTX_CORE0_LP_I2C_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_I2C_INTR_MAP_S 0
/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_WDT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_WDT_INTR_MAP_M (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S)
#define INTMTX_CORE0_LP_WDT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_WDT_INTR_MAP_S 0
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S)
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S 0
/** INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
/** INTMTX_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_M (INTMTX_CORE0_LP_APM_M1_INTR_MAP_V << INTMTX_CORE0_LP_APM_M1_INTR_MAP_S)
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S)
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TRACE_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TRACE_INTR_MAP_M (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S)
#define INTMTX_CORE0_TRACE_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TRACE_INTR_MAP_S 0
/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CACHE_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CACHE_INTR_MAP_M (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S)
#define INTMTX_CORE0_CACHE_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CACHE_INTR_MAP_S 0
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001FU
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
/** INTMTX_CORE0_PAU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PAU_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PAU_INTR_MAP_M (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S)
#define INTMTX_CORE0_PAU_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PAU_INTR_MAP_S 0
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S)
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S 0
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S)
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S 0
/** INTMTX_CORE0_LP_APM0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
/** INTMTX_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LP_APM0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LP_APM0_INTR_MAP_M (INTMTX_CORE0_LP_APM0_INTR_MAP_V << INTMTX_CORE0_LP_APM0_INTR_MAP_S)
#define INTMTX_CORE0_LP_APM0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LP_APM0_INTR_MAP_S 0
/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_MSPI_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_MSPI_INTR_MAP_M (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S)
#define INTMTX_CORE0_MSPI_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_MSPI_INTR_MAP_S 0
/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_I2S1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_M (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S)
#define INTMTX_CORE0_I2S1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2S1_INTR_MAP_S 0
/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_UHCI0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_UHCI0_INTR_MAP_M (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S)
#define INTMTX_CORE0_UHCI0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_UHCI0_INTR_MAP_S 0
/** INTMTX_CORE0_UART0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_UART0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_UART0_INTR_MAP_M (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S)
#define INTMTX_CORE0_UART0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_UART0_INTR_MAP_S 0
/** INTMTX_CORE0_UART1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_UART1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_UART1_INTR_MAP_M (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S)
#define INTMTX_CORE0_UART1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_UART1_INTR_MAP_S 0
/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_LEDC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_LEDC_INTR_MAP_M (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S)
#define INTMTX_CORE0_LEDC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_LEDC_INTR_MAP_S 0
/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CAN0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CAN0_INTR_MAP_M (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S)
#define INTMTX_CORE0_CAN0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CAN0_INTR_MAP_S 0
/** INTMTX_CORE0_CAN1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
/** INTMTX_CORE0_CAN1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_CAN1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_CAN1_INTR_MAP_M (INTMTX_CORE0_CAN1_INTR_MAP_V << INTMTX_CORE0_CAN1_INTR_MAP_S)
#define INTMTX_CORE0_CAN1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_CAN1_INTR_MAP_S 0
/** INTMTX_CORE0_USB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_USB_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_USB_INTR_MAP_M (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S)
#define INTMTX_CORE0_USB_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_USB_INTR_MAP_S 0
/** INTMTX_CORE0_RMT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_RMT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_RMT_INTR_MAP_M (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S)
#define INTMTX_CORE0_RMT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_RMT_INTR_MAP_S 0
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S)
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S 0
/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG0_T0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG0_T0_INTR_MAP_M (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S)
#define INTMTX_CORE0_TG0_T0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG0_T0_INTR_MAP_S 0
/** INTMTX_CORE0_TG0_T1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
/** INTMTX_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG0_T1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG0_T1_INTR_MAP_M (INTMTX_CORE0_TG0_T1_INTR_MAP_V << INTMTX_CORE0_TG0_T1_INTR_MAP_S)
#define INTMTX_CORE0_TG0_T1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG0_T1_INTR_MAP_S 0
/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG0_WDT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S)
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S 0
/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG1_T0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG1_T0_INTR_MAP_M (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S)
#define INTMTX_CORE0_TG1_T0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG1_T0_INTR_MAP_S 0
/** INTMTX_CORE0_TG1_T1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
/** INTMTX_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG1_T1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG1_T1_INTR_MAP_M (INTMTX_CORE0_TG1_T1_INTR_MAP_V << INTMTX_CORE0_TG1_T1_INTR_MAP_S)
#define INTMTX_CORE0_TG1_T1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG1_T1_INTR_MAP_S 0
/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_TG1_WDT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S)
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S 0
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0
/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_APB_ADC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_APB_ADC_INTR_MAP_M (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S)
#define INTMTX_CORE0_APB_ADC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_APB_ADC_INTR_MAP_S 0
/** INTMTX_CORE0_PWM_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PWM_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PWM_INTR_MAP_M (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S)
#define INTMTX_CORE0_PWM_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PWM_INTR_MAP_S 0
/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PCNT_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PCNT_INTR_MAP_M (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S)
#define INTMTX_CORE0_PCNT_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PCNT_INTR_MAP_S 0
/** INTMTX_CORE0_PARL_IO_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
/** INTMTX_CORE0_PARL_IO_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_PARL_IO_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_PARL_IO_INTR_MAP_M (INTMTX_CORE0_PARL_IO_INTR_MAP_V << INTMTX_CORE0_PARL_IO_INTR_MAP_S)
#define INTMTX_CORE0_PARL_IO_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_PARL_IO_INTR_MAP_S 0
/** INTMTX_CORE0_SLC0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
/** INTMTX_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SLC0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SLC0_INTR_MAP_M (INTMTX_CORE0_SLC0_INTR_MAP_V << INTMTX_CORE0_SLC0_INTR_MAP_S)
#define INTMTX_CORE0_SLC0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SLC0_INTR_MAP_S 0
/** INTMTX_CORE0_SLC1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
/** INTMTX_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SLC1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SLC1_INTR_MAP_M (INTMTX_CORE0_SLC1_INTR_MAP_V << INTMTX_CORE0_SLC1_INTR_MAP_S)
#define INTMTX_CORE0_SLC1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SLC1_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S)
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S)
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S)
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x114)
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S)
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x118)
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S)
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S 0
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x11c)
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S)
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S 0
/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x120)
/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_GPSPI2_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_GPSPI2_INTR_MAP_M (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S)
#define INTMTX_CORE0_GPSPI2_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_GPSPI2_INTR_MAP_S 0
/** INTMTX_CORE0_AES_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x124)
/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_AES_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_AES_INTR_MAP_M (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S)
#define INTMTX_CORE0_AES_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_AES_INTR_MAP_S 0
/** INTMTX_CORE0_SHA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x128)
/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_SHA_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_SHA_INTR_MAP_M (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S)
#define INTMTX_CORE0_SHA_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_SHA_INTR_MAP_S 0
/** INTMTX_CORE0_RSA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x12c)
/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_RSA_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_RSA_INTR_MAP_M (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S)
#define INTMTX_CORE0_RSA_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_RSA_INTR_MAP_S 0
/** INTMTX_CORE0_ECC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x130)
/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_ECC_INTR_MAP 0x0000001FU
#define INTMTX_CORE0_ECC_INTR_MAP_M (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S)
#define INTMTX_CORE0_ECC_INTR_MAP_V 0x0000001FU
#define INTMTX_CORE0_ECC_INTR_MAP_S 0
/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x134)
/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_INT_STATUS_0 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_0_M (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S)
#define INTMTX_CORE0_INT_STATUS_0_V 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_0_S 0
/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x138)
/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_INT_STATUS_1 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_1_M (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S)
#define INTMTX_CORE0_INT_STATUS_1_V 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_1_S 0
/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x13c)
/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTMTX_CORE0_INT_STATUS_2 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_2_M (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S)
#define INTMTX_CORE0_INT_STATUS_2_V 0xFFFFFFFFU
#define INTMTX_CORE0_INT_STATUS_2_S 0
/** INTMTX_CORE0_CLOCK_GATE_REG register
* register description
*/
#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x140)
/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define INTMTX_CORE0_REG_CLK_EN (BIT(0))
#define INTMTX_CORE0_REG_CLK_EN_M (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S)
#define INTMTX_CORE0_REG_CLK_EN_V 0x00000001U
#define INTMTX_CORE0_REG_CLK_EN_S 0
/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
* register description
*/
#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35664144;
* Need add description
*/
#define INTMTX_CORE0_INTERRUPT_REG_DATE 0x0FFFFFFFU
#define INTMTX_CORE0_INTERRUPT_REG_DATE_M (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S)
#define INTMTX_CORE0_INTERRUPT_REG_DATE_V 0x0FFFFFFFU
#define INTMTX_CORE0_INTERRUPT_REG_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/interrupt_matrix_struct.h Normal file
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/clic_reg.h"
#include "soc/soc_caps.h"
// ESP32P4 should use the CLIC controller as the interrupt controller instead of INTC (SOC_INT_CLIC_SUPPORTED = y)
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG
#define INTERRUPT_CORE1_CPU_INT_THRESH_REG CLIC_INT_THRESH_REG

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CORE0_CPU_INT_ENABLE_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTPRI_BASE + 0x0)
/** INTPRI_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_ENABLE 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_ENABLE_M (INTPRI_CORE0_CPU_INT_ENABLE_V << INTPRI_CORE0_CPU_INT_ENABLE_S)
#define INTPRI_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_ENABLE_S 0
/** INTPRI_CORE0_CPU_INT_TYPE_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_TYPE_REG (DR_REG_INTPRI_BASE + 0x4)
/** INTPRI_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_TYPE 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_TYPE_M (INTPRI_CORE0_CPU_INT_TYPE_V << INTPRI_CORE0_CPU_INT_TYPE_S)
#define INTPRI_CORE0_CPU_INT_TYPE_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_TYPE_S 0
/** INTPRI_CORE0_CPU_INT_EIP_STATUS_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTPRI_BASE + 0x8)
/** INTPRI_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_M (INTPRI_CORE0_CPU_INT_EIP_STATUS_V << INTPRI_CORE0_CPU_INT_EIP_STATUS_S)
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_EIP_STATUS_S 0
/** INTPRI_CORE0_CPU_INT_PRI_0_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTPRI_BASE + 0xc)
/** INTPRI_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_0_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_0_MAP_M (INTPRI_CORE0_CPU_PRI_0_MAP_V << INTPRI_CORE0_CPU_PRI_0_MAP_S)
#define INTPRI_CORE0_CPU_PRI_0_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_0_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_1_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTPRI_BASE + 0x10)
/** INTPRI_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_1_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_1_MAP_M (INTPRI_CORE0_CPU_PRI_1_MAP_V << INTPRI_CORE0_CPU_PRI_1_MAP_S)
#define INTPRI_CORE0_CPU_PRI_1_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_1_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_2_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTPRI_BASE + 0x14)
/** INTPRI_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_2_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_2_MAP_M (INTPRI_CORE0_CPU_PRI_2_MAP_V << INTPRI_CORE0_CPU_PRI_2_MAP_S)
#define INTPRI_CORE0_CPU_PRI_2_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_2_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_3_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTPRI_BASE + 0x18)
/** INTPRI_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_3_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_3_MAP_M (INTPRI_CORE0_CPU_PRI_3_MAP_V << INTPRI_CORE0_CPU_PRI_3_MAP_S)
#define INTPRI_CORE0_CPU_PRI_3_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_3_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_4_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTPRI_BASE + 0x1c)
/** INTPRI_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_4_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_4_MAP_M (INTPRI_CORE0_CPU_PRI_4_MAP_V << INTPRI_CORE0_CPU_PRI_4_MAP_S)
#define INTPRI_CORE0_CPU_PRI_4_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_4_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_5_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTPRI_BASE + 0x20)
/** INTPRI_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_5_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_5_MAP_M (INTPRI_CORE0_CPU_PRI_5_MAP_V << INTPRI_CORE0_CPU_PRI_5_MAP_S)
#define INTPRI_CORE0_CPU_PRI_5_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_5_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_6_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTPRI_BASE + 0x24)
/** INTPRI_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_6_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_6_MAP_M (INTPRI_CORE0_CPU_PRI_6_MAP_V << INTPRI_CORE0_CPU_PRI_6_MAP_S)
#define INTPRI_CORE0_CPU_PRI_6_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_6_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_7_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTPRI_BASE + 0x28)
/** INTPRI_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_7_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_7_MAP_M (INTPRI_CORE0_CPU_PRI_7_MAP_V << INTPRI_CORE0_CPU_PRI_7_MAP_S)
#define INTPRI_CORE0_CPU_PRI_7_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_7_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_8_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTPRI_BASE + 0x2c)
/** INTPRI_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_8_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_8_MAP_M (INTPRI_CORE0_CPU_PRI_8_MAP_V << INTPRI_CORE0_CPU_PRI_8_MAP_S)
#define INTPRI_CORE0_CPU_PRI_8_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_8_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_9_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTPRI_BASE + 0x30)
/** INTPRI_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_9_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_9_MAP_M (INTPRI_CORE0_CPU_PRI_9_MAP_V << INTPRI_CORE0_CPU_PRI_9_MAP_S)
#define INTPRI_CORE0_CPU_PRI_9_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_9_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_10_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTPRI_BASE + 0x34)
/** INTPRI_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_10_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_10_MAP_M (INTPRI_CORE0_CPU_PRI_10_MAP_V << INTPRI_CORE0_CPU_PRI_10_MAP_S)
#define INTPRI_CORE0_CPU_PRI_10_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_10_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_11_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTPRI_BASE + 0x38)
/** INTPRI_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_11_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_11_MAP_M (INTPRI_CORE0_CPU_PRI_11_MAP_V << INTPRI_CORE0_CPU_PRI_11_MAP_S)
#define INTPRI_CORE0_CPU_PRI_11_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_11_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_12_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTPRI_BASE + 0x3c)
/** INTPRI_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_12_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_12_MAP_M (INTPRI_CORE0_CPU_PRI_12_MAP_V << INTPRI_CORE0_CPU_PRI_12_MAP_S)
#define INTPRI_CORE0_CPU_PRI_12_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_12_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_13_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTPRI_BASE + 0x40)
/** INTPRI_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_13_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_13_MAP_M (INTPRI_CORE0_CPU_PRI_13_MAP_V << INTPRI_CORE0_CPU_PRI_13_MAP_S)
#define INTPRI_CORE0_CPU_PRI_13_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_13_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_14_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTPRI_BASE + 0x44)
/** INTPRI_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_14_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_14_MAP_M (INTPRI_CORE0_CPU_PRI_14_MAP_V << INTPRI_CORE0_CPU_PRI_14_MAP_S)
#define INTPRI_CORE0_CPU_PRI_14_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_14_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_15_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTPRI_BASE + 0x48)
/** INTPRI_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_15_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_15_MAP_M (INTPRI_CORE0_CPU_PRI_15_MAP_V << INTPRI_CORE0_CPU_PRI_15_MAP_S)
#define INTPRI_CORE0_CPU_PRI_15_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_15_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_16_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTPRI_BASE + 0x4c)
/** INTPRI_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_16_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_16_MAP_M (INTPRI_CORE0_CPU_PRI_16_MAP_V << INTPRI_CORE0_CPU_PRI_16_MAP_S)
#define INTPRI_CORE0_CPU_PRI_16_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_16_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_17_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTPRI_BASE + 0x50)
/** INTPRI_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_17_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_17_MAP_M (INTPRI_CORE0_CPU_PRI_17_MAP_V << INTPRI_CORE0_CPU_PRI_17_MAP_S)
#define INTPRI_CORE0_CPU_PRI_17_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_17_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_18_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTPRI_BASE + 0x54)
/** INTPRI_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_18_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_18_MAP_M (INTPRI_CORE0_CPU_PRI_18_MAP_V << INTPRI_CORE0_CPU_PRI_18_MAP_S)
#define INTPRI_CORE0_CPU_PRI_18_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_18_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_19_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTPRI_BASE + 0x58)
/** INTPRI_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_19_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_19_MAP_M (INTPRI_CORE0_CPU_PRI_19_MAP_V << INTPRI_CORE0_CPU_PRI_19_MAP_S)
#define INTPRI_CORE0_CPU_PRI_19_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_19_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_20_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTPRI_BASE + 0x5c)
/** INTPRI_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_20_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_20_MAP_M (INTPRI_CORE0_CPU_PRI_20_MAP_V << INTPRI_CORE0_CPU_PRI_20_MAP_S)
#define INTPRI_CORE0_CPU_PRI_20_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_20_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_21_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTPRI_BASE + 0x60)
/** INTPRI_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_21_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_21_MAP_M (INTPRI_CORE0_CPU_PRI_21_MAP_V << INTPRI_CORE0_CPU_PRI_21_MAP_S)
#define INTPRI_CORE0_CPU_PRI_21_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_21_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_22_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTPRI_BASE + 0x64)
/** INTPRI_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_22_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_22_MAP_M (INTPRI_CORE0_CPU_PRI_22_MAP_V << INTPRI_CORE0_CPU_PRI_22_MAP_S)
#define INTPRI_CORE0_CPU_PRI_22_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_22_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_23_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTPRI_BASE + 0x68)
/** INTPRI_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_23_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_23_MAP_M (INTPRI_CORE0_CPU_PRI_23_MAP_V << INTPRI_CORE0_CPU_PRI_23_MAP_S)
#define INTPRI_CORE0_CPU_PRI_23_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_23_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_24_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTPRI_BASE + 0x6c)
/** INTPRI_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_24_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_24_MAP_M (INTPRI_CORE0_CPU_PRI_24_MAP_V << INTPRI_CORE0_CPU_PRI_24_MAP_S)
#define INTPRI_CORE0_CPU_PRI_24_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_24_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_25_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTPRI_BASE + 0x70)
/** INTPRI_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_25_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_25_MAP_M (INTPRI_CORE0_CPU_PRI_25_MAP_V << INTPRI_CORE0_CPU_PRI_25_MAP_S)
#define INTPRI_CORE0_CPU_PRI_25_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_25_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_26_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTPRI_BASE + 0x74)
/** INTPRI_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_26_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_26_MAP_M (INTPRI_CORE0_CPU_PRI_26_MAP_V << INTPRI_CORE0_CPU_PRI_26_MAP_S)
#define INTPRI_CORE0_CPU_PRI_26_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_26_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_27_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTPRI_BASE + 0x78)
/** INTPRI_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_27_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_27_MAP_M (INTPRI_CORE0_CPU_PRI_27_MAP_V << INTPRI_CORE0_CPU_PRI_27_MAP_S)
#define INTPRI_CORE0_CPU_PRI_27_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_27_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_28_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTPRI_BASE + 0x7c)
/** INTPRI_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_28_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_28_MAP_M (INTPRI_CORE0_CPU_PRI_28_MAP_V << INTPRI_CORE0_CPU_PRI_28_MAP_S)
#define INTPRI_CORE0_CPU_PRI_28_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_28_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_29_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTPRI_BASE + 0x80)
/** INTPRI_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_29_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_29_MAP_M (INTPRI_CORE0_CPU_PRI_29_MAP_V << INTPRI_CORE0_CPU_PRI_29_MAP_S)
#define INTPRI_CORE0_CPU_PRI_29_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_29_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_30_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTPRI_BASE + 0x84)
/** INTPRI_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_30_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_30_MAP_M (INTPRI_CORE0_CPU_PRI_30_MAP_V << INTPRI_CORE0_CPU_PRI_30_MAP_S)
#define INTPRI_CORE0_CPU_PRI_30_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_30_MAP_S 0
/** INTPRI_CORE0_CPU_INT_PRI_31_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTPRI_BASE + 0x88)
/** INTPRI_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_PRI_31_MAP 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_31_MAP_M (INTPRI_CORE0_CPU_PRI_31_MAP_V << INTPRI_CORE0_CPU_PRI_31_MAP_S)
#define INTPRI_CORE0_CPU_PRI_31_MAP_V 0x0000000FU
#define INTPRI_CORE0_CPU_PRI_31_MAP_S 0
/** INTPRI_CORE0_CPU_INT_THRESH_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_THRESH_REG (DR_REG_INTPRI_BASE + 0x8c)
/** INTPRI_CORE0_CPU_INT_THRESH : R/W; bitpos: [7:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_THRESH 0x000000FFU
#define INTPRI_CORE0_CPU_INT_THRESH_M (INTPRI_CORE0_CPU_INT_THRESH_V << INTPRI_CORE0_CPU_INT_THRESH_S)
#define INTPRI_CORE0_CPU_INT_THRESH_V 0x000000FFU
#define INTPRI_CORE0_CPU_INT_THRESH_S 0
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_0_S 0
/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_1_S 0
/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_2_S 0
/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_3_S 0
/** INTPRI_DATE_REG register
* register description
*/
#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 35655824;
* Need add description
*/
#define INTPRI_DATE 0x0FFFFFFFU
#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S)
#define INTPRI_DATE_V 0x0FFFFFFFU
#define INTPRI_DATE_S 0
/** INTPRI_CLOCK_GATE_REG register
* register description
*/
#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define INTPRI_CLK_EN (BIT(0))
#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
#define INTPRI_CLK_EN_V 0x00000001U
#define INTPRI_CLK_EN_S 0
/** INTPRI_CORE0_CPU_INT_CLEAR_REG register
* register description
*/
#define INTPRI_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTPRI_BASE + 0xa8)
/** INTPRI_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
#define INTPRI_CORE0_CPU_INT_CLEAR 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_CLEAR_M (INTPRI_CORE0_CPU_INT_CLEAR_V << INTPRI_CORE0_CPU_INT_CLEAR_S)
#define INTPRI_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFFU
#define INTPRI_CORE0_CPU_INT_CLEAR_S 0
/** INTPRI_RND_ECO_REG register
* redcy eco register.
*/
#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac)
/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_ENA (BIT(0))
#define INTPRI_REDCY_ENA_M (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S)
#define INTPRI_REDCY_ENA_V 0x00000001U
#define INTPRI_REDCY_ENA_S 0
/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_RESULT (BIT(1))
#define INTPRI_REDCY_RESULT_M (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S)
#define INTPRI_REDCY_RESULT_V 0x00000001U
#define INTPRI_REDCY_RESULT_S 1
/** INTPRI_RND_ECO_LOW_REG register
* redcy eco low register.
*/
#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0)
/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_LOW 0xFFFFFFFFU
#define INTPRI_REDCY_LOW_M (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S)
#define INTPRI_REDCY_LOW_V 0xFFFFFFFFU
#define INTPRI_REDCY_LOW_S 0
/** INTPRI_RND_ECO_HIGH_REG register
* redcy eco high register.
*/
#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc)
/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
#define INTPRI_REDCY_HIGH 0xFFFFFFFFU
#define INTPRI_REDCY_HIGH_M (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S)
#define INTPRI_REDCY_HIGH_V 0xFFFFFFFFU
#define INTPRI_REDCY_HIGH_S 0
#ifdef __cplusplus
}
#endif

256
components/soc/esp32p4/include/soc/intpri_struct.h Normal file
View File

@ -0,0 +1,256 @@
/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of core0_cpu_int_enable register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_enable : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_enable:32;
};
uint32_t val;
} intpri_core0_cpu_int_enable_reg_t;
/** Type of core0_cpu_int_type register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_type : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_type:32;
};
uint32_t val;
} intpri_core0_cpu_int_type_reg_t;
/** Type of core0_cpu_int_eip_status register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_eip_status : RO; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_eip_status:32;
};
uint32_t val;
} intpri_core0_cpu_int_eip_status_reg_t;
/** Type of core0_cpu_int_pri_n register
* register description
*/
typedef union {
struct {
/** map : R/W; bitpos: [3:0]; default: 0;
* Need add description
*/
uint32_t map:4;
uint32_t reserved_4:28;
};
uint32_t val;
} intpri_core0_cpu_int_pri_n_reg_t;
/** Type of core0_cpu_int_thresh register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_thresh : R/W; bitpos: [7:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_thresh:8;
uint32_t reserved_8:24;
};
uint32_t val;
} intpri_core0_cpu_int_thresh_reg_t;
/** Type of clock_gate register
* register description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_clock_gate_reg_t;
/** Type of core0_cpu_int_clear register
* register description
*/
typedef union {
struct {
/** core0_cpu_int_clear : R/W; bitpos: [31:0]; default: 0;
* Need add description
*/
uint32_t core0_cpu_int_clear:32;
};
uint32_t val;
} intpri_core0_cpu_int_clear_reg_t;
/** Group: Interrupt Registers */
/** Type of cpu_intr_from_cpu_0 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_0:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_0_reg_t;
/** Type of cpu_intr_from_cpu_1 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_1:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_1_reg_t;
/** Type of cpu_intr_from_cpu_2 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_2:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_2_reg_t;
/** Type of cpu_intr_from_cpu_3 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_3:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_3_reg_t;
/** Group: Version Registers */
/** Type of date register
* register description
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35655824;
* Need add description
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} intpri_date_reg_t;
/** Group: Redcy ECO Registers */
/** Type of rnd_eco register
* redcy eco register.
*/
typedef union {
struct {
/** redcy_ena : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_ena:1;
/** redcy_result : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} intpri_rnd_eco_reg_t;
/** Type of rnd_eco_low register
* redcy eco low register.
*/
typedef union {
struct {
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_low:32;
};
uint32_t val;
} intpri_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* redcy eco high register.
*/
typedef union {
struct {
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
uint32_t redcy_high:32;
};
uint32_t val;
} intpri_rnd_eco_high_reg_t;
typedef struct intpri_dev_t {
volatile intpri_core0_cpu_int_enable_reg_t core0_cpu_int_enable;
volatile intpri_core0_cpu_int_type_reg_t core0_cpu_int_type;
volatile intpri_core0_cpu_int_eip_status_reg_t core0_cpu_int_eip_status;
volatile intpri_core0_cpu_int_pri_n_reg_t core0_cpu_int_pri[32];
volatile intpri_core0_cpu_int_thresh_reg_t core0_cpu_int_thresh;
volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
volatile intpri_date_reg_t date;
volatile intpri_clock_gate_reg_t clock_gate;
volatile intpri_core0_cpu_int_clear_reg_t core0_cpu_int_clear;
volatile intpri_rnd_eco_reg_t rnd_eco;
volatile intpri_rnd_eco_low_reg_t rnd_eco_low;
uint32_t reserved_0b4[210];
volatile intpri_rnd_eco_high_reg_t rnd_eco_high;
} intpri_dev_t;
extern intpri_dev_t INTPRI;
#ifndef __cplusplus
_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

60
components/soc/esp32p4/include/soc/io_mux_reg.h
View File

@ -64,6 +64,17 @@
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
@ -138,6 +149,55 @@
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define SPI_CS1_GPIO_NUM 26
#define SPI_HD_GPIO_NUM 27
#define SPI_WP_GPIO_NUM 28
#define SPI_CS0_GPIO_NUM 29
#define SPI_CLK_GPIO_NUM 30
#define SPI_Q_GPIO_NUM 31
#define SPI_D_GPIO_NUM 32
#define SPI_D4_GPIO_NUM 33
#define SPI_D5_GPIO_NUM 34
#define SPI_D6_GPIO_NUM 35
#define SPI_D7_GPIO_NUM 36
#define SPI_DQS_GPIO_NUM 37
#define PIN_FUNC_SPI_DEBUG 4
#define FLASH_CS_DEBUG_GPIO_NUM 49
#define FLASH_Q_DEBUG_GPIO_NUM 50
#define FLASH_WP_DEBUG_GPIO_NUM 51
#define FLASH_HD_DEBUG_GPIO_NUM 52
#define FLASH_CLK_DEBUG_GPIO_NUM 53
#define FLASH_D_DEBUG_GPIO_NUM 54
#define PSRAM_D_DEBUG_GPIO_NUM 28
#define PSRAM_Q_DEBUG_GPIO_NUM 29
#define PSRAM_WP_DEBUG_GPIO_NUM 30
#define PSRAM_HOLD_DEBUG_GPIO_NUM 31
#define PSRAM_DP4_DEBUG_GPIO_NUM 32
#define PSRAM_DP5_DEBUG_GPIO_NUM 33
#define PSRAM_DP6_DEBUG_GPIO_NUM 34
#define PSRAM_DP7_DEBUG_GPIO_NUM 35
#define PSRAM_DQS0_DEBUG_GPIO_NUM 36
#define PSRAM_CLK_DEBUG_GPIO_NUM 22
#define PSRAM_CS_DEBUG_GPIO_NUM 23
#define PSRAM_DP8_DEBUG_GPIO_NUM 39
#define PSRAM_DP9_DEBUG_GPIO_NUM 40
#define PSRAM_DP10_DEBUG_GPIO_NUM 41
#define PSRAM_DP11_DEBUG_GPIO_NUM 42
#define PSRAM_DP12_DEBUG_GPIO_NUM 43
#define PSRAM_DP13_DEBUG_GPIO_NUM 44
#define PSRAM_DP14_DEBUG_GPIO_NUM 45
#define PSRAM_DP15_DEBUG_GPIO_NUM 46
#define PSRAM_DQS1_DEBUG_GPIO_NUM 47
#define SD_CLK_GPIO_NUM 12
#define SD_CMD_GPIO_NUM 11
#define SD_DATA0_GPIO_NUM 13
#define SD_DATA1_GPIO_NUM 14
#define SD_DATA2_GPIO_NUM 9
#define SD_DATA3_GPIO_NUM 10
#define MAX_RTC_GPIO_NUM 15
#define MAX_PAD_GPIO_NUM 56
#define MAX_GPIO_NUM 56

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components/soc/esp32p4/include/soc/lcd_cam_reg.h Normal file
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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_LCD_CAM_REG_H_
#define _SOC_LCD_CAM_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define LCD_CAM_LCD_CLOCK_REG (DR_REG_LCD_CAM_BASE + 0x0)
/* LCD_CAM_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: Set this bit to enable clk gate.*/
#define LCD_CAM_CLK_EN (BIT(31))
#define LCD_CAM_CLK_EN_M (BIT(31))
#define LCD_CAM_CLK_EN_V 0x1
#define LCD_CAM_CLK_EN_S 31
/* LCD_CAM_LCD_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
/*description: Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/
#define LCD_CAM_LCD_CLK_SEL 0x00000003
#define LCD_CAM_LCD_CLK_SEL_M ((LCD_CAM_LCD_CLK_SEL_V)<<(LCD_CAM_LCD_CLK_SEL_S))
#define LCD_CAM_LCD_CLK_SEL_V 0x3
#define LCD_CAM_LCD_CLK_SEL_S 29
/* LCD_CAM_LCD_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
/*description: Fractional clock divider denominator value.*/
#define LCD_CAM_LCD_CLKM_DIV_A 0x0000003F
#define LCD_CAM_LCD_CLKM_DIV_A_M ((LCD_CAM_LCD_CLKM_DIV_A_V)<<(LCD_CAM_LCD_CLKM_DIV_A_S))
#define LCD_CAM_LCD_CLKM_DIV_A_V 0x3F
#define LCD_CAM_LCD_CLKM_DIV_A_S 23
/* LCD_CAM_LCD_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
/*description: Fractional clock divider numerator value.*/
#define LCD_CAM_LCD_CLKM_DIV_B 0x0000003F
#define LCD_CAM_LCD_CLKM_DIV_B_M ((LCD_CAM_LCD_CLKM_DIV_B_V)<<(LCD_CAM_LCD_CLKM_DIV_B_S))
#define LCD_CAM_LCD_CLKM_DIV_B_V 0x3F
#define LCD_CAM_LCD_CLKM_DIV_B_S 17
/* LCD_CAM_LCD_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
/*description: Integral LCD clock divider value.*/
#define LCD_CAM_LCD_CLKM_DIV_NUM 0x000000FF
#define LCD_CAM_LCD_CLKM_DIV_NUM_M ((LCD_CAM_LCD_CLKM_DIV_NUM_V)<<(LCD_CAM_LCD_CLKM_DIV_NUM_S))
#define LCD_CAM_LCD_CLKM_DIV_NUM_V 0xFF
#define LCD_CAM_LCD_CLKM_DIV_NUM_S 9
/* LCD_CAM_LCD_CK_OUT_EDGE : R/W ;bitpos:[8] ;default: 1'h0 ; */
/*description: 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is l
ow in the second half data cycle..*/
#define LCD_CAM_LCD_CK_OUT_EDGE (BIT(8))
#define LCD_CAM_LCD_CK_OUT_EDGE_M (BIT(8))
#define LCD_CAM_LCD_CK_OUT_EDGE_V 0x1
#define LCD_CAM_LCD_CK_OUT_EDGE_S 8
/* LCD_CAM_LCD_CK_IDLE_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle..*/
#define LCD_CAM_LCD_CK_IDLE_EDGE (BIT(7))
#define LCD_CAM_LCD_CK_IDLE_EDGE_M (BIT(7))
#define LCD_CAM_LCD_CK_IDLE_EDGE_V 0x1
#define LCD_CAM_LCD_CK_IDLE_EDGE_S 7
/* LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W ;bitpos:[6] ;default: 1'h1 ; */
/*description: 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)..*/
#define LCD_CAM_LCD_CLK_EQU_SYSCLK (BIT(6))
#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M (BIT(6))
#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V 0x1
#define LCD_CAM_LCD_CLK_EQU_SYSCLK_S 6
/* LCD_CAM_LCD_CLKCNT_N : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
/*description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0..*/
#define LCD_CAM_LCD_CLKCNT_N 0x0000003F
#define LCD_CAM_LCD_CLKCNT_N_M ((LCD_CAM_LCD_CLKCNT_N_V)<<(LCD_CAM_LCD_CLKCNT_N_S))
#define LCD_CAM_LCD_CLKCNT_N_V 0x3F
#define LCD_CAM_LCD_CLKCNT_N_S 0
#define LCD_CAM_CAM_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x4)
/* LCD_CAM_CAM_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
/*description: Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock..*/
#define LCD_CAM_CAM_CLK_SEL 0x00000003
#define LCD_CAM_CAM_CLK_SEL_M ((LCD_CAM_CAM_CLK_SEL_V)<<(LCD_CAM_CAM_CLK_SEL_S))
#define LCD_CAM_CAM_CLK_SEL_V 0x3
#define LCD_CAM_CAM_CLK_SEL_S 29
/* LCD_CAM_CAM_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
/*description: Fractional clock divider denominator value.*/
#define LCD_CAM_CAM_CLKM_DIV_A 0x0000003F
#define LCD_CAM_CAM_CLKM_DIV_A_M ((LCD_CAM_CAM_CLKM_DIV_A_V)<<(LCD_CAM_CAM_CLKM_DIV_A_S))
#define LCD_CAM_CAM_CLKM_DIV_A_V 0x3F
#define LCD_CAM_CAM_CLKM_DIV_A_S 23
/* LCD_CAM_CAM_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
/*description: Fractional clock divider numerator value.*/
#define LCD_CAM_CAM_CLKM_DIV_B 0x0000003F
#define LCD_CAM_CAM_CLKM_DIV_B_M ((LCD_CAM_CAM_CLKM_DIV_B_V)<<(LCD_CAM_CAM_CLKM_DIV_B_S))
#define LCD_CAM_CAM_CLKM_DIV_B_V 0x3F
#define LCD_CAM_CAM_CLKM_DIV_B_S 17
/* LCD_CAM_CAM_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
/*description: Integral Camera clock divider value.*/
#define LCD_CAM_CAM_CLKM_DIV_NUM 0x000000FF
#define LCD_CAM_CAM_CLKM_DIV_NUM_M ((LCD_CAM_CAM_CLKM_DIV_NUM_V)<<(LCD_CAM_CAM_CLKM_DIV_NUM_S))
#define LCD_CAM_CAM_CLKM_DIV_NUM_V 0xFF
#define LCD_CAM_CAM_CLKM_DIV_NUM_S 9
/* LCD_CAM_CAM_VS_EOF_EN : R/W ;bitpos:[8] ;default: 1'h0 ; */
/*description: 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_
data_cyclelen..*/
#define LCD_CAM_CAM_VS_EOF_EN (BIT(8))
#define LCD_CAM_CAM_VS_EOF_EN_M (BIT(8))
#define LCD_CAM_CAM_VS_EOF_EN_V 0x1
#define LCD_CAM_CAM_VS_EOF_EN_S 8
/* LCD_CAM_CAM_LINE_INT_EN : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: 1: Enable to generate CAM_HS_INT. 0: Disable..*/
#define LCD_CAM_CAM_LINE_INT_EN (BIT(7))
#define LCD_CAM_CAM_LINE_INT_EN_M (BIT(7))
#define LCD_CAM_CAM_LINE_INT_EN_V 0x1
#define LCD_CAM_CAM_LINE_INT_EN_S 7
/* LCD_CAM_CAM_BIT_ORDER : R/W ;bitpos:[6] ;default: 1'h0 ; */
/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/
#define LCD_CAM_CAM_BIT_ORDER (BIT(6))
#define LCD_CAM_CAM_BIT_ORDER_M (BIT(6))
#define LCD_CAM_CAM_BIT_ORDER_V 0x1
#define LCD_CAM_CAM_BIT_ORDER_S 6
/* LCD_CAM_CAM_BYTE_ORDER : R/W ;bitpos:[5] ;default: 1'h0 ; */
/*description: 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byt
e mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change..*/
#define LCD_CAM_CAM_BYTE_ORDER (BIT(5))
#define LCD_CAM_CAM_BYTE_ORDER_M (BIT(5))
#define LCD_CAM_CAM_BYTE_ORDER_V 0x1
#define LCD_CAM_CAM_BYTE_ORDER_S 5
/* LCD_CAM_CAM_UPDATE_REG : R/W/SC ;bitpos:[4] ;default: 1'h0 ; */
/*description: 1: Update Camera registers, will be cleared by hardware. 0 : Not care..*/
#define LCD_CAM_CAM_UPDATE_REG (BIT(4))
#define LCD_CAM_CAM_UPDATE_REG_M (BIT(4))
#define LCD_CAM_CAM_UPDATE_REG_V 0x1
#define LCD_CAM_CAM_UPDATE_REG_S 4
/* LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W ;bitpos:[3:1] ;default: 3'h0 ; */
/*description: Filter threshold value for CAM_VSYNC signal..*/
#define LCD_CAM_CAM_VSYNC_FILTER_THRES 0x00000007
#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M ((LCD_CAM_CAM_VSYNC_FILTER_THRES_V)<<(LCD_CAM_CAM_VSYNC_FILTER_THRES_S))
#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V 0x7
#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S 1
/* LCD_CAM_CAM_STOP_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop
..*/
#define LCD_CAM_CAM_STOP_EN (BIT(0))
#define LCD_CAM_CAM_STOP_EN_M (BIT(0))
#define LCD_CAM_CAM_STOP_EN_V 0x1
#define LCD_CAM_CAM_STOP_EN_S 0
#define LCD_CAM_CAM_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x8)
/* LCD_CAM_CAM_AFIFO_RESET : WT ;bitpos:[31] ;default: 1'h0 ; */
/*description: Camera AFIFO reset signal..*/
#define LCD_CAM_CAM_AFIFO_RESET (BIT(31))
#define LCD_CAM_CAM_AFIFO_RESET_M (BIT(31))
#define LCD_CAM_CAM_AFIFO_RESET_V 0x1
#define LCD_CAM_CAM_AFIFO_RESET_S 31
/* LCD_CAM_CAM_RESET : WT ;bitpos:[30] ;default: 1'h0 ; */
/*description: Camera module reset signal..*/
#define LCD_CAM_CAM_RESET (BIT(30))
#define LCD_CAM_CAM_RESET_M (BIT(30))
#define LCD_CAM_CAM_RESET_V 0x1
#define LCD_CAM_CAM_RESET_S 30
/* LCD_CAM_CAM_START : R/W/SC ;bitpos:[29] ;default: 1'h0 ; */
/*description: Camera module start signal..*/
#define LCD_CAM_CAM_START (BIT(29))
#define LCD_CAM_CAM_START_M (BIT(29))
#define LCD_CAM_CAM_START_V 0x1
#define LCD_CAM_CAM_START_S 29
/* LCD_CAM_CAM_VH_DE_MODE_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
/*description: 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control si
gnals are CAM_DE and CAM_VSYNC..*/
#define LCD_CAM_CAM_VH_DE_MODE_EN (BIT(28))
#define LCD_CAM_CAM_VH_DE_MODE_EN_M (BIT(28))
#define LCD_CAM_CAM_VH_DE_MODE_EN_V 0x1
#define LCD_CAM_CAM_VH_DE_MODE_EN_S 28
/* LCD_CAM_CAM_VSYNC_INV : R/W ;bitpos:[27] ;default: 1'h0 ; */
/*description: CAM_VSYNC invert enable signal, valid in high level..*/
#define LCD_CAM_CAM_VSYNC_INV (BIT(27))
#define LCD_CAM_CAM_VSYNC_INV_M (BIT(27))
#define LCD_CAM_CAM_VSYNC_INV_V 0x1
#define LCD_CAM_CAM_VSYNC_INV_S 27
/* LCD_CAM_CAM_HSYNC_INV : R/W ;bitpos:[26] ;default: 1'h0 ; */
/*description: CAM_HSYNC invert enable signal, valid in high level..*/
#define LCD_CAM_CAM_HSYNC_INV (BIT(26))
#define LCD_CAM_CAM_HSYNC_INV_M (BIT(26))
#define LCD_CAM_CAM_HSYNC_INV_V 0x1
#define LCD_CAM_CAM_HSYNC_INV_S 26
/* LCD_CAM_CAM_DE_INV : R/W ;bitpos:[25] ;default: 1'h0 ; */
/*description: CAM_DE invert enable signal, valid in high level..*/
#define LCD_CAM_CAM_DE_INV (BIT(25))
#define LCD_CAM_CAM_DE_INV_M (BIT(25))
#define LCD_CAM_CAM_DE_INV_V 0x1
#define LCD_CAM_CAM_DE_INV_S 25
/* LCD_CAM_CAM_2BYTE_EN : R/W ;bitpos:[24] ;default: 1'h0 ; */
/*description: 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8
..*/
#define LCD_CAM_CAM_2BYTE_EN (BIT(24))
#define LCD_CAM_CAM_2BYTE_EN_M (BIT(24))
#define LCD_CAM_CAM_2BYTE_EN_V 0x1
#define LCD_CAM_CAM_2BYTE_EN_S 24
/* LCD_CAM_CAM_VSYNC_FILTER_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */
/*description: 1: Enable CAM_VSYNC filter function. 0: bypass..*/
#define LCD_CAM_CAM_VSYNC_FILTER_EN (BIT(23))
#define LCD_CAM_CAM_VSYNC_FILTER_EN_M (BIT(23))
#define LCD_CAM_CAM_VSYNC_FILTER_EN_V 0x1
#define LCD_CAM_CAM_VSYNC_FILTER_EN_S 23
/* LCD_CAM_CAM_CLK_INV : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: 1: Invert the input signal CAM_PCLK. 0: Not invert..*/
#define LCD_CAM_CAM_CLK_INV (BIT(22))
#define LCD_CAM_CAM_CLK_INV_M (BIT(22))
#define LCD_CAM_CAM_CLK_INV_V 0x1
#define LCD_CAM_CAM_CLK_INV_S 22
/* LCD_CAM_CAM_LINE_INT_NUM : R/W ;bitpos:[21:16] ;default: 6'h0 ; */
/*description: The line number minus 1 to generate cam_hs_int..*/
#define LCD_CAM_CAM_LINE_INT_NUM 0x0000003F
#define LCD_CAM_CAM_LINE_INT_NUM_M ((LCD_CAM_CAM_LINE_INT_NUM_V)<<(LCD_CAM_CAM_LINE_INT_NUM_S))
#define LCD_CAM_CAM_LINE_INT_NUM_V 0x3F
#define LCD_CAM_CAM_LINE_INT_NUM_S 16
/* LCD_CAM_CAM_REC_DATA_BYTELEN : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int..*/
#define LCD_CAM_CAM_REC_DATA_BYTELEN 0x0000FFFF
#define LCD_CAM_CAM_REC_DATA_BYTELEN_M ((LCD_CAM_CAM_REC_DATA_BYTELEN_V)<<(LCD_CAM_CAM_REC_DATA_BYTELEN_S))
#define LCD_CAM_CAM_REC_DATA_BYTELEN_V 0xFFFF
#define LCD_CAM_CAM_REC_DATA_BYTELEN_S 0
#define LCD_CAM_CAM_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0xC)
/* LCD_CAM_CAM_CONV_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: 0: Bypass converter. 1: Enable converter..*/
#define LCD_CAM_CAM_CONV_ENABLE (BIT(31))
#define LCD_CAM_CAM_CONV_ENABLE_M (BIT(31))
#define LCD_CAM_CAM_CONV_ENABLE_V 0x1
#define LCD_CAM_CAM_CONV_ENABLE_S 31
/* LCD_CAM_CAM_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: 0: YUV to RGB. 1: RGB to YUV..*/
#define LCD_CAM_CAM_CONV_TRANS_MODE (BIT(30))
#define LCD_CAM_CAM_CONV_TRANS_MODE_M (BIT(30))
#define LCD_CAM_CAM_CONV_TRANS_MODE_V 0x1
#define LCD_CAM_CAM_CONV_TRANS_MODE_S 30
/* LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: 0: 16bits mode. 1: 8bits mode..*/
#define LCD_CAM_CAM_CONV_MODE_8BITS_ON (BIT(29))
#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M (BIT(29))
#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V 0x1
#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S 29
/* LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/
#define LCD_CAM_CAM_CONV_DATA_IN_MODE (BIT(28))
#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M (BIT(28))
#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V 0x1
#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S 28
/* LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/
#define LCD_CAM_CAM_CONV_DATA_OUT_MODE (BIT(27))
#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M (BIT(27))
#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V 0x1
#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S 27
/* LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 0:BT601. 1:BT709..*/
#define LCD_CAM_CAM_CONV_PROTOCOL_MODE (BIT(26))
#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M (BIT(26))
#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V 0x1
#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S 26
/* LCD_CAM_CAM_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
mode of Data_in.*/
#define LCD_CAM_CAM_CONV_YUV_MODE 0x00000003
#define LCD_CAM_CAM_CONV_YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV_MODE_S))
#define LCD_CAM_CAM_CONV_YUV_MODE_V 0x3
#define LCD_CAM_CAM_CONV_YUV_MODE_S 24
/* LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode,
trans_mode must be set to 1..*/
#define LCD_CAM_CAM_CONV_YUV2YUV_MODE 0x00000003
#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_CAM_CONV_YUV2YUV_MODE_S))
#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V 0x3
#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S 22
/* LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: 1:invert every two 8bits input data. 2. disabled..*/
#define LCD_CAM_CAM_CONV_8BITS_DATA_INV (BIT(21))
#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M (BIT(21))
#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V 0x1
#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S 21
#define LCD_CAM_LCD_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x10)
/* LCD_CAM_LCD_CONV_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: 0: Bypass converter. 1: Enable converter..*/
#define LCD_CAM_LCD_CONV_ENABLE (BIT(31))
#define LCD_CAM_LCD_CONV_ENABLE_M (BIT(31))
#define LCD_CAM_LCD_CONV_ENABLE_V 0x1
#define LCD_CAM_LCD_CONV_ENABLE_S 31
/* LCD_CAM_LCD_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: 0: YUV to RGB. 1: RGB to YUV..*/
#define LCD_CAM_LCD_CONV_TRANS_MODE (BIT(30))
#define LCD_CAM_LCD_CONV_TRANS_MODE_M (BIT(30))
#define LCD_CAM_LCD_CONV_TRANS_MODE_V 0x1
#define LCD_CAM_LCD_CONV_TRANS_MODE_S 30
/* LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: 0: 16bits mode. 1: 8bits mode..*/
#define LCD_CAM_LCD_CONV_MODE_8BITS_ON (BIT(29))
#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M (BIT(29))
#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V 0x1
#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S 29
/* LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full.*/
#define LCD_CAM_LCD_CONV_DATA_IN_MODE (BIT(28))
#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M (BIT(28))
#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V 0x1
#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S 28
/* LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full.*/
#define LCD_CAM_LCD_CONV_DATA_OUT_MODE (BIT(27))
#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M (BIT(27))
#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V 0x1
#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S 27
/* LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 0:BT601. 1:BT709..*/
#define LCD_CAM_LCD_CONV_PROTOCOL_MODE (BIT(26))
#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M (BIT(26))
#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V 0x1
#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S 26
/* LCD_CAM_LCD_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
mode of Data_in.*/
#define LCD_CAM_LCD_CONV_YUV_MODE 0x00000003
#define LCD_CAM_LCD_CONV_YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV_MODE_S))
#define LCD_CAM_LCD_CONV_YUV_MODE_V 0x3
#define LCD_CAM_LCD_CONV_YUV_MODE_S 24
/* LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode,
trans_mode must be set to 1..*/
#define LCD_CAM_LCD_CONV_YUV2YUV_MODE 0x00000003
#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV2YUV_MODE_V)<<(LCD_CAM_LCD_CONV_YUV2YUV_MODE_S))
#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V 0x3
#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S 22
/* LCD_CAM_LCD_CONV_TXTORX : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: 0: txtorx mode off. 1: txtorx mode on..*/
#define LCD_CAM_LCD_CONV_TXTORX (BIT(21))
#define LCD_CAM_LCD_CONV_TXTORX_M (BIT(21))
#define LCD_CAM_LCD_CONV_TXTORX_V 0x1
#define LCD_CAM_LCD_CONV_TXTORX_S 21
/* LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: 1:invert every two 8bits input data. 2. disabled..*/
#define LCD_CAM_LCD_CONV_8BITS_DATA_INV (BIT(20))
#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M (BIT(20))
#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V 0x1
#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S 20
#define LCD_CAM_LCD_USER_REG (DR_REG_LCD_CAM_BASE + 0x14)
/* LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*description: The cycle length of command phase. 1: 2 cycles. 0: 1 cycle..*/
#define LCD_CAM_LCD_CMD_2_CYCLE_EN (BIT(31))
#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M (BIT(31))
#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V 0x1
#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S 31
/* LCD_CAM_LCD_DUMMY_CYCLELEN : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
/*description: The dummy cycle length minus 1..*/
#define LCD_CAM_LCD_DUMMY_CYCLELEN 0x00000003
#define LCD_CAM_LCD_DUMMY_CYCLELEN_M ((LCD_CAM_LCD_DUMMY_CYCLELEN_V)<<(LCD_CAM_LCD_DUMMY_CYCLELEN_S))
#define LCD_CAM_LCD_DUMMY_CYCLELEN_V 0x3
#define LCD_CAM_LCD_DUMMY_CYCLELEN_S 29
/* LCD_CAM_LCD_RESET : WT ;bitpos:[28] ;default: 1'b0 ; */
/*description: The value of command..*/
#define LCD_CAM_LCD_RESET (BIT(28))
#define LCD_CAM_LCD_RESET_M (BIT(28))
#define LCD_CAM_LCD_RESET_V 0x1
#define LCD_CAM_LCD_RESET_S 28
/* LCD_CAM_LCD_START : R/W/SC ;bitpos:[27] ;default: 1'h0 ; */
/*description: LCD start sending data enable signal, valid in high level..*/
#define LCD_CAM_LCD_START (BIT(27))
#define LCD_CAM_LCD_START_M (BIT(27))
#define LCD_CAM_LCD_START_V 0x1
#define LCD_CAM_LCD_START_S 27
/* LCD_CAM_LCD_CMD : R/W ;bitpos:[26] ;default: 1'h0 ; */
/*description: 1: Be able to send command in LCD sequence when LCD starts. 0: Disable..*/
#define LCD_CAM_LCD_CMD (BIT(26))
#define LCD_CAM_LCD_CMD_M (BIT(26))
#define LCD_CAM_LCD_CMD_V 0x1
#define LCD_CAM_LCD_CMD_S 26
/* LCD_CAM_LCD_DUMMY : R/W ;bitpos:[25] ;default: 1'h0 ; */
/*description: 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable..*/
#define LCD_CAM_LCD_DUMMY (BIT(25))
#define LCD_CAM_LCD_DUMMY_M (BIT(25))
#define LCD_CAM_LCD_DUMMY_V 0x1
#define LCD_CAM_LCD_DUMMY_S 25
/* LCD_CAM_LCD_DOUT : R/W ;bitpos:[24] ;default: 1'h0 ; */
/*description: 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable..*/
#define LCD_CAM_LCD_DOUT (BIT(24))
#define LCD_CAM_LCD_DOUT_M (BIT(24))
#define LCD_CAM_LCD_DOUT_V 0x1
#define LCD_CAM_LCD_DOUT_S 24
/* LCD_CAM_LCD_BYTE_ORDER : R/W ;bitpos:[23] ;default: 1'h0 ; */
/*description: 1: invert data byte order, only valid in 2 byte mode. 0: Not change..*/
#define LCD_CAM_LCD_BYTE_ORDER (BIT(23))
#define LCD_CAM_LCD_BYTE_ORDER_M (BIT(23))
#define LCD_CAM_LCD_BYTE_ORDER_V 0x1
#define LCD_CAM_LCD_BYTE_ORDER_S 23
/* LCD_CAM_LCD_BIT_ORDER : R/W ;bitpos:[22] ;default: 1'h0 ; */
/*description: 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one b
yte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change..*/
#define LCD_CAM_LCD_BIT_ORDER (BIT(22))
#define LCD_CAM_LCD_BIT_ORDER_M (BIT(22))
#define LCD_CAM_LCD_BIT_ORDER_V 0x1
#define LCD_CAM_LCD_BIT_ORDER_S 22
/* LCD_CAM_LCD_UPDATE_REG : R/W/SC ;bitpos:[21] ;default: 1'h0 ; */
/*description: 1: Update LCD registers, will be cleared by hardware. 0 : Not care..*/
#define LCD_CAM_LCD_UPDATE_REG (BIT(21))
#define LCD_CAM_LCD_UPDATE_REG_M (BIT(21))
#define LCD_CAM_LCD_UPDATE_REG_V 0x1
#define LCD_CAM_LCD_UPDATE_REG_S 21
/* LCD_CAM_LCD_BYTE_MODE : R/W ;bitpos:[20:19] ;default: 2'h0 ; */
/*description: 2: 24bit mode. 1: 16bit mode. 0: 8bit mode.*/
#define LCD_CAM_LCD_BYTE_MODE 0x00000003
#define LCD_CAM_LCD_BYTE_MODE_M ((LCD_CAM_LCD_BYTE_MODE_V)<<(LCD_CAM_LCD_BYTE_MODE_S))
#define LCD_CAM_LCD_BYTE_MODE_V 0x3
#define LCD_CAM_LCD_BYTE_MODE_S 19
/* LCD_CAM_LCD_DOUT_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
/*description: 1: change bit order in every byte. 0: Not change..*/
#define LCD_CAM_LCD_DOUT_BIT_ORDER (BIT(18))
#define LCD_CAM_LCD_DOUT_BIT_ORDER_M (BIT(18))
#define LCD_CAM_LCD_DOUT_BIT_ORDER_V 0x1
#define LCD_CAM_LCD_DOUT_BIT_ORDER_S 18
/* LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE : R/W ;bitpos:[17] ;default: 1'h0 ; */
/*description: 1: enable byte swizzle 0: disable.*/
#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE (BIT(17))
#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_M (BIT(17))
#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_V 0x1
#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_ENABLE_S 17
/* LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE : R/W ;bitpos:[16:14] ;default: 3'h0 ; */
/*description: 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA.*/
#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE 0x00000007
#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_M ((LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V)<<(LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S))
#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_V 0x7
#define LCD_CAM_LCD_DOUT_BYTE_SWIZZLE_MODE_S 14
/* LCD_CAM_LCD_ALWAYS_OUT_EN : R/W ;bitpos:[13] ;default: 1'h0 ; */
/*description: LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared
or reg_lcd_reset is set..*/
#define LCD_CAM_LCD_ALWAYS_OUT_EN (BIT(13))
#define LCD_CAM_LCD_ALWAYS_OUT_EN_M (BIT(13))
#define LCD_CAM_LCD_ALWAYS_OUT_EN_V 0x1
#define LCD_CAM_LCD_ALWAYS_OUT_EN_S 13
/* LCD_CAM_LCD_DOUT_CYCLELEN : R/W ;bitpos:[12:0] ;default: 13'h1 ; */
/*description: The output data cycles minus 1 of LCD module..*/
#define LCD_CAM_LCD_DOUT_CYCLELEN 0x00001FFF
#define LCD_CAM_LCD_DOUT_CYCLELEN_M ((LCD_CAM_LCD_DOUT_CYCLELEN_V)<<(LCD_CAM_LCD_DOUT_CYCLELEN_S))
#define LCD_CAM_LCD_DOUT_CYCLELEN_V 0x1FFF
#define LCD_CAM_LCD_DOUT_CYCLELEN_S 0
#define LCD_CAM_LCD_MISC_REG (DR_REG_LCD_CAM_BASE + 0x18)
/* LCD_CAM_LCD_CD_IDLE_EDGE : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: The default value of LCD_CD..*/
#define LCD_CAM_LCD_CD_IDLE_EDGE (BIT(31))
#define LCD_CAM_LCD_CD_IDLE_EDGE_M (BIT(31))
#define LCD_CAM_LCD_CD_IDLE_EDGE_V 0x1
#define LCD_CAM_LCD_CD_IDLE_EDGE_S 31
/* LCD_CAM_LCD_CD_CMD_SET : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD =
reg_cd_idle_edge..*/
#define LCD_CAM_LCD_CD_CMD_SET (BIT(30))
#define LCD_CAM_LCD_CD_CMD_SET_M (BIT(30))
#define LCD_CAM_LCD_CD_CMD_SET_V 0x1
#define LCD_CAM_LCD_CD_CMD_SET_S 30
/* LCD_CAM_LCD_CD_DUMMY_SET : R/W ;bitpos:[29] ;default: 1'h0 ; */
/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD
= reg_cd_idle_edge..*/
#define LCD_CAM_LCD_CD_DUMMY_SET (BIT(29))
#define LCD_CAM_LCD_CD_DUMMY_SET_M (BIT(29))
#define LCD_CAM_LCD_CD_DUMMY_SET_V 0x1
#define LCD_CAM_LCD_CD_DUMMY_SET_S 29
/* LCD_CAM_LCD_CD_DATA_SET : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD
= reg_cd_idle_edge..*/
#define LCD_CAM_LCD_CD_DATA_SET (BIT(28))
#define LCD_CAM_LCD_CD_DATA_SET_M (BIT(28))
#define LCD_CAM_LCD_CD_DATA_SET_V 0x1
#define LCD_CAM_LCD_CD_DATA_SET_S 28
/* LCD_CAM_LCD_AFIFO_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
/*description: LCD AFIFO reset signal..*/
#define LCD_CAM_LCD_AFIFO_RESET (BIT(27))
#define LCD_CAM_LCD_AFIFO_RESET_M (BIT(27))
#define LCD_CAM_LCD_AFIFO_RESET_V 0x1
#define LCD_CAM_LCD_AFIFO_RESET_S 27
/* LCD_CAM_LCD_BK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: Enable blank region when LCD sends data out. 0: No blank region..*/
#define LCD_CAM_LCD_BK_EN (BIT(26))
#define LCD_CAM_LCD_BK_EN_M (BIT(26))
#define LCD_CAM_LCD_BK_EN_V 0x1
#define LCD_CAM_LCD_BK_EN_S 26
/* LCD_CAM_LCD_NEXT_FRAME_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: Send the next frame data when the current frame is sent out. 0: LCD stops whe
n the current frame is sent out..*/
#define LCD_CAM_LCD_NEXT_FRAME_EN (BIT(25))
#define LCD_CAM_LCD_NEXT_FRAME_EN_M (BIT(25))
#define LCD_CAM_LCD_NEXT_FRAME_EN_V 0x1
#define LCD_CAM_LCD_NEXT_FRAME_EN_S 25
/* LCD_CAM_LCD_VBK_CYCLELEN : R/W ;bitpos:[24:12] ;default: 13'h0 ; */
/*description: The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
time cycle length in LCD non-RGB mode..*/
#define LCD_CAM_LCD_VBK_CYCLELEN 0x00001FFF
#define LCD_CAM_LCD_VBK_CYCLELEN_M ((LCD_CAM_LCD_VBK_CYCLELEN_V)<<(LCD_CAM_LCD_VBK_CYCLELEN_S))
#define LCD_CAM_LCD_VBK_CYCLELEN_V 0x1FFF
#define LCD_CAM_LCD_VBK_CYCLELEN_S 12
/* LCD_CAM_LCD_VFK_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'h3 ; */
/*description: The setup cycle length minus 1 in LCD non-RGB mode..*/
#define LCD_CAM_LCD_VFK_CYCLELEN 0x0000003F
#define LCD_CAM_LCD_VFK_CYCLELEN_M ((LCD_CAM_LCD_VFK_CYCLELEN_V)<<(LCD_CAM_LCD_VFK_CYCLELEN_S))
#define LCD_CAM_LCD_VFK_CYCLELEN_V 0x3F
#define LCD_CAM_LCD_VFK_CYCLELEN_S 6
/* LCD_CAM_LCD_WIRE_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
/*description: The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit.*/
#define LCD_CAM_LCD_WIRE_MODE 0x00000003
#define LCD_CAM_LCD_WIRE_MODE_M ((LCD_CAM_LCD_WIRE_MODE_V)<<(LCD_CAM_LCD_WIRE_MODE_S))
#define LCD_CAM_LCD_WIRE_MODE_V 0x3
#define LCD_CAM_LCD_WIRE_MODE_S 4
#define LCD_CAM_LCD_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x1C)
/* LCD_CAM_LCD_RGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: 1: Enable LCD RGB mode. 0: Disable LCD RGB mode..*/
#define LCD_CAM_LCD_RGB_MODE_EN (BIT(31))
#define LCD_CAM_LCD_RGB_MODE_EN_M (BIT(31))
#define LCD_CAM_LCD_RGB_MODE_EN_V 0x1
#define LCD_CAM_LCD_RGB_MODE_EN_S 31
/* LCD_CAM_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */
/*description: It is the vertical total height of a frame..*/
#define LCD_CAM_LCD_VT_HEIGHT 0x000003FF
#define LCD_CAM_LCD_VT_HEIGHT_M ((LCD_CAM_LCD_VT_HEIGHT_V)<<(LCD_CAM_LCD_VT_HEIGHT_S))
#define LCD_CAM_LCD_VT_HEIGHT_V 0x3FF
#define LCD_CAM_LCD_VT_HEIGHT_S 21
/* LCD_CAM_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */
/*description: It is the vertical active height of a frame..*/
#define LCD_CAM_LCD_VA_HEIGHT 0x000003FF
#define LCD_CAM_LCD_VA_HEIGHT_M ((LCD_CAM_LCD_VA_HEIGHT_V)<<(LCD_CAM_LCD_VA_HEIGHT_S))
#define LCD_CAM_LCD_VA_HEIGHT_V 0x3FF
#define LCD_CAM_LCD_VA_HEIGHT_S 11
/* LCD_CAM_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */
/*description: It is the horizontal blank front porch of a frame..*/
#define LCD_CAM_LCD_HB_FRONT 0x000007FF
#define LCD_CAM_LCD_HB_FRONT_M ((LCD_CAM_LCD_HB_FRONT_V)<<(LCD_CAM_LCD_HB_FRONT_S))
#define LCD_CAM_LCD_HB_FRONT_V 0x7FF
#define LCD_CAM_LCD_HB_FRONT_S 0
#define LCD_CAM_LCD_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x20)
/* LCD_CAM_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */
/*description: It is the horizontal total width of a frame..*/
#define LCD_CAM_LCD_HT_WIDTH 0x00000FFF
#define LCD_CAM_LCD_HT_WIDTH_M ((LCD_CAM_LCD_HT_WIDTH_V)<<(LCD_CAM_LCD_HT_WIDTH_S))
#define LCD_CAM_LCD_HT_WIDTH_V 0xFFF
#define LCD_CAM_LCD_HT_WIDTH_S 20
/* LCD_CAM_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */
/*description: It is the horizontal active width of a frame..*/
#define LCD_CAM_LCD_HA_WIDTH 0x00000FFF
#define LCD_CAM_LCD_HA_WIDTH_M ((LCD_CAM_LCD_HA_WIDTH_V)<<(LCD_CAM_LCD_HA_WIDTH_S))
#define LCD_CAM_LCD_HA_WIDTH_V 0xFFF
#define LCD_CAM_LCD_HA_WIDTH_S 8
/* LCD_CAM_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
/*description: It is the vertical blank front porch of a frame..*/
#define LCD_CAM_LCD_VB_FRONT 0x000000FF
#define LCD_CAM_LCD_VB_FRONT_M ((LCD_CAM_LCD_VB_FRONT_V)<<(LCD_CAM_LCD_VB_FRONT_S))
#define LCD_CAM_LCD_VB_FRONT_V 0xFF
#define LCD_CAM_LCD_VB_FRONT_S 0
#define LCD_CAM_LCD_CTRL2_REG (DR_REG_LCD_CAM_BASE + 0x24)
/* LCD_CAM_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
/*description: It is the position of LCD_HSYNC active pulse in a line..*/
#define LCD_CAM_LCD_HSYNC_POSITION 0x000000FF
#define LCD_CAM_LCD_HSYNC_POSITION_M ((LCD_CAM_LCD_HSYNC_POSITION_V)<<(LCD_CAM_LCD_HSYNC_POSITION_S))
#define LCD_CAM_LCD_HSYNC_POSITION_V 0xFF
#define LCD_CAM_LCD_HSYNC_POSITION_S 24
/* LCD_CAM_LCD_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: It is the idle value of LCD_HSYNC..*/
#define LCD_CAM_LCD_HSYNC_IDLE_POL (BIT(23))
#define LCD_CAM_LCD_HSYNC_IDLE_POL_M (BIT(23))
#define LCD_CAM_LCD_HSYNC_IDLE_POL_V 0x1
#define LCD_CAM_LCD_HSYNC_IDLE_POL_S 23
/* LCD_CAM_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */
/*description: It is the position of LCD_HSYNC active pulse in a line..*/
#define LCD_CAM_LCD_HSYNC_WIDTH 0x0000007F
#define LCD_CAM_LCD_HSYNC_WIDTH_M ((LCD_CAM_LCD_HSYNC_WIDTH_V)<<(LCD_CAM_LCD_HSYNC_WIDTH_S))
#define LCD_CAM_LCD_HSYNC_WIDTH_V 0x7F
#define LCD_CAM_LCD_HSYNC_WIDTH_S 16
/* LCD_CAM_LCD_HS_BLANK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSY
NC pulse is valid only in active region lines in RGB mode..*/
#define LCD_CAM_LCD_HS_BLANK_EN (BIT(9))
#define LCD_CAM_LCD_HS_BLANK_EN_M (BIT(9))
#define LCD_CAM_LCD_HS_BLANK_EN_V 0x1
#define LCD_CAM_LCD_HS_BLANK_EN_S 9
/* LCD_CAM_LCD_DE_IDLE_POL : R/W ;bitpos:[8] ;default: 1'h0 ; */
/*description: It is the idle value of LCD_DE..*/
#define LCD_CAM_LCD_DE_IDLE_POL (BIT(8))
#define LCD_CAM_LCD_DE_IDLE_POL_M (BIT(8))
#define LCD_CAM_LCD_DE_IDLE_POL_V 0x1
#define LCD_CAM_LCD_DE_IDLE_POL_S 8
/* LCD_CAM_LCD_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */
/*description: It is the idle value of LCD_VSYNC..*/
#define LCD_CAM_LCD_VSYNC_IDLE_POL (BIT(7))
#define LCD_CAM_LCD_VSYNC_IDLE_POL_M (BIT(7))
#define LCD_CAM_LCD_VSYNC_IDLE_POL_V 0x1
#define LCD_CAM_LCD_VSYNC_IDLE_POL_S 7
/* LCD_CAM_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
/*description: It is the position of LCD_VSYNC active pulse in a line..*/
#define LCD_CAM_LCD_VSYNC_WIDTH 0x0000007F
#define LCD_CAM_LCD_VSYNC_WIDTH_M ((LCD_CAM_LCD_VSYNC_WIDTH_V)<<(LCD_CAM_LCD_VSYNC_WIDTH_S))
#define LCD_CAM_LCD_VSYNC_WIDTH_V 0x7F
#define LCD_CAM_LCD_VSYNC_WIDTH_S 0
#define LCD_CAM_LCD_FIRST_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x28)
/* LCD_CAM_LCD_FIRST_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The LCD write command value of first cmd cycle..*/
#define LCD_CAM_LCD_FIRST_CMD_VALUE 0xFFFFFFFF
#define LCD_CAM_LCD_FIRST_CMD_VALUE_M ((LCD_CAM_LCD_FIRST_CMD_VALUE_V)<<(LCD_CAM_LCD_FIRST_CMD_VALUE_S))
#define LCD_CAM_LCD_FIRST_CMD_VALUE_V 0xFFFFFFFF
#define LCD_CAM_LCD_FIRST_CMD_VALUE_S 0
#define LCD_CAM_LCD_LATTER_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x2C)
/* LCD_CAM_LCD_LATTER_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: The LCD write command value of latter cmd cycle..*/
#define LCD_CAM_LCD_LATTER_CMD_VALUE 0xFFFFFFFF
#define LCD_CAM_LCD_LATTER_CMD_VALUE_M ((LCD_CAM_LCD_LATTER_CMD_VALUE_V)<<(LCD_CAM_LCD_LATTER_CMD_VALUE_S))
#define LCD_CAM_LCD_LATTER_CMD_VALUE_V 0xFFFFFFFF
#define LCD_CAM_LCD_LATTER_CMD_VALUE_S 0
#define LCD_CAM_LCD_DLY_MODE_CFG1_REG (DR_REG_LCD_CAM_BASE + 0x30)
/* LCD_CAM_LCD_VSYNC_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */
/*description: The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay
ed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of L
CD_CLK..*/
#define LCD_CAM_LCD_VSYNC_MODE 0x00000003
#define LCD_CAM_LCD_VSYNC_MODE_M ((LCD_CAM_LCD_VSYNC_MODE_V)<<(LCD_CAM_LCD_VSYNC_MODE_S))
#define LCD_CAM_LCD_VSYNC_MODE_V 0x3
#define LCD_CAM_LCD_VSYNC_MODE_S 22
/* LCD_CAM_LCD_HSYNC_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
/*description: The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay
ed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of L
CD_CLK..*/
#define LCD_CAM_LCD_HSYNC_MODE 0x00000003
#define LCD_CAM_LCD_HSYNC_MODE_M ((LCD_CAM_LCD_HSYNC_MODE_V)<<(LCD_CAM_LCD_HSYNC_MODE_S))
#define LCD_CAM_LCD_HSYNC_MODE_V 0x3
#define LCD_CAM_LCD_HSYNC_MODE_S 20
/* LCD_CAM_LCD_DE_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */
/*description: The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed.
1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_
CLK..*/
#define LCD_CAM_LCD_DE_MODE 0x00000003
#define LCD_CAM_LCD_DE_MODE_M ((LCD_CAM_LCD_DE_MODE_V)<<(LCD_CAM_LCD_DE_MODE_S))
#define LCD_CAM_LCD_DE_MODE_V 0x3
#define LCD_CAM_LCD_DE_MODE_S 18
/* LCD_CAM_LCD_CD_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
/*description: The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed.
1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_
CLK..*/
#define LCD_CAM_LCD_CD_MODE 0x00000003
#define LCD_CAM_LCD_CD_MODE_M ((LCD_CAM_LCD_CD_MODE_V)<<(LCD_CAM_LCD_CD_MODE_S))
#define LCD_CAM_LCD_CD_MODE_V 0x3
#define LCD_CAM_LCD_CD_MODE_S 16
/* LCD_CAM_DOUT23_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT23_MODE 0x00000003
#define LCD_CAM_DOUT23_MODE_M ((LCD_CAM_DOUT23_MODE_V)<<(LCD_CAM_DOUT23_MODE_S))
#define LCD_CAM_DOUT23_MODE_V 0x3
#define LCD_CAM_DOUT23_MODE_S 14
/* LCD_CAM_DOUT22_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT22_MODE 0x00000003
#define LCD_CAM_DOUT22_MODE_M ((LCD_CAM_DOUT22_MODE_V)<<(LCD_CAM_DOUT22_MODE_S))
#define LCD_CAM_DOUT22_MODE_V 0x3
#define LCD_CAM_DOUT22_MODE_S 12
/* LCD_CAM_DOUT21_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT21_MODE 0x00000003
#define LCD_CAM_DOUT21_MODE_M ((LCD_CAM_DOUT21_MODE_V)<<(LCD_CAM_DOUT21_MODE_S))
#define LCD_CAM_DOUT21_MODE_V 0x3
#define LCD_CAM_DOUT21_MODE_S 10
/* LCD_CAM_DOUT20_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT20_MODE 0x00000003
#define LCD_CAM_DOUT20_MODE_M ((LCD_CAM_DOUT20_MODE_V)<<(LCD_CAM_DOUT20_MODE_S))
#define LCD_CAM_DOUT20_MODE_V 0x3
#define LCD_CAM_DOUT20_MODE_S 8
/* LCD_CAM_DOUT19_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT19_MODE 0x00000003
#define LCD_CAM_DOUT19_MODE_M ((LCD_CAM_DOUT19_MODE_V)<<(LCD_CAM_DOUT19_MODE_S))
#define LCD_CAM_DOUT19_MODE_V 0x3
#define LCD_CAM_DOUT19_MODE_S 6
/* LCD_CAM_DOUT18_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT18_MODE 0x00000003
#define LCD_CAM_DOUT18_MODE_M ((LCD_CAM_DOUT18_MODE_V)<<(LCD_CAM_DOUT18_MODE_S))
#define LCD_CAM_DOUT18_MODE_V 0x3
#define LCD_CAM_DOUT18_MODE_S 4
/* LCD_CAM_DOUT17_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT17_MODE 0x00000003
#define LCD_CAM_DOUT17_MODE_M ((LCD_CAM_DOUT17_MODE_V)<<(LCD_CAM_DOUT17_MODE_S))
#define LCD_CAM_DOUT17_MODE_V 0x3
#define LCD_CAM_DOUT17_MODE_S 2
/* LCD_CAM_DOUT16_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT16_MODE 0x00000003
#define LCD_CAM_DOUT16_MODE_M ((LCD_CAM_DOUT16_MODE_V)<<(LCD_CAM_DOUT16_MODE_S))
#define LCD_CAM_DOUT16_MODE_V 0x3
#define LCD_CAM_DOUT16_MODE_S 0
#define LCD_CAM_LCD_DLY_MODE_CFG2_REG (DR_REG_LCD_CAM_BASE + 0x38)
/* LCD_CAM_DOUT15_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT15_MODE 0x00000003
#define LCD_CAM_DOUT15_MODE_M ((LCD_CAM_DOUT15_MODE_V)<<(LCD_CAM_DOUT15_MODE_S))
#define LCD_CAM_DOUT15_MODE_V 0x3
#define LCD_CAM_DOUT15_MODE_S 30
/* LCD_CAM_DOUT14_MODE : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT14_MODE 0x00000003
#define LCD_CAM_DOUT14_MODE_M ((LCD_CAM_DOUT14_MODE_V)<<(LCD_CAM_DOUT14_MODE_S))
#define LCD_CAM_DOUT14_MODE_V 0x3
#define LCD_CAM_DOUT14_MODE_S 28
/* LCD_CAM_DOUT13_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT13_MODE 0x00000003
#define LCD_CAM_DOUT13_MODE_M ((LCD_CAM_DOUT13_MODE_V)<<(LCD_CAM_DOUT13_MODE_S))
#define LCD_CAM_DOUT13_MODE_V 0x3
#define LCD_CAM_DOUT13_MODE_S 26
/* LCD_CAM_DOUT12_MODE : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT12_MODE 0x00000003
#define LCD_CAM_DOUT12_MODE_M ((LCD_CAM_DOUT12_MODE_V)<<(LCD_CAM_DOUT12_MODE_S))
#define LCD_CAM_DOUT12_MODE_V 0x3
#define LCD_CAM_DOUT12_MODE_S 24
/* LCD_CAM_DOUT11_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT11_MODE 0x00000003
#define LCD_CAM_DOUT11_MODE_M ((LCD_CAM_DOUT11_MODE_V)<<(LCD_CAM_DOUT11_MODE_S))
#define LCD_CAM_DOUT11_MODE_V 0x3
#define LCD_CAM_DOUT11_MODE_S 22
/* LCD_CAM_DOUT10_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT10_MODE 0x00000003
#define LCD_CAM_DOUT10_MODE_M ((LCD_CAM_DOUT10_MODE_V)<<(LCD_CAM_DOUT10_MODE_S))
#define LCD_CAM_DOUT10_MODE_V 0x3
#define LCD_CAM_DOUT10_MODE_S 20
/* LCD_CAM_DOUT9_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT9_MODE 0x00000003
#define LCD_CAM_DOUT9_MODE_M ((LCD_CAM_DOUT9_MODE_V)<<(LCD_CAM_DOUT9_MODE_S))
#define LCD_CAM_DOUT9_MODE_V 0x3
#define LCD_CAM_DOUT9_MODE_S 18
/* LCD_CAM_DOUT8_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT8_MODE 0x00000003
#define LCD_CAM_DOUT8_MODE_M ((LCD_CAM_DOUT8_MODE_V)<<(LCD_CAM_DOUT8_MODE_S))
#define LCD_CAM_DOUT8_MODE_V 0x3
#define LCD_CAM_DOUT8_MODE_S 16
/* LCD_CAM_DOUT7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT7_MODE 0x00000003
#define LCD_CAM_DOUT7_MODE_M ((LCD_CAM_DOUT7_MODE_V)<<(LCD_CAM_DOUT7_MODE_S))
#define LCD_CAM_DOUT7_MODE_V 0x3
#define LCD_CAM_DOUT7_MODE_S 14
/* LCD_CAM_DOUT6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT6_MODE 0x00000003
#define LCD_CAM_DOUT6_MODE_M ((LCD_CAM_DOUT6_MODE_V)<<(LCD_CAM_DOUT6_MODE_S))
#define LCD_CAM_DOUT6_MODE_V 0x3
#define LCD_CAM_DOUT6_MODE_S 12
/* LCD_CAM_DOUT5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT5_MODE 0x00000003
#define LCD_CAM_DOUT5_MODE_M ((LCD_CAM_DOUT5_MODE_V)<<(LCD_CAM_DOUT5_MODE_S))
#define LCD_CAM_DOUT5_MODE_V 0x3
#define LCD_CAM_DOUT5_MODE_S 10
/* LCD_CAM_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT4_MODE 0x00000003
#define LCD_CAM_DOUT4_MODE_M ((LCD_CAM_DOUT4_MODE_V)<<(LCD_CAM_DOUT4_MODE_S))
#define LCD_CAM_DOUT4_MODE_V 0x3
#define LCD_CAM_DOUT4_MODE_S 8
/* LCD_CAM_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT3_MODE 0x00000003
#define LCD_CAM_DOUT3_MODE_M ((LCD_CAM_DOUT3_MODE_V)<<(LCD_CAM_DOUT3_MODE_S))
#define LCD_CAM_DOUT3_MODE_V 0x3
#define LCD_CAM_DOUT3_MODE_S 6
/* LCD_CAM_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT2_MODE 0x00000003
#define LCD_CAM_DOUT2_MODE_M ((LCD_CAM_DOUT2_MODE_V)<<(LCD_CAM_DOUT2_MODE_S))
#define LCD_CAM_DOUT2_MODE_V 0x3
#define LCD_CAM_DOUT2_MODE_S 4
/* LCD_CAM_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT1_MODE 0x00000003
#define LCD_CAM_DOUT1_MODE_M ((LCD_CAM_DOUT1_MODE_V)<<(LCD_CAM_DOUT1_MODE_S))
#define LCD_CAM_DOUT1_MODE_V 0x3
#define LCD_CAM_DOUT1_MODE_S 2
/* LCD_CAM_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: The output data bit $n is delayed by module clock LCD_CLK. 0: output without del
ayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
LCD_CLK..*/
#define LCD_CAM_DOUT0_MODE 0x00000003
#define LCD_CAM_DOUT0_MODE_M ((LCD_CAM_DOUT0_MODE_V)<<(LCD_CAM_DOUT0_MODE_S))
#define LCD_CAM_DOUT0_MODE_V 0x3
#define LCD_CAM_DOUT0_MODE_S 0
#define LCD_CAM_LC_DMA_INT_ENA_REG (DR_REG_LCD_CAM_BASE + 0x64)
/* LCD_CAM_CAM_HS_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The enable bit for Camera line interrupt..*/
#define LCD_CAM_CAM_HS_INT_ENA (BIT(3))
#define LCD_CAM_CAM_HS_INT_ENA_M (BIT(3))
#define LCD_CAM_CAM_HS_INT_ENA_V 0x1
#define LCD_CAM_CAM_HS_INT_ENA_S 3
/* LCD_CAM_CAM_VSYNC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The enable bit for Camera frame end interrupt..*/
#define LCD_CAM_CAM_VSYNC_INT_ENA (BIT(2))
#define LCD_CAM_CAM_VSYNC_INT_ENA_M (BIT(2))
#define LCD_CAM_CAM_VSYNC_INT_ENA_V 0x1
#define LCD_CAM_CAM_VSYNC_INT_ENA_S 2
/* LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The enable bit for lcd transfer end interrupt..*/
#define LCD_CAM_LCD_TRANS_DONE_INT_ENA (BIT(1))
#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M (BIT(1))
#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V 0x1
#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S 1
/* LCD_CAM_LCD_VSYNC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The enable bit for LCD frame end interrupt..*/
#define LCD_CAM_LCD_VSYNC_INT_ENA (BIT(0))
#define LCD_CAM_LCD_VSYNC_INT_ENA_M (BIT(0))
#define LCD_CAM_LCD_VSYNC_INT_ENA_V 0x1
#define LCD_CAM_LCD_VSYNC_INT_ENA_S 0
#define LCD_CAM_LC_DMA_INT_RAW_REG (DR_REG_LCD_CAM_BASE + 0x68)
/* LCD_CAM_CAM_HS_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw bit for Camera line interrupt..*/
#define LCD_CAM_CAM_HS_INT_RAW (BIT(3))
#define LCD_CAM_CAM_HS_INT_RAW_M (BIT(3))
#define LCD_CAM_CAM_HS_INT_RAW_V 0x1
#define LCD_CAM_CAM_HS_INT_RAW_S 3
/* LCD_CAM_CAM_VSYNC_INT_RAW : RO/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
/*description: The raw bit for Camera frame end interrupt..*/
#define LCD_CAM_CAM_VSYNC_INT_RAW (BIT(2))
#define LCD_CAM_CAM_VSYNC_INT_RAW_M (BIT(2))
#define LCD_CAM_CAM_VSYNC_INT_RAW_V 0x1
#define LCD_CAM_CAM_VSYNC_INT_RAW_S 2
/* LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw bit for lcd transfer end interrupt..*/
#define LCD_CAM_LCD_TRANS_DONE_INT_RAW (BIT(1))
#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M (BIT(1))
#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V 0x1
#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S 1
/* LCD_CAM_LCD_VSYNC_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw bit for LCD frame end interrupt..*/
#define LCD_CAM_LCD_VSYNC_INT_RAW (BIT(0))
#define LCD_CAM_LCD_VSYNC_INT_RAW_M (BIT(0))
#define LCD_CAM_LCD_VSYNC_INT_RAW_V 0x1
#define LCD_CAM_LCD_VSYNC_INT_RAW_S 0
#define LCD_CAM_LC_DMA_INT_ST_REG (DR_REG_LCD_CAM_BASE + 0x6C)
/* LCD_CAM_CAM_HS_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The status bit for Camera transfer end interrupt..*/
#define LCD_CAM_CAM_HS_INT_ST (BIT(3))
#define LCD_CAM_CAM_HS_INT_ST_M (BIT(3))
#define LCD_CAM_CAM_HS_INT_ST_V 0x1
#define LCD_CAM_CAM_HS_INT_ST_S 3
/* LCD_CAM_CAM_VSYNC_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The status bit for Camera frame end interrupt..*/
#define LCD_CAM_CAM_VSYNC_INT_ST (BIT(2))
#define LCD_CAM_CAM_VSYNC_INT_ST_M (BIT(2))
#define LCD_CAM_CAM_VSYNC_INT_ST_V 0x1
#define LCD_CAM_CAM_VSYNC_INT_ST_S 2
/* LCD_CAM_LCD_TRANS_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The status bit for lcd transfer end interrupt..*/
#define LCD_CAM_LCD_TRANS_DONE_INT_ST (BIT(1))
#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M (BIT(1))
#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V 0x1
#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S 1
/* LCD_CAM_LCD_VSYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The status bit for LCD frame end interrupt..*/
#define LCD_CAM_LCD_VSYNC_INT_ST (BIT(0))
#define LCD_CAM_LCD_VSYNC_INT_ST_M (BIT(0))
#define LCD_CAM_LCD_VSYNC_INT_ST_V 0x1
#define LCD_CAM_LCD_VSYNC_INT_ST_S 0
#define LCD_CAM_LC_DMA_INT_CLR_REG (DR_REG_LCD_CAM_BASE + 0x70)
/* LCD_CAM_CAM_HS_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: The clear bit for Camera line interrupt..*/
#define LCD_CAM_CAM_HS_INT_CLR (BIT(3))
#define LCD_CAM_CAM_HS_INT_CLR_M (BIT(3))
#define LCD_CAM_CAM_HS_INT_CLR_V 0x1
#define LCD_CAM_CAM_HS_INT_CLR_S 3
/* LCD_CAM_CAM_VSYNC_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: The clear bit for Camera frame end interrupt..*/
#define LCD_CAM_CAM_VSYNC_INT_CLR (BIT(2))
#define LCD_CAM_CAM_VSYNC_INT_CLR_M (BIT(2))
#define LCD_CAM_CAM_VSYNC_INT_CLR_V 0x1
#define LCD_CAM_CAM_VSYNC_INT_CLR_S 2
/* LCD_CAM_LCD_TRANS_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: The clear bit for lcd transfer end interrupt..*/
#define LCD_CAM_LCD_TRANS_DONE_INT_CLR (BIT(1))
#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M (BIT(1))
#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V 0x1
#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S 1
/* LCD_CAM_LCD_VSYNC_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: The clear bit for LCD frame end interrupt..*/
#define LCD_CAM_LCD_VSYNC_INT_CLR (BIT(0))
#define LCD_CAM_LCD_VSYNC_INT_CLR_M (BIT(0))
#define LCD_CAM_LCD_VSYNC_INT_CLR_V 0x1
#define LCD_CAM_LCD_VSYNC_INT_CLR_S 0
#define LCD_CAM_LC_REG_DATE_REG (DR_REG_LCD_CAM_BASE + 0xFC)
/* LCD_CAM_LC_DATE : R/W ;bitpos:[27:0] ;default: 28'h2303090 ; */
/*description: LCD_CAM version control register.*/
#define LCD_CAM_LC_DATE 0x0FFFFFFF
#define LCD_CAM_LC_DATE_M ((LCD_CAM_LC_DATE_V)<<(LCD_CAM_LC_DATE_S))
#define LCD_CAM_LC_DATE_V 0xFFFFFFF
#define LCD_CAM_LC_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_LCD_CAM_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_LCD_CAM_STRUCT_H_
#define _SOC_LCD_CAM_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
union {
struct {
uint32_t lcd_clkcnt_n : 6; /*f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/
uint32_t lcd_clk_equ_sysclk : 1; /*1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/
uint32_t lcd_ck_idle_edge : 1; /*1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. */
uint32_t lcd_ck_out_edge : 1; /*1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle. */
uint32_t lcd_clkm_div_num : 8; /*Integral LCD clock divider value*/
uint32_t lcd_clkm_div_b : 6; /*Fractional clock divider numerator value*/
uint32_t lcd_clkm_div_a : 6; /*Fractional clock divider denominator value*/
uint32_t lcd_clk_sel : 2; /*Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
uint32_t clk_en : 1; /*Set this bit to enable clk gate*/
};
uint32_t val;
} lcd_clock;
union {
struct {
uint32_t cam_stop_en : 1; /*Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.*/
uint32_t cam_vsync_filter_thres : 3; /*Filter threshold value for CAM_VSYNC signal.*/
uint32_t cam_update : 1; /*1: Update Camera registers, will be cleared by hardware. 0 : Not care.*/
uint32_t cam_byte_order : 1; /*1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/
uint32_t cam_bit_order : 1; /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
uint32_t cam_line_int_en : 1; /*1: Enable to generate CAM_HS_INT. 0: Disable.*/
uint32_t cam_vs_eof_en : 1; /*1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.*/
uint32_t cam_clkm_div_num : 8; /*Integral Camera clock divider value*/
uint32_t cam_clkm_div_b : 6; /*Fractional clock divider numerator value*/
uint32_t cam_clkm_div_a : 6; /*Fractional clock divider denominator value*/
uint32_t cam_clk_sel : 2; /*Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} cam_ctrl;
union {
struct {
uint32_t cam_rec_data_bytelen : 16; /*Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/
uint32_t cam_line_int_num : 6; /*The line number minus 1 to generate cam_hs_int.*/
uint32_t cam_clk_inv : 1; /*1: Invert the input signal CAM_PCLK. 0: Not invert.*/
uint32_t cam_vsync_filter_en : 1; /*1: Enable CAM_VSYNC filter function. 0: bypass.*/
uint32_t cam_2byte_en : 1; /*1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. */
uint32_t cam_de_inv : 1; /*CAM_DE invert enable signal, valid in high level.*/
uint32_t cam_hsync_inv : 1; /*CAM_HSYNC invert enable signal, valid in high level.*/
uint32_t cam_vsync_inv : 1; /*CAM_VSYNC invert enable signal, valid in high level.*/
uint32_t cam_vh_de_mode_en : 1; /*1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC.*/
uint32_t cam_start : 1; /*Camera module start signal.*/
uint32_t cam_reset : 1; /*Camera module reset signal.*/
uint32_t cam_afifo_reset : 1; /*Camera AFIFO reset signal.*/
};
uint32_t val;
} cam_ctrl1;
union {
struct {
uint32_t reserved0 : 21; /*reserved*/
uint32_t cam_conv_8bits_data_inv : 1; /*1:invert every two 8bits input data. 2. disabled.*/
uint32_t cam_conv_yuv2yuv_mode : 2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. */
uint32_t cam_conv_yuv_mode : 2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
uint32_t cam_conv_protocol_mode : 1; /*0:BT601. 1:BT709.*/
uint32_t cam_conv_data_out_mode : 1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
uint32_t cam_conv_data_in_mode : 1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
uint32_t cam_conv_mode_8bits_on : 1; /*0: 16bits mode. 1: 8bits mode.*/
uint32_t cam_conv_trans_mode : 1; /*0: YUV to RGB. 1: RGB to YUV.*/
uint32_t cam_conv_enable : 1; /*0: Bypass converter. 1: Enable converter.*/
};
uint32_t val;
} cam_rgb_yuv;
union {
struct {
uint32_t reserved0 : 20; /*reserved*/
uint32_t lcd_conv_8bits_data_inv : 1; /*1:invert every two 8bits input data. 2. disabled.*/
uint32_t lcd_conv_txtorx : 1; /*0: txtorx mode off. 1: txtorx mode on.*/
uint32_t lcd_conv_yuv2yuv_mode : 2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. */
uint32_t lcd_conv_yuv_mode : 2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in*/
uint32_t lcd_conv_protocol_mode : 1; /*0:BT601. 1:BT709.*/
uint32_t lcd_conv_data_out_mode : 1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
uint32_t lcd_conv_data_in_mode : 1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
uint32_t lcd_conv_mode_8bits_on : 1; /*0: 16bits mode. 1: 8bits mode.*/
uint32_t lcd_conv_trans_mode : 1; /*0: YUV to RGB. 1: RGB to YUV.*/
uint32_t lcd_conv_enable : 1; /*0: Bypass converter. 1: Enable converter.*/
};
uint32_t val;
} lcd_rgb_yuv;
union {
struct {
uint32_t lcd_dout_cyclelen : 13; /*The output data cycles minus 1 of LCD module.*/
uint32_t lcd_always_out_en : 1; /*LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set.*/
uint32_t lcd_dout_byte_swizzle_mode : 3; /*0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA*/
uint32_t lcd_dout_byte_swizzle_enable : 1; /*1: enable byte swizzle 0: disable*/
uint32_t lcd_dout_bit_order : 1; /*1: change bit order in every byte. 0: Not change.*/
uint32_t lcd_byte_mode : 2; /*2: 24bit mode. 1: 16bit mode. 0: 8bit mode*/
uint32_t lcd_update : 1; /*1: Update LCD registers, will be cleared by hardware. 0 : Not care.*/
uint32_t lcd_bit_order : 1; /*1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/
uint32_t lcd_byte_order : 1; /*1: invert data byte order, only valid in 2 byte mode. 0: Not change.*/
uint32_t lcd_dout : 1; /*1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/
uint32_t lcd_dummy : 1; /*1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/
uint32_t lcd_cmd : 1; /*1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/
uint32_t lcd_start : 1; /*LCD start sending data enable signal, valid in high level.*/
uint32_t lcd_reset : 1; /*The value of command. */
uint32_t lcd_dummy_cyclelen : 2; /*The dummy cycle length minus 1.*/
uint32_t lcd_cmd_2_cycle_en : 1; /*The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. */
};
uint32_t val;
} lcd_user;
union {
struct {
uint32_t reserved0 : 4; /*reserved*/
uint32_t lcd_wire_mode : 2; /*The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit*/
uint32_t lcd_vfk_cyclelen : 6; /*The setup cycle length minus 1 in LCD non-RGB mode.*/
uint32_t lcd_vbk_cyclelen : 13; /*The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode.*/
uint32_t lcd_next_frame_en : 1; /*1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.*/
uint32_t lcd_bk_en : 1; /*1: Enable blank region when LCD sends data out. 0: No blank region.*/
uint32_t lcd_afifo_reset : 1; /*LCD AFIFO reset signal.*/
uint32_t lcd_cd_data_set : 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. */
uint32_t lcd_cd_dummy_set : 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. */
uint32_t lcd_cd_cmd_set : 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. */
uint32_t lcd_cd_idle_edge : 1; /*The default value of LCD_CD. */
};
uint32_t val;
} lcd_misc;
union {
struct {
uint32_t lcd_hb_front : 11; /*It is the horizontal blank front porch of a frame. */
uint32_t lcd_va_height : 10; /*It is the vertical active height of a frame. */
uint32_t lcd_vt_height : 10; /*It is the vertical total height of a frame. */
uint32_t lcd_rgb_mode_en : 1; /*1: Enable LCD RGB mode. 0: Disable LCD RGB mode.*/
};
uint32_t val;
} lcd_ctrl;
union {
struct {
uint32_t lcd_vb_front : 8; /*It is the vertical blank front porch of a frame. */
uint32_t lcd_ha_width : 12; /*It is the horizontal active width of a frame. */
uint32_t lcd_ht_width : 12; /*It is the horizontal total width of a frame. */
};
uint32_t val;
} lcd_ctrl1;
union {
struct {
uint32_t lcd_vsync_width : 7; /*It is the position of LCD_VSYNC active pulse in a line. */
uint32_t lcd_vsync_idle_pol : 1; /*It is the idle value of LCD_VSYNC. */
uint32_t lcd_de_idle_pol : 1; /*It is the idle value of LCD_DE. */
uint32_t lcd_hs_blank_en : 1; /*1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. */
uint32_t reserved10 : 6; /*reserved*/
uint32_t lcd_hsync_width : 7; /*It is the position of LCD_HSYNC active pulse in a line. */
uint32_t lcd_hsync_idle_pol : 1; /*It is the idle value of LCD_HSYNC. */
uint32_t lcd_hsync_position : 8; /*It is the position of LCD_HSYNC active pulse in a line. */
};
uint32_t val;
} lcd_ctrl2;
uint32_t lcd_first_cmd_val;
uint32_t lcd_latter_cmd_val;
union {
struct {
uint32_t dout16_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout17_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout18_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout19_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout20_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout21_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout22_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout23_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t lcd_cd_mode : 2; /*The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t lcd_de_mode : 2; /*The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t lcd_hsync_mode : 2; /*The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t lcd_vsync_mode : 2; /*The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t reserved24 : 8; /*reserved*/
};
uint32_t val;
} lcd_dly_mode_cfg1;
uint32_t reserved_34;
union {
struct {
uint32_t dout0_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout1_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout2_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout3_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout4_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout5_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout6_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout7_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout8_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout9_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout10_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout11_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout12_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout13_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout14_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
uint32_t dout15_mode : 2; /*The output data bit $n is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.*/
};
uint32_t val;
} lcd_dly_mode_cfg2;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
union {
struct {
uint32_t lcd_vsync : 1; /*The enable bit for LCD frame end interrupt.*/
uint32_t lcd_trans_done : 1; /*The enable bit for lcd transfer end interrupt.*/
uint32_t cam_vsync : 1; /*The enable bit for Camera frame end interrupt.*/
uint32_t cam_hs : 1; /*The enable bit for Camera line interrupt.*/
uint32_t reserved4 : 28; /*reserved*/
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t lcd_vsync : 1; /*The raw bit for LCD frame end interrupt.*/
uint32_t lcd_trans_done : 1; /*The raw bit for lcd transfer end interrupt.*/
uint32_t cam_vsync : 1; /*The raw bit for Camera frame end interrupt.*/
uint32_t cam_hs : 1; /*The raw bit for Camera line interrupt.*/
uint32_t reserved4 : 28; /*reserved*/
};
uint32_t val;
} dma_int_raw;
union {
struct {
uint32_t lcd_vsync : 1; /*The status bit for LCD frame end interrupt.*/
uint32_t lcd_trans_done : 1; /*The status bit for lcd transfer end interrupt.*/
uint32_t cam_vsync : 1; /*The status bit for Camera frame end interrupt.*/
uint32_t cam_hs : 1; /*The status bit for Camera transfer end interrupt.*/
uint32_t reserved4 : 28; /*reserved*/
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t lcd_vsync : 1; /*The clear bit for LCD frame end interrupt.*/
uint32_t lcd_trans_done : 1; /*The clear bit for lcd transfer end interrupt.*/
uint32_t cam_vsync : 1; /*The clear bit for Camera frame end interrupt.*/
uint32_t cam_hs : 1; /*The clear bit for Camera line interrupt.*/
uint32_t reserved4 : 28; /*reserved*/
};
uint32_t val;
} dma_int_clr;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
union {
struct {
uint32_t date : 28; /*LCD_CAM version control register*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} lcd_cam_dev_t;
extern lcd_cam_dev_t LCD_CAM;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_LCD_CAM_STRUCT_H_ */

2
components/soc/esp32p4/include/soc/lcdcam_struct.h
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@ -820,7 +820,7 @@ typedef union {
} lcdcam_lc_reg_date_reg_t;
typedef struct {
typedef struct lcd_cam_dev_s {
volatile lcdcam_lcd_clock_reg_t lcd_clock;
volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;

418
components/soc/esp32p4/include/soc/lp_aon_reg.h Normal file
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@ -0,0 +1,418 @@
/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_AON_STORE0_REG register
* need_des
*/
#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
/** LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE0 0xFFFFFFFFU
#define LP_AON_STORE0_M (LP_AON_STORE0_V << LP_AON_STORE0_S)
#define LP_AON_STORE0_V 0xFFFFFFFFU
#define LP_AON_STORE0_S 0
/** LP_AON_STORE1_REG register
* need_des
*/
#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
/** LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE1 0xFFFFFFFFU
#define LP_AON_STORE1_M (LP_AON_STORE1_V << LP_AON_STORE1_S)
#define LP_AON_STORE1_V 0xFFFFFFFFU
#define LP_AON_STORE1_S 0
/** LP_AON_STORE2_REG register
* need_des
*/
#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
/** LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE2 0xFFFFFFFFU
#define LP_AON_STORE2_M (LP_AON_STORE2_V << LP_AON_STORE2_S)
#define LP_AON_STORE2_V 0xFFFFFFFFU
#define LP_AON_STORE2_S 0
/** LP_AON_STORE3_REG register
* need_des
*/
#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
/** LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE3 0xFFFFFFFFU
#define LP_AON_STORE3_M (LP_AON_STORE3_V << LP_AON_STORE3_S)
#define LP_AON_STORE3_V 0xFFFFFFFFU
#define LP_AON_STORE3_S 0
/** LP_AON_STORE4_REG register
* need_des
*/
#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
/** LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE4 0xFFFFFFFFU
#define LP_AON_STORE4_M (LP_AON_STORE4_V << LP_AON_STORE4_S)
#define LP_AON_STORE4_V 0xFFFFFFFFU
#define LP_AON_STORE4_S 0
/** LP_AON_STORE5_REG register
* need_des
*/
#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
/** LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE5 0xFFFFFFFFU
#define LP_AON_STORE5_M (LP_AON_STORE5_V << LP_AON_STORE5_S)
#define LP_AON_STORE5_V 0xFFFFFFFFU
#define LP_AON_STORE5_S 0
/** LP_AON_STORE6_REG register
* need_des
*/
#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
/** LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE6 0xFFFFFFFFU
#define LP_AON_STORE6_M (LP_AON_STORE6_V << LP_AON_STORE6_S)
#define LP_AON_STORE6_V 0xFFFFFFFFU
#define LP_AON_STORE6_S 0
/** LP_AON_STORE7_REG register
* need_des
*/
#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
/** LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE7 0xFFFFFFFFU
#define LP_AON_STORE7_M (LP_AON_STORE7_V << LP_AON_STORE7_S)
#define LP_AON_STORE7_V 0xFFFFFFFFU
#define LP_AON_STORE7_S 0
/** LP_AON_STORE8_REG register
* need_des
*/
#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
/** LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE8 0xFFFFFFFFU
#define LP_AON_STORE8_M (LP_AON_STORE8_V << LP_AON_STORE8_S)
#define LP_AON_STORE8_V 0xFFFFFFFFU
#define LP_AON_STORE8_S 0
/** LP_AON_STORE9_REG register
* need_des
*/
#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
/** LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_STORE9 0xFFFFFFFFU
#define LP_AON_STORE9_M (LP_AON_STORE9_V << LP_AON_STORE9_S)
#define LP_AON_STORE9_V 0xFFFFFFFFU
#define LP_AON_STORE9_S 0
/** LP_AON_GPIO_MUX_REG register
* need_des
*/
#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_MUX_SEL 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_S 0
/** LP_AON_GPIO_HOLD0_REG register
* need_des
*/
#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_S 0
/** LP_AON_GPIO_HOLD1_REG register
* need_des
*/
#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_S 0
/** LP_AON_SYS_CFG_REG register
* need_des
*/
#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30))
#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U
#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30
/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_HPSYS_SW_RESET (BIT(31))
#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
#define LP_AON_HPSYS_SW_RESET_V 0x00000001U
#define LP_AON_HPSYS_SW_RESET_S 31
/** LP_AON_CPUCORE0_CFG_REG register
* need_des
*/
#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_S 0
/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_SW_RESET (BIT(28))
#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_SW_RESET_S 28
/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29))
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29
/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30))
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30
/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31))
#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U
#define LP_AON_CPU_CORE0_DRESET_MASK_S 31
/** LP_AON_IO_MUX_REG register
* need_des
*/
#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31))
#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U
#define LP_AON_IO_MUX_RESET_DISABLE_S 31
/** LP_AON_EXT_WAKEUP_CNTL_REG register
* need_des
*/
#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_S 0
/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14))
#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U
#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14
/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_S 15
/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_LV 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_S 23
/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_FILTER (BIT(31))
#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U
#define LP_AON_EXT_WAKEUP_FILTER_S 31
/** LP_AON_USB_REG register
* need_des
*/
#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44)
/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_USB_RESET_DISABLE (BIT(31))
#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
#define LP_AON_USB_RESET_DISABLE_V 0x00000001U
#define LP_AON_USB_RESET_DISABLE_S 31
/** LP_AON_LPBUS_REG register
* need_des
*/
#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0;
* This field controls fast memory WPULSE parameter.
*/
#define LP_AON_FAST_MEM_WPULSE 0x00000007U
#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S)
#define LP_AON_FAST_MEM_WPULSE_V 0x00000007U
#define LP_AON_FAST_MEM_WPULSE_S 16
/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4;
* This field controls fast memory WA parameter.
*/
#define LP_AON_FAST_MEM_WA 0x00000007U
#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S)
#define LP_AON_FAST_MEM_WA_V 0x00000007U
#define LP_AON_FAST_MEM_WA_S 19
/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0;
* This field controls fast memory RA parameter.
*/
#define LP_AON_FAST_MEM_RA 0x00000003U
#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S)
#define LP_AON_FAST_MEM_RA_V 0x00000003U
#define LP_AON_FAST_MEM_RA_S 22
/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28))
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28
/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29))
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29
/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30))
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30
/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL (BIT(31))
#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_S 31
/** LP_AON_SDIO_ACTIVE_REG register
* need_des
*/
#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
#define LP_AON_SDIO_ACT_DNUM 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_S 22
/** LP_AON_LPCORE_REG register
* need_des
*/
#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50)
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1
/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_DISABLE (BIT(31))
#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S)
#define LP_AON_LPCORE_DISABLE_V 0x00000001U
#define LP_AON_LPCORE_DISABLE_S 31
/** LP_AON_SAR_CCT_REG register
* need_des
*/
#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
#define LP_AON_SAR2_PWDET_CCT 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_S 29
/** LP_AON_DATE_REG register
* need_des
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 35672704;
* need_des
*/
#define LP_AON_DATE 0x7FFFFFFFU
#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S)
#define LP_AON_DATE_V 0x7FFFFFFFU
#define LP_AON_DATE_S 0
/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_CLK_EN (BIT(31))
#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
#define LP_AON_CLK_EN_V 0x00000001U
#define LP_AON_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of store register
* need_des
*/
typedef union {
struct {
/** store : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t store:32;
};
uint32_t val;
} lp_aon_store_reg_t;
/** Type of gpio_mux register
* need_des
*/
typedef union {
struct {
/** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t gpio_mux_sel:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_aon_gpio_mux_reg_t;
/** Type of gpio_hold0 register
* need_des
*/
typedef union {
struct {
/** gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t gpio_hold0:32;
};
uint32_t val;
} lp_aon_gpio_hold0_reg_t;
/** Type of gpio_hold1 register
* need_des
*/
typedef union {
struct {
/** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t gpio_hold1:32;
};
uint32_t val;
} lp_aon_gpio_hold1_reg_t;
/** Type of sys_cfg register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** force_download_boot : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t force_download_boot:1;
/** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t hpsys_sw_reset:1;
};
uint32_t val;
} lp_aon_sys_cfg_reg_t;
/** Type of cpucore0_cfg register
* need_des
*/
typedef union {
struct {
/** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t cpu_core0_sw_stall:8;
uint32_t reserved_8:20;
/** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t cpu_core0_sw_reset:1;
/** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t cpu_core0_ocd_halt_on_reset:1;
/** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t cpu_core0_stat_vector_sel:1;
/** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t cpu_core0_dreset_mask:1;
};
uint32_t val;
} lp_aon_cpucore0_cfg_reg_t;
/** Type of io_mux register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t io_mux_reset_disable:1;
};
uint32_t val;
} lp_aon_io_mux_reg_t;
/** Type of ext_wakeup_cntl register
* need_des
*/
typedef union {
struct {
/** ext_wakeup_status : RO; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t ext_wakeup_status:8;
uint32_t reserved_8:6;
/** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0;
* need_des
*/
uint32_t ext_wakeup_status_clr:1;
/** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0;
* need_des
*/
uint32_t ext_wakeup_sel:8;
/** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
uint32_t ext_wakeup_lv:8;
/** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ext_wakeup_filter:1;
};
uint32_t val;
} lp_aon_ext_wakeup_cntl_reg_t;
/** Type of usb register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** usb_reset_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t usb_reset_disable:1;
};
uint32_t val;
} lp_aon_usb_reg_t;
/** Type of lpbus register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:16;
/** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0;
* This field controls fast memory WPULSE parameter.
*/
uint32_t fast_mem_wpulse:3;
/** fast_mem_wa : R/W; bitpos: [21:19]; default: 4;
* This field controls fast memory WA parameter.
*/
uint32_t fast_mem_wa:3;
/** fast_mem_ra : R/W; bitpos: [23:22]; default: 0;
* This field controls fast memory RA parameter.
*/
uint32_t fast_mem_ra:2;
uint32_t reserved_24:4;
/** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_fsm_idle:1;
/** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_sel_status:1;
/** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t fast_mem_mux_sel_update:1;
/** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_sel:1;
};
uint32_t val;
} lp_aon_lpbus_reg_t;
/** Type of sdio_active register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
uint32_t sdio_act_dnum:10;
};
uint32_t val;
} lp_aon_sdio_active_reg_t;
/** Type of lpcore register
* need_des
*/
typedef union {
struct {
/** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t lpcore_etm_wakeup_flag_clr:1;
/** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t lpcore_etm_wakeup_flag:1;
uint32_t reserved_2:29;
/** lpcore_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lpcore_disable:1;
};
uint32_t val;
} lp_aon_lpcore_reg_t;
/** Type of sar_cct register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
uint32_t sar2_pwdet_cct:3;
};
uint32_t val;
} lp_aon_sar_cct_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 35672704;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_aon_date_reg_t;
typedef struct lp_aon_dev_t {
volatile lp_aon_store_reg_t store[10];
volatile lp_aon_gpio_mux_reg_t gpio_mux;
volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
volatile lp_aon_sys_cfg_reg_t sys_cfg;
volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg;
volatile lp_aon_io_mux_reg_t io_mux;
volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
volatile lp_aon_usb_reg_t usb;
volatile lp_aon_lpbus_reg_t lpbus;
volatile lp_aon_sdio_active_reg_t sdio_active;
volatile lp_aon_lpcore_reg_t lpcore;
volatile lp_aon_sar_cct_reg_t sar_cct;
uint32_t reserved_058[233];
volatile lp_aon_date_reg_t date;
} lp_aon_dev_t;
extern lp_aon_dev_t LP_AON;
#ifndef __cplusplus
_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/lp_apm0_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM0_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
#define LP_APM0_REGION_FILTER_EN 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_S 0
/** LP_APM0_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S)
#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_S 0
/** LP_APM0_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S)
#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_S 0
/** LP_APM0_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_X (BIT(0))
#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S)
#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_X_S 0
/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_W (BIT(1))
#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S)
#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_W_S 1
/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_R (BIT(2))
#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S)
#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_R_S 2
/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_X (BIT(4))
#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S)
#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_X_S 4
/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_W (BIT(5))
#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S)
#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_W_S 5
/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_R (BIT(6))
#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S)
#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_R_S 6
/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_X (BIT(8))
#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S)
#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_X_S 8
/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_W (BIT(9))
#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S)
#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_W_S 9
/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_R (BIT(10))
#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S)
#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_R_S 10
/** LP_APM0_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S)
#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_S 0
/** LP_APM0_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S)
#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_S 0
/** LP_APM0_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_X (BIT(0))
#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S)
#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_X_S 0
/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_W (BIT(1))
#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S)
#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_W_S 1
/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_R (BIT(2))
#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S)
#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_R_S 2
/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_X (BIT(4))
#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S)
#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_X_S 4
/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_W (BIT(5))
#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S)
#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_W_S 5
/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_R (BIT(6))
#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S)
#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_R_S 6
/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_X (BIT(8))
#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S)
#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_X_S 8
/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_W (BIT(9))
#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S)
#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_W_S 9
/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_R (BIT(10))
#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S)
#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_R_S 10
/** LP_APM0_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S)
#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_S 0
/** LP_APM0_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S)
#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_S 0
/** LP_APM0_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_X (BIT(0))
#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S)
#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_X_S 0
/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_W (BIT(1))
#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S)
#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_W_S 1
/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_R (BIT(2))
#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S)
#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_R_S 2
/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_X (BIT(4))
#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S)
#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_X_S 4
/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_W (BIT(5))
#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S)
#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_W_S 5
/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_R (BIT(6))
#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S)
#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_R_S 6
/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_X (BIT(8))
#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S)
#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_X_S 8
/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_W (BIT(9))
#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S)
#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_W_S 9
/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_R (BIT(10))
#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S)
#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_R_S 10
/** LP_APM0_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S)
#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_S 0
/** LP_APM0_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S)
#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_S 0
/** LP_APM0_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_X (BIT(0))
#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S)
#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_X_S 0
/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_W (BIT(1))
#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S)
#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_W_S 1
/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_R (BIT(2))
#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S)
#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_R_S 2
/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_X (BIT(4))
#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S)
#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_X_S 4
/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_W (BIT(5))
#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S)
#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_W_S 5
/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_R (BIT(6))
#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S)
#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_R_S 6
/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_X (BIT(8))
#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S)
#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_X_S 8
/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_W (BIT(9))
#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S)
#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_W_S 9
/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_R (BIT(10))
#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S)
#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_R_S 10
/** LP_APM0_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM0_M0_PMS_FUNC_EN (BIT(0))
#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S)
#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U
#define LP_APM0_M0_PMS_FUNC_EN_S 0
/** LP_APM0_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_S 0
/** LP_APM0_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0))
#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S)
#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM0_M0_REGION_STATUS_CLR_S 0
/** LP_APM0_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_S 0
/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S)
#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_S 16
/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S)
#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_S 18
/** LP_APM0_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S)
#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_S 0
/** LP_APM0_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
#define LP_APM0_M0_APM_INT_EN (BIT(0))
#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
#define LP_APM0_M0_APM_INT_EN_V 0x00000001U
#define LP_APM0_M0_APM_INT_EN_S 0
/** LP_APM0_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_APM0_CLK_EN (BIT(0))
#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)
#define LP_APM0_CLK_EN_V 0x00000001U
#define LP_APM0_CLK_EN_S 0
/** LP_APM0_DATE_REG register
* Version register
*/
#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
#define LP_APM0_DATE 0x0FFFFFFFU
#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S)
#define LP_APM0_DATE_V 0x0FFFFFFFU
#define LP_APM0_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm0_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of region0_addr_start register
* Region address register
*/
typedef union {
struct {
/** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
uint32_t region0_addr_start:32;
};
uint32_t val;
} lp_apm0_region0_addr_start_reg_t;
/** Type of region0_addr_end register
* Region address register
*/
typedef union {
struct {
/** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
uint32_t region0_addr_end:32;
};
uint32_t val;
} lp_apm0_region0_addr_end_reg_t;
/** Type of region1_addr_start register
* Region address register
*/
typedef union {
struct {
/** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
uint32_t region1_addr_start:32;
};
uint32_t val;
} lp_apm0_region1_addr_start_reg_t;
/** Type of region1_addr_end register
* Region address register
*/
typedef union {
struct {
/** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
uint32_t region1_addr_end:32;
};
uint32_t val;
} lp_apm0_region1_addr_end_reg_t;
/** Type of region2_addr_start register
* Region address register
*/
typedef union {
struct {
/** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
uint32_t region2_addr_start:32;
};
uint32_t val;
} lp_apm0_region2_addr_start_reg_t;
/** Type of region2_addr_end register
* Region address register
*/
typedef union {
struct {
/** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
uint32_t region2_addr_end:32;
};
uint32_t val;
} lp_apm0_region2_addr_end_reg_t;
/** Type of region3_addr_start register
* Region address register
*/
typedef union {
struct {
/** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
uint32_t region3_addr_start:32;
};
uint32_t val;
} lp_apm0_region3_addr_start_reg_t;
/** Type of region3_addr_end register
* Region address register
*/
typedef union {
struct {
/** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
uint32_t region3_addr_end:32;
};
uint32_t val;
} lp_apm0_region3_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of region0_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region0_r0_pms_x:1;
/** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region0_r0_pms_w:1;
/** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region0_r0_pms_r:1;
uint32_t reserved_3:1;
/** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region0_r1_pms_x:1;
/** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region0_r1_pms_w:1;
/** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region0_r1_pms_r:1;
uint32_t reserved_7:1;
/** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region0_r2_pms_x:1;
/** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region0_r2_pms_w:1;
/** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region0_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm0_region0_pms_attr_reg_t;
/** Type of region1_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region1_r0_pms_x:1;
/** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region1_r0_pms_w:1;
/** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region1_r0_pms_r:1;
uint32_t reserved_3:1;
/** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region1_r1_pms_x:1;
/** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region1_r1_pms_w:1;
/** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region1_r1_pms_r:1;
uint32_t reserved_7:1;
/** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region1_r2_pms_x:1;
/** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region1_r2_pms_w:1;
/** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region1_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm0_region1_pms_attr_reg_t;
/** Type of region2_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region2_r0_pms_x:1;
/** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region2_r0_pms_w:1;
/** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region2_r0_pms_r:1;
uint32_t reserved_3:1;
/** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region2_r1_pms_x:1;
/** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region2_r1_pms_w:1;
/** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region2_r1_pms_r:1;
uint32_t reserved_7:1;
/** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region2_r2_pms_x:1;
/** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region2_r2_pms_w:1;
/** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region2_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm0_region2_pms_attr_reg_t;
/** Type of region3_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region3_r0_pms_x:1;
/** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region3_r0_pms_w:1;
/** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region3_r0_pms_r:1;
uint32_t reserved_3:1;
/** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region3_r1_pms_x:1;
/** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region3_r1_pms_w:1;
/** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region3_r1_pms_r:1;
uint32_t reserved_7:1;
/** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region3_r2_pms_x:1;
/** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region3_r2_pms_w:1;
/** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region3_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm0_region3_pms_attr_reg_t;
/** Group: PMS function control register */
/** Type of func_ctrl register
* PMS function control register
*/
typedef union {
struct {
/** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_pms_func_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm0_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m0_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm0_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm0_m0_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
uint32_t m0_apm_int_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm0_date_reg_t;
typedef struct lp_apm0_dev_t {
volatile lp_apm0_region_filter_en_reg_t region_filter_en;
volatile lp_apm0_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm0_region0_addr_end_reg_t region0_addr_end;
volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr;
volatile lp_apm0_region1_addr_start_reg_t region1_addr_start;
volatile lp_apm0_region1_addr_end_reg_t region1_addr_end;
volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr;
volatile lp_apm0_region2_addr_start_reg_t region2_addr_start;
volatile lp_apm0_region2_addr_end_reg_t region2_addr_end;
volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr;
volatile lp_apm0_region3_addr_start_reg_t region3_addr_start;
volatile lp_apm0_region3_addr_end_reg_t region3_addr_end;
volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr;
uint32_t reserved_034[36];
volatile lp_apm0_func_ctrl_reg_t func_ctrl;
volatile lp_apm0_m0_status_reg_t m0_status;
volatile lp_apm0_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm0_int_en_reg_t int_en;
volatile lp_apm0_clock_gate_reg_t clock_gate;
uint32_t reserved_0e0[455];
volatile lp_apm0_date_reg_t date;
} lp_apm0_dev_t;
extern lp_apm0_dev_t LP_APM0;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
#define LP_APM_REGION_FILTER_EN 0x0000000FU
#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
#define LP_APM_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM_REGION_FILTER_EN_S 0
/** LP_APM_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S)
#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_S 0
/** LP_APM_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S)
#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_S 0
/** LP_APM_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_X (BIT(0))
#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S)
#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_X_S 0
/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_W (BIT(1))
#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S)
#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_W_S 1
/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_R (BIT(2))
#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S)
#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_R_S 2
/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_X (BIT(4))
#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S)
#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_X_S 4
/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_W (BIT(5))
#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S)
#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_W_S 5
/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_R (BIT(6))
#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S)
#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_R_S 6
/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_X (BIT(8))
#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S)
#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_X_S 8
/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_W (BIT(9))
#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S)
#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_W_S 9
/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_R (BIT(10))
#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S)
#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_R_S 10
/** LP_APM_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S)
#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_S 0
/** LP_APM_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S)
#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_S 0
/** LP_APM_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_X (BIT(0))
#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S)
#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_X_S 0
/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_W (BIT(1))
#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S)
#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_W_S 1
/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_R (BIT(2))
#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S)
#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_R_S 2
/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_X (BIT(4))
#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S)
#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_X_S 4
/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_W (BIT(5))
#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S)
#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_W_S 5
/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_R (BIT(6))
#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S)
#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_R_S 6
/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_X (BIT(8))
#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S)
#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_X_S 8
/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_W (BIT(9))
#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S)
#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_W_S 9
/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_R (BIT(10))
#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S)
#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_R_S 10
/** LP_APM_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c)
/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S)
#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_S 0
/** LP_APM_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20)
/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S)
#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_S 0
/** LP_APM_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24)
/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_X (BIT(0))
#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S)
#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_X_S 0
/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_W (BIT(1))
#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S)
#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_W_S 1
/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_R (BIT(2))
#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S)
#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_R_S 2
/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_X (BIT(4))
#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S)
#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_X_S 4
/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_W (BIT(5))
#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S)
#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_W_S 5
/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_R (BIT(6))
#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S)
#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_R_S 6
/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_X (BIT(8))
#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S)
#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_X_S 8
/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_W (BIT(9))
#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S)
#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_W_S 9
/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_R (BIT(10))
#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S)
#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_R_S 10
/** LP_APM_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28)
/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S)
#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_S 0
/** LP_APM_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c)
/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S)
#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_S 0
/** LP_APM_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30)
/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_X (BIT(0))
#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S)
#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_X_S 0
/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_W (BIT(1))
#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S)
#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_W_S 1
/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_R (BIT(2))
#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S)
#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_R_S 2
/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_X (BIT(4))
#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S)
#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_X_S 4
/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_W (BIT(5))
#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S)
#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_W_S 5
/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_R (BIT(6))
#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S)
#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_R_S 6
/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_X (BIT(8))
#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S)
#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_X_S 8
/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_W (BIT(9))
#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S)
#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_W_S 9
/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_R (BIT(10))
#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S)
#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_R_S 10
/** LP_APM_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM_M0_PMS_FUNC_EN (BIT(0))
#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S)
#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U
#define LP_APM_M0_PMS_FUNC_EN_S 0
/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
#define LP_APM_M1_PMS_FUNC_EN (BIT(1))
#define LP_APM_M1_PMS_FUNC_EN_M (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S)
#define LP_APM_M1_PMS_FUNC_EN_V 0x00000001U
#define LP_APM_M1_PMS_FUNC_EN_S 1
/** LP_APM_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_S 0
/** LP_APM_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM_M0_REGION_STATUS_CLR (BIT(0))
#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S)
#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM_M0_REGION_STATUS_CLR_S 0
/** LP_APM_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_S 0
/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S)
#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_S 16
/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S)
#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_S 18
/** LP_APM_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S)
#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_S 0
/** LP_APM_M1_STATUS_REG register
* M1 status register
*/
#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8)
/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S)
#define LP_APM_M1_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_S 0
/** LP_APM_M1_STATUS_CLR_REG register
* M1 status clear register
*/
#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc)
/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM_M1_REGION_STATUS_CLR (BIT(0))
#define LP_APM_M1_REGION_STATUS_CLR_M (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S)
#define LP_APM_M1_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM_M1_REGION_STATUS_CLR_S 0
/** LP_APM_M1_EXCEPTION_INFO0_REG register
* M1 exception_info0 register
*/
#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0)
/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S)
#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_S 0
/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM_M1_EXCEPTION_MODE 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S)
#define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_S 16
/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM_M1_EXCEPTION_ID 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S)
#define LP_APM_M1_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_S 18
/** LP_APM_M1_EXCEPTION_INFO1_REG register
* M1 exception_info1 register
*/
#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4)
/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S)
#define LP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_S 0
/** LP_APM_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
#define LP_APM_M0_APM_INT_EN (BIT(0))
#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
#define LP_APM_M0_APM_INT_EN_V 0x00000001U
#define LP_APM_M0_APM_INT_EN_S 0
/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
* APM M1 interrupt enable
*/
#define LP_APM_M1_APM_INT_EN (BIT(1))
#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S)
#define LP_APM_M1_APM_INT_EN_V 0x00000001U
#define LP_APM_M1_APM_INT_EN_S 1
/** LP_APM_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_APM_CLK_EN (BIT(0))
#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)
#define LP_APM_CLK_EN_V 0x00000001U
#define LP_APM_CLK_EN_S 0
/** LP_APM_DATE_REG register
* Version register
*/
#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc)
/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
#define LP_APM_DATE 0x0FFFFFFFU
#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S)
#define LP_APM_DATE_V 0x0FFFFFFFU
#define LP_APM_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of region0_addr_start register
* Region address register
*/
typedef union {
struct {
/** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
uint32_t region0_addr_start:32;
};
uint32_t val;
} lp_apm_region0_addr_start_reg_t;
/** Type of region0_addr_end register
* Region address register
*/
typedef union {
struct {
/** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
uint32_t region0_addr_end:32;
};
uint32_t val;
} lp_apm_region0_addr_end_reg_t;
/** Type of region1_addr_start register
* Region address register
*/
typedef union {
struct {
/** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
uint32_t region1_addr_start:32;
};
uint32_t val;
} lp_apm_region1_addr_start_reg_t;
/** Type of region1_addr_end register
* Region address register
*/
typedef union {
struct {
/** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
uint32_t region1_addr_end:32;
};
uint32_t val;
} lp_apm_region1_addr_end_reg_t;
/** Type of region2_addr_start register
* Region address register
*/
typedef union {
struct {
/** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
uint32_t region2_addr_start:32;
};
uint32_t val;
} lp_apm_region2_addr_start_reg_t;
/** Type of region2_addr_end register
* Region address register
*/
typedef union {
struct {
/** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
uint32_t region2_addr_end:32;
};
uint32_t val;
} lp_apm_region2_addr_end_reg_t;
/** Type of region3_addr_start register
* Region address register
*/
typedef union {
struct {
/** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
uint32_t region3_addr_start:32;
};
uint32_t val;
} lp_apm_region3_addr_start_reg_t;
/** Type of region3_addr_end register
* Region address register
*/
typedef union {
struct {
/** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
uint32_t region3_addr_end:32;
};
uint32_t val;
} lp_apm_region3_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of region0_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region0_r0_pms_x:1;
/** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region0_r0_pms_w:1;
/** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region0_r0_pms_r:1;
uint32_t reserved_3:1;
/** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region0_r1_pms_x:1;
/** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region0_r1_pms_w:1;
/** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region0_r1_pms_r:1;
uint32_t reserved_7:1;
/** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region0_r2_pms_x:1;
/** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region0_r2_pms_w:1;
/** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region0_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region0_pms_attr_reg_t;
/** Type of region1_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region1_r0_pms_x:1;
/** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region1_r0_pms_w:1;
/** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region1_r0_pms_r:1;
uint32_t reserved_3:1;
/** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region1_r1_pms_x:1;
/** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region1_r1_pms_w:1;
/** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region1_r1_pms_r:1;
uint32_t reserved_7:1;
/** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region1_r2_pms_x:1;
/** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region1_r2_pms_w:1;
/** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region1_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region1_pms_attr_reg_t;
/** Type of region2_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region2_r0_pms_x:1;
/** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region2_r0_pms_w:1;
/** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region2_r0_pms_r:1;
uint32_t reserved_3:1;
/** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region2_r1_pms_x:1;
/** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region2_r1_pms_w:1;
/** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region2_r1_pms_r:1;
uint32_t reserved_7:1;
/** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region2_r2_pms_x:1;
/** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region2_r2_pms_w:1;
/** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region2_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region2_pms_attr_reg_t;
/** Type of region3_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region3_r0_pms_x:1;
/** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region3_r0_pms_w:1;
/** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region3_r0_pms_r:1;
uint32_t reserved_3:1;
/** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region3_r1_pms_x:1;
/** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region3_r1_pms_w:1;
/** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region3_r1_pms_r:1;
uint32_t reserved_7:1;
/** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region3_r2_pms_x:1;
/** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region3_r2_pms_w:1;
/** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region3_r2_pms_r:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_apm_region3_pms_attr_reg_t;
/** Group: PMS function control register */
/** Type of func_ctrl register
* PMS function control register
*/
typedef union {
struct {
/** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_pms_func_en:1;
/** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_pms_func_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m0_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m1_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m1_exception_region:4;
uint32_t reserved_4:12;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} lp_apm_m1_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* APM M1 interrupt enable
*/
uint32_t m1_apm_int_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35672640;
* reg_date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm_date_reg_t;
typedef struct lp_apm_dev_t {
volatile lp_apm_region_filter_en_reg_t region_filter_en;
volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm_region0_addr_end_reg_t region0_addr_end;
volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr;
volatile lp_apm_region1_addr_start_reg_t region1_addr_start;
volatile lp_apm_region1_addr_end_reg_t region1_addr_end;
volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr;
volatile lp_apm_region2_addr_start_reg_t region2_addr_start;
volatile lp_apm_region2_addr_end_reg_t region2_addr_end;
volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr;
volatile lp_apm_region3_addr_start_reg_t region3_addr_start;
volatile lp_apm_region3_addr_end_reg_t region3_addr_end;
volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr;
uint32_t reserved_034[36];
volatile lp_apm_func_ctrl_reg_t func_ctrl;
volatile lp_apm_m0_status_reg_t m0_status;
volatile lp_apm_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm_m1_status_reg_t m1_status;
volatile lp_apm_m1_status_clr_reg_t m1_status_clr;
volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile lp_apm_int_en_reg_t int_en;
volatile lp_apm_clock_gate_reg_t clock_gate;
uint32_t reserved_0f0[3];
volatile lp_apm_date_reg_t date;
} lp_apm_dev_t;
extern lp_apm_dev_t LP_APM;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/lp_clkrst_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_CLKRST_LP_CLK_CONF_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
* need_des
*/
#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_S 0
/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [2]; default: 1;
* need_des
*/
#define LP_CLKRST_FAST_CLK_SEL (BIT(2))
#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
#define LP_CLKRST_FAST_CLK_SEL_V 0x00000001U
#define LP_CLKRST_FAST_CLK_SEL_S 2
/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_S 3
/** LP_CLKRST_LP_CLK_PO_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
* need_des
*/
#define LP_CLKRST_AON_SLOW_OEN (BIT(0))
#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_AON_SLOW_OEN_S 0
/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
* need_des
*/
#define LP_CLKRST_AON_FAST_OEN (BIT(1))
#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U
#define LP_CLKRST_AON_FAST_OEN_S 1
/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
* need_des
*/
#define LP_CLKRST_SOSC_OEN (BIT(2))
#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
#define LP_CLKRST_SOSC_OEN_V 0x00000001U
#define LP_CLKRST_SOSC_OEN_S 2
/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
* need_des
*/
#define LP_CLKRST_FOSC_OEN (BIT(3))
#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
#define LP_CLKRST_FOSC_OEN_V 0x00000001U
#define LP_CLKRST_FOSC_OEN_S 3
/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
* need_des
*/
#define LP_CLKRST_OSC32K_OEN (BIT(4))
#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
#define LP_CLKRST_OSC32K_OEN_V 0x00000001U
#define LP_CLKRST_OSC32K_OEN_S 4
/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
* need_des
*/
#define LP_CLKRST_XTAL32K_OEN (BIT(5))
#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U
#define LP_CLKRST_XTAL32K_OEN_S 5
/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
* need_des
*/
#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6))
#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U
#define LP_CLKRST_CORE_EFUSE_OEN_S 6
/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
* need_des
*/
#define LP_CLKRST_SLOW_OEN (BIT(7))
#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
#define LP_CLKRST_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_SLOW_OEN_S 7
/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
* need_des
*/
#define LP_CLKRST_FAST_OEN (BIT(8))
#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
#define LP_CLKRST_FAST_OEN_V 0x00000001U
#define LP_CLKRST_FAST_OEN_S 8
/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
* need_des
*/
#define LP_CLKRST_RNG_OEN (BIT(9))
#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
#define LP_CLKRST_RNG_OEN_V 0x00000001U
#define LP_CLKRST_RNG_OEN_S 9
/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
* need_des
*/
#define LP_CLKRST_LPBUS_OEN (BIT(10))
#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
#define LP_CLKRST_LPBUS_OEN_V 0x00000001U
#define LP_CLKRST_LPBUS_OEN_S 10
/** LP_CLKRST_LP_CLK_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_FAST_ORI_GATE (BIT(31))
#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U
#define LP_CLKRST_FAST_ORI_GATE_S 31
/** LP_CLKRST_LP_RST_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28))
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28
/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29))
#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U
#define LP_CLKRST_LP_TIMER_RESET_EN_S 29
/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_WDT_RESET_EN (BIT(30))
#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U
#define LP_CLKRST_WDT_RESET_EN_S 30
/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31))
#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U
#define LP_CLKRST_ANA_PERI_RESET_EN_S 31
/** LP_CLKRST_RESET_CAUSE_REG register
* need_des
*/
#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
* need_des
*/
#define LP_CLKRST_RESET_CAUSE 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_S 0
/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5))
#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_S 5
/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29))
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29
/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30))
#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30
/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31))
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31
/** LP_CLKRST_CPU_RESET_REG register
* need_des
*/
#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
* need_des
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22
/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25))
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25
/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
* need_des
*/
#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_S 26
/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CPU_STALL_EN (BIT(31))
#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U
#define LP_CLKRST_CPU_STALL_EN_S 31
/** LP_CLKRST_FOSC_CNTL_REG register
* need_des
*/
#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
#define LP_CLKRST_FOSC_DFREQ 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_S 22
/** LP_CLKRST_RC32K_CNTL_REG register
* need_des
*/
#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
#define LP_CLKRST_RC32K_DFREQ 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_S 22
/** LP_CLKRST_CLK_TO_HP_REG register
* need_des
*/
#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28))
#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_XTAL32K_S 28
/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_SOSC (BIT(29))
#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_SOSC_S 29
/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_OSC32K (BIT(30))
#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_OSC32K_S 30
/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_FOSC (BIT(31))
#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_FOSC_S 31
/** LP_CLKRST_LPMEM_FORCE_REG register
* need_des
*/
#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31))
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31
/** LP_CLKRST_LPPERI_REG register
* need_des
*/
#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28)
/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30))
#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S)
#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_I2C_CLK_SEL_S 30
/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31))
#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S)
#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_UART_CLK_SEL_S 31
/** LP_CLKRST_XTAL32K_REG register
* need_des
*/
#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
* need_des
*/
#define LP_CLKRST_DRES_XTAL32K 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_S 22
/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
* need_des
*/
#define LP_CLKRST_DGM_XTAL32K 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_S 25
/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_CLKRST_DBUF_XTAL32K (BIT(28))
#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U
#define LP_CLKRST_DBUF_XTAL32K_S 28
/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
* need_des
*/
#define LP_CLKRST_DAC_XTAL32K 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_S 29
/** LP_CLKRST_DATE_REG register
* need_des
*/
#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 35676304;
* need_des
*/
#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_S 0
/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CLK_EN (BIT(31))
#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
#define LP_CLKRST_CLK_EN_V 0x00000001U
#define LP_CLKRST_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/lp_clkrst_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_clk_conf register
* need_des
*/
typedef union {
struct {
/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
* need_des
*/
uint32_t slow_clk_sel:2;
/** fast_clk_sel : R/W; bitpos: [2]; default: 1;
* need_des
*/
uint32_t fast_clk_sel:1;
/** lp_peri_div_num : R/W; bitpos: [10:3]; default: 0;
* need_des
*/
uint32_t lp_peri_div_num:8;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_clkrst_lp_clk_conf_reg_t;
/** Type of lp_clk_po_en register
* need_des
*/
typedef union {
struct {
/** aon_slow_oen : R/W; bitpos: [0]; default: 1;
* need_des
*/
uint32_t aon_slow_oen:1;
/** aon_fast_oen : R/W; bitpos: [1]; default: 1;
* need_des
*/
uint32_t aon_fast_oen:1;
/** sosc_oen : R/W; bitpos: [2]; default: 1;
* need_des
*/
uint32_t sosc_oen:1;
/** fosc_oen : R/W; bitpos: [3]; default: 1;
* need_des
*/
uint32_t fosc_oen:1;
/** osc32k_oen : R/W; bitpos: [4]; default: 1;
* need_des
*/
uint32_t osc32k_oen:1;
/** xtal32k_oen : R/W; bitpos: [5]; default: 1;
* need_des
*/
uint32_t xtal32k_oen:1;
/** core_efuse_oen : R/W; bitpos: [6]; default: 1;
* need_des
*/
uint32_t core_efuse_oen:1;
/** slow_oen : R/W; bitpos: [7]; default: 1;
* need_des
*/
uint32_t slow_oen:1;
/** fast_oen : R/W; bitpos: [8]; default: 1;
* need_des
*/
uint32_t fast_oen:1;
/** rng_oen : R/W; bitpos: [9]; default: 1;
* need_des
*/
uint32_t rng_oen:1;
/** lpbus_oen : R/W; bitpos: [10]; default: 1;
* need_des
*/
uint32_t lpbus_oen:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_clkrst_lp_clk_po_en_reg_t;
/** Type of lp_clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** fast_ori_gate : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t fast_ori_gate:1;
};
uint32_t val;
} lp_clkrst_lp_clk_en_reg_t;
/** Type of lp_rst_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t aon_efuse_core_reset_en:1;
/** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_timer_reset_en:1;
/** wdt_reset_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t wdt_reset_en:1;
/** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_peri_reset_en:1;
};
uint32_t val;
} lp_clkrst_lp_rst_en_reg_t;
/** Type of reset_cause register
* need_des
*/
typedef union {
struct {
/** reset_cause : RO; bitpos: [4:0]; default: 0;
* need_des
*/
uint32_t reset_cause:5;
/** core0_reset_flag : RO; bitpos: [5]; default: 1;
* need_des
*/
uint32_t core0_reset_flag:1;
uint32_t reserved_6:23;
/** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t core0_reset_cause_clr:1;
/** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t core0_reset_flag_set:1;
/** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t core0_reset_flag_clr:1;
};
uint32_t val;
} lp_clkrst_reset_cause_reg_t;
/** Type of cpu_reset register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
* need_des
*/
uint32_t rtc_wdt_cpu_reset_length:3;
/** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t rtc_wdt_cpu_reset_en:1;
/** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
* need_des
*/
uint32_t cpu_stall_wait:5;
/** cpu_stall_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t cpu_stall_en:1;
};
uint32_t val;
} lp_clkrst_cpu_reset_reg_t;
/** Type of fosc_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
uint32_t fosc_dfreq:10;
};
uint32_t val;
} lp_clkrst_fosc_cntl_reg_t;
/** Type of rc32k_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
uint32_t rc32k_dfreq:10;
};
uint32_t val;
} lp_clkrst_rc32k_cntl_reg_t;
/** Type of clk_to_hp register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
* need_des
*/
uint32_t icg_hp_xtal32k:1;
/** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t icg_hp_sosc:1;
/** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t icg_hp_osc32k:1;
/** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t icg_hp_fosc:1;
};
uint32_t val;
} lp_clkrst_clk_to_hp_reg_t;
/** Type of lpmem_force register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lpmem_clk_force_on:1;
};
uint32_t val;
} lp_clkrst_lpmem_force_reg_t;
/** Type of lpperi register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_i2c_clk_sel:1;
/** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_uart_clk_sel:1;
};
uint32_t val;
} lp_clkrst_lpperi_reg_t;
/** Type of xtal32k register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
* need_des
*/
uint32_t dres_xtal32k:3;
/** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
* need_des
*/
uint32_t dgm_xtal32k:3;
/** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t dbuf_xtal32k:1;
/** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
* need_des
*/
uint32_t dac_xtal32k:3;
};
uint32_t val;
} lp_clkrst_xtal32k_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** clkrst_date : R/W; bitpos: [30:0]; default: 35676304;
* need_des
*/
uint32_t clkrst_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_clkrst_date_reg_t;
typedef struct lp_clkrst_dev_t {
volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
volatile lp_clkrst_reset_cause_reg_t reset_cause;
volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
volatile lp_clkrst_lpperi_reg_t lpperi;
volatile lp_clkrst_xtal32k_reg_t xtal32k;
uint32_t reserved_030[243];
volatile lp_clkrst_date_reg_t date;
} lp_clkrst_dev_t;
extern lp_clkrst_dev_t LP_CLKRST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/lp_gpio_sig_map.h Normal file
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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_LP_GPIO_SIG_MAP_H_
#define _SOC_LP_GPIO_SIG_MAP_H_
#define LP_I2C_SCL_PAD_IN_IDX 0
#define LP_I2C_SCL_PAD_OUT_IDX 0
#define LP_I2C_SDA_PAD_IN_IDX 1
#define LP_I2C_SDA_PAD_OUT_IDX 1
#define LP_UART_RXD_PAD_IN_IDX 2
#define LP_UART_TXD_PAD_OUT_IDX 2
#define LP_UART_CTSN_PAD_IN_IDX 3
#define LP_UART_RTSN_PAD_OUT_IDX 3
#define LP_UART_DSRN_PAD_IN_IDX 4
#define LP_UART_DTRN_PAD_OUT_IDX 4
#define LP_SPI_CK_PAD_IN_IDX 5
#define LP_SPI_CK_PAD_OUT_IDX 5
#define LP_SPI_CS_PAD_IN_IDX 6
#define LP_SPI_CS_PAD_OUT_IDX 6
#define LP_SPI_D_PAD_IN_IDX 7
#define LP_SPI_D_PAD_OUT_IDX 7
#define LP_SPI_Q_PAD_IN_IDX 8
#define LP_SPI_Q_PAD_OUT_IDX 8
#define LP_I2S_I_BCK_PAD_IN_IDX 9
#define LP_I2S_I_BCK_PAD_OUT_IDX 9
#define LP_I2S_I_SD_PAD_IN_IDX 10
#define LP_I2S_O_SD_PAD_OUT_IDX 10
#define LP_I2S_I_WS_PAD_IN_IDX 11
#define LP_I2S_I_WS_PAD_OUT_IDX 11
#define LP_I2S_O_BCK_PAD_IN_IDX 12
#define LP_I2S_O_BCK_PAD_OUT_IDX 12
#define LP_I2S_O_WS_PAD_IN_IDX 13
#define LP_I2S_O_WS_PAD_OUT_IDX 13
#define LP_PROBE_TOP_OUT0_IDX 14
#define LP_PROBE_TOP_OUT1_IDX 15
#define LP_PROBE_TOP_OUT2_IDX 16
#define LP_PROBE_TOP_OUT3_IDX 17
#define LP_PROBE_TOP_OUT4_IDX 18
#define LP_PROBE_TOP_OUT5_IDX 19
#define LP_PROBE_TOP_OUT6_IDX 20
#define LP_PROBE_TOP_OUT7_IDX 21
#define LP_PROBE_TOP_OUT8_IDX 22
#define LP_PROBE_TOP_OUT9_IDX 23
#define LP_PROBE_TOP_OUT10_IDX 24
#define LP_PROBE_TOP_OUT11_IDX 25
#define LP_PROBE_TOP_OUT12_IDX 26
#define LP_PROBE_TOP_OUT13_IDX 27
#define LP_PROBE_TOP_OUT14_IDX 28
#define LP_PROBE_TOP_OUT15_IDX 29
#define PROBE_CHAIN_CLK_PAD_OUT_IDX 30
#define GPIO_MAP_DATE_IDX 0x230323
#endif /* _SOC_LP_GPIO_SIG_MAP_H_ */

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_I2C_ANA_MST_I2C0_CTRL_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0)
/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S)
#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CTRL_S 0
/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25))
#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S)
#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U
#define LP_I2C_ANA_MST_I2C0_BUSY_S 25
/** LP_I2C_ANA_MST_I2C0_CONF_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4)
/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S)
#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CONF_S 0
/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7;
* reserved
*/
#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S)
#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_STATUS_S 24
/** LP_I2C_ANA_MST_I2C0_DATA_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8)
/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S)
#define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_RDATA_S 0
/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S)
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8
/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1;
* need des
*/
#define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11))
#define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S)
#define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U
#define LP_I2C_ANA_MST_I2C_MST_SEL_S 11
/** LP_I2C_ANA_MST_ANA_CONF1_REG register
* need_des
*/
#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc)
/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU
#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S)
#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU
#define LP_I2C_ANA_MST_ANA_CONF1_S 0
/** LP_I2C_ANA_MST_NOUSE_REG register
* need_des
*/
#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10)
/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S)
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0
/** LP_I2C_ANA_MST_DEVICE_EN_REG register
* need_des
*/
#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14)
/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S)
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0
/** LP_I2C_ANA_MST_DATE_REG register
* need_des
*/
#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc)
/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU
#define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S)
#define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU
#define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0
/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28))
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S)
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of i2c0_ctrl register
* need_des
*/
typedef union {
struct {
/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
* need_des
*/
uint32_t i2c0_ctrl:25;
/** i2c0_busy : RO; bitpos: [25]; default: 0;
* need_des
*/
uint32_t i2c0_busy:1;
uint32_t reserved_26:6;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_ctrl_reg_t;
/** Type of i2c0_conf register
* need_des
*/
typedef union {
struct {
/** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
uint32_t i2c0_conf:24;
/** i2c0_status : RO; bitpos: [31:24]; default: 7;
* reserved
*/
uint32_t i2c0_status:8;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_conf_reg_t;
/** Type of i2c0_data register
* need_des
*/
typedef union {
struct {
/** i2c0_rdata : RO; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t i2c0_rdata:8;
/** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1;
* need_des
*/
uint32_t i2c0_clk_sel:3;
/** i2c_mst_sel : R/W; bitpos: [11]; default: 1;
* need des
*/
uint32_t i2c_mst_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_data_reg_t;
/** Type of ana_conf1 register
* need_des
*/
typedef union {
struct {
/** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
uint32_t ana_conf1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} lp_i2c_ana_mst_ana_conf1_reg_t;
/** Type of nouse register
* need_des
*/
typedef union {
struct {
/** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t i2c_mst_nouse:32;
};
uint32_t val;
} lp_i2c_ana_mst_nouse_reg_t;
/** Type of device_en register
* need_des
*/
typedef union {
struct {
/** i2c_device_en : R/W; bitpos: [11:0]; default: 0;
* need_des
*/
uint32_t i2c_device_en:12;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2c_ana_mst_device_en_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873;
* need_des
*/
uint32_t i2c_mat_date:28;
/** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t i2c_mat_clk_en:1;
uint32_t reserved_29:3;
};
uint32_t val;
} lp_i2c_ana_mst_date_reg_t;
typedef struct lp_i2c_ana_mst_dev_t {
volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data;
volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1;
volatile lp_i2c_ana_mst_nouse_reg_t nouse;
volatile lp_i2c_ana_mst_device_en_reg_t device_en;
uint32_t reserved_018[249];
volatile lp_i2c_ana_mst_date_reg_t date;
} lp_i2c_ana_mst_dev_t;
extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of out_data register
* need des
*/
typedef union {
struct {
/** out_data : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t out_data:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_reg_t;
/** Type of out_data_w1ts register
* need des
*/
typedef union {
struct {
/** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t out_data_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_w1ts_reg_t;
/** Type of out_data_w1tc register
* need des
*/
typedef union {
struct {
/** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t out_data_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_w1tc_reg_t;
/** Type of out_enable register
* need des
*/
typedef union {
struct {
/** enable : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t enable:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_reg_t;
/** Type of out_enable_w1ts register
* need des
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t enable_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_w1ts_reg_t;
/** Type of out_enable_w1tc register
* need des
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t enable_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_w1tc_reg_t;
/** Type of status register
* need des
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t status_interrupt:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_reg_t;
/** Type of status_w1ts register
* need des
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t status_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_w1ts_reg_t;
/** Type of status_w1tc register
* need des
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t status_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_w1tc_reg_t;
/** Type of in register
* need des
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [7:0]; default: 0;
* need des
*/
uint32_t in_data_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_in_reg_t;
/** Type of pin register
* need des
*/
typedef union {
struct {
/** sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t sync_bypass:2;
/** pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t pad_driver:1;
/** edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t int_type:3;
/** wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t wakeup_enable:1;
/** filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin_reg_t;
/** Type of gpio register
* need des
*/
typedef union {
struct {
/** mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t mcu_oe:1;
/** slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t slp_sel:1;
/** mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t mcu_wpd:1;
/** mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t mcu_wpu:1;
/** mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t mcu_ie:1;
/** mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t mcu_drv:2;
/** fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t fun_wpd:1;
/** fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t fun_wpu:1;
/** fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t fun_ie:1;
/** fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t fun_drv:2;
/** mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio_reg_t;
/** Type of status_interrupt register
* need des
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
* need des
*/
uint32_t status_interrupt_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_interrupt_reg_t;
/** Type of debug_sel0 register
* need des
*/
typedef union {
struct {
/** debug_sel0 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t debug_sel0:7;
/** debug_sel1 : R/W; bitpos: [13:7]; default: 0;
* need des
*/
uint32_t debug_sel1:7;
/** debug_sel2 : R/W; bitpos: [20:14]; default: 0;
* need des
*/
uint32_t debug_sel2:7;
/** debug_sel3 : R/W; bitpos: [27:21]; default: 0;
* need des
*/
uint32_t debug_sel3:7;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_io_debug_sel0_reg_t;
/** Type of debug_sel1 register
* need des
*/
typedef union {
struct {
/** debug_sel4 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t debug_sel4:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_io_debug_sel1_reg_t;
/** Type of lpi2c register
* need des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1;
* need des
*/
uint32_t lp_i2c_sda_ie:1;
/** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1;
* need des
*/
uint32_t lp_i2c_scl_ie:1;
};
uint32_t val;
} lp_io_lpi2c_reg_t;
/** Type of date register
* need des
*/
typedef union {
struct {
/** lp_io_date : R/W; bitpos: [30:0]; default: 35660032;
* need des
*/
uint32_t lp_io_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_io_date_reg_t;
typedef struct lp_io_dev_t {
volatile lp_io_out_data_reg_t out_data;
volatile lp_io_out_data_w1ts_reg_t out_data_w1ts;
volatile lp_io_out_data_w1tc_reg_t out_data_w1tc;
volatile lp_io_out_enable_reg_t out_enable;
volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts;
volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc;
volatile lp_io_status_reg_t status;
volatile lp_io_status_w1ts_reg_t status_w1ts;
volatile lp_io_status_w1tc_reg_t status_w1tc;
volatile lp_io_in_reg_t in;
volatile lp_io_pin_reg_t pin[8];
volatile lp_io_gpio_reg_t gpio[8];
volatile lp_io_status_interrupt_reg_t status_interrupt;
volatile lp_io_debug_sel0_reg_t debug_sel0;
volatile lp_io_debug_sel1_reg_t debug_sel1;
volatile lp_io_lpi2c_reg_t lpi2c;
uint32_t reserved_078[225];
volatile lp_io_date_reg_t date;
} lp_io_dev_t;
extern lp_io_dev_t LP_IO;
#ifndef __cplusplus
_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TEE_M0_MODE_CTRL_REG register
* Tee mode control register
*/
#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define LP_TEE_M0_MODE 0x00000003U
#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
#define LP_TEE_M0_MODE_V 0x00000003U
#define LP_TEE_M0_MODE_S 0
/** LP_TEE_CLOCK_GATE_REG register
* Clock gating register
*/
#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4)
/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_TEE_CLK_EN (BIT(0))
#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
#define LP_TEE_CLK_EN_V 0x00000001U
#define LP_TEE_CLK_EN_S 0
/** LP_TEE_FORCE_ACC_HP_REG register
* need_des
*/
#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0))
#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U
#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0
/** LP_TEE_DATE_REG register
* Version register
*/
#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35672688;
* reg_tee_date
*/
#define LP_TEE_DATE_REG 0x0FFFFFFFU
#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S)
#define LP_TEE_DATE_REG_V 0x0FFFFFFFU
#define LP_TEE_DATE_REG_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 3;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m0_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_tee_m0_mode_ctrl_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_clock_gate_reg_t;
/** Group: configure_register */
/** Type of force_acc_hp register
* need_des
*/
typedef union {
struct {
/** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t force_acc_hpmem_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_force_acc_hp_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date_reg : R/W; bitpos: [27:0]; default: 35672688;
* reg_tee_date
*/
uint32_t date_reg:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_tee_date_reg_t;
typedef struct lp_tee_dev_t {
volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
volatile lp_tee_clock_gate_reg_t clock_gate;
uint32_t reserved_008[34];
volatile lp_tee_force_acc_hp_reg_t force_acc_hp;
uint32_t reserved_094[26];
volatile lp_tee_date_reg_t date;
} lp_tee_dev_t;
extern lp_tee_dev_t LP_TEE;
#ifndef __cplusplus
_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TIMER_TAR0_LOW_REG register
* need_des
*/
#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0
/** LP_TIMER_TAR0_HIGH_REG register
* need_des
*/
#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31
/** LP_TIMER_TAR1_LOW_REG register
* need_des
*/
#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8)
/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0
/** LP_TIMER_TAR1_HIGH_REG register
* need_des
*/
#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31
/** LP_TIMER_UPDATE_REG register
* need_des
*/
#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28))
#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_UPDATE_S 28
/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29
/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30
/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31
/** LP_TIMER_MAIN_BUF0_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0
/** LP_TIMER_MAIN_BUF0_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
/** LP_TIMER_MAIN_BUF1_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0
/** LP_TIMER_MAIN_BUF1_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
/** LP_TIMER_MAIN_OVERFLOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31))
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S)
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31
/** LP_TIMER_INT_RAW_REG register
* need_des
*/
#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_RAW (BIT(30))
#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U
#define LP_TIMER_OVERFLOW_RAW_S 30
/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31
/** LP_TIMER_INT_ST_REG register
* need_des
*/
#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ST (BIT(30))
#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
#define LP_TIMER_OVERFLOW_ST_V 0x00000001U
#define LP_TIMER_OVERFLOW_ST_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31
/** LP_TIMER_INT_ENA_REG register
* need_des
*/
#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30)
/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ENA (BIT(30))
#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U
#define LP_TIMER_OVERFLOW_ENA_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31
/** LP_TIMER_INT_CLR_REG register
* need_des
*/
#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34)
/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_CLR (BIT(30))
#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U
#define LP_TIMER_OVERFLOW_CLR_S 30
/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31
/** LP_TIMER_LP_INT_RAW_REG register
* need_des
*/
#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31
/** LP_TIMER_LP_INT_ST_REG register
* need_des
*/
#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31
/** LP_TIMER_LP_INT_ENA_REG register
* need_des
*/
#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31
/** LP_TIMER_LP_INT_CLR_REG register
* need_des
*/
#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31
/** LP_TIMER_DATE_REG register
* need_des
*/
#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc)
/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
#define LP_TIMER_DATE 0x7FFFFFFFU
#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
#define LP_TIMER_DATE_V 0x7FFFFFFFU
#define LP_TIMER_DATE_S 0
/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_CLK_EN (BIT(31))
#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S)
#define LP_TIMER_CLK_EN_V 0x00000001U
#define LP_TIMER_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/lp_timer_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of tar0_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low0:32;
};
uint32_t val;
} lp_timer_tar0_low_reg_t;
/** Type of tar0_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high0:16;
uint32_t reserved_16:15;
/** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en0:1;
};
uint32_t val;
} lp_timer_tar0_high_reg_t;
/** Type of tar1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low1:32;
};
uint32_t val;
} lp_timer_tar1_low_reg_t;
/** Type of tar1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high1:16;
uint32_t reserved_16:15;
/** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en1:1;
};
uint32_t val;
} lp_timer_tar1_high_reg_t;
/** Type of update register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** main_timer_update : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t main_timer_update:1;
/** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t main_timer_xtal_off:1;
/** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_sys_stall:1;
/** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_sys_rst:1;
};
uint32_t val;
} lp_timer_update_reg_t;
/** Type of main_buf0_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_low:32;
};
uint32_t val;
} lp_timer_main_buf0_low_reg_t;
/** Type of main_buf0_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf0_high_reg_t;
/** Type of main_buf1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_low:32;
};
uint32_t val;
} lp_timer_main_buf1_low_reg_t;
/** Type of main_buf1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf1_high_reg_t;
/** Type of main_overflow register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_alarm_load:1;
};
uint32_t val;
} lp_timer_main_overflow_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_raw:1;
/** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_raw:1;
};
uint32_t val;
} lp_timer_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_st:1;
/** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_st:1;
};
uint32_t val;
} lp_timer_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_ena:1;
/** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_ena:1;
};
uint32_t val;
} lp_timer_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_clr:1;
/** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_clr:1;
};
uint32_t val;
} lp_timer_int_clr_reg_t;
/** Type of lp_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_raw:1;
/** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_raw:1;
};
uint32_t val;
} lp_timer_lp_int_raw_reg_t;
/** Type of lp_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_st:1;
/** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_st:1;
};
uint32_t val;
} lp_timer_lp_int_st_reg_t;
/** Type of lp_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_ena:1;
/** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_ena:1;
};
uint32_t val;
} lp_timer_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_clr:1;
/** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_clr:1;
};
uint32_t val;
} lp_timer_lp_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_timer_date_reg_t;
typedef struct lp_timer_dev_t {
volatile lp_timer_tar0_low_reg_t tar0_low;
volatile lp_timer_tar0_high_reg_t tar0_high;
volatile lp_timer_tar1_low_reg_t tar1_low;
volatile lp_timer_tar1_high_reg_t tar1_high;
volatile lp_timer_update_reg_t update;
volatile lp_timer_main_buf0_low_reg_t main_buf0_low;
volatile lp_timer_main_buf0_high_reg_t main_buf0_high;
volatile lp_timer_main_buf1_low_reg_t main_buf1_low;
volatile lp_timer_main_buf1_high_reg_t main_buf1_high;
volatile lp_timer_main_overflow_reg_t main_overflow;
volatile lp_timer_int_raw_reg_t int_raw;
volatile lp_timer_int_st_reg_t int_st;
volatile lp_timer_int_ena_reg_t int_ena;
volatile lp_timer_int_clr_reg_t int_clr;
volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
volatile lp_timer_lp_int_st_reg_t lp_int_st;
volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_048[237];
volatile lp_timer_date_reg_t date;
} lp_timer_dev_t;
extern lp_timer_dev_t LP_TIMER;
#ifndef __cplusplus
_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/lp_wdt_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// TODO: IDF-5730 (better to rename and move to wdt_types.h?)
/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
#define RTC_WDT_RESET_LENGTH_100_NS 0
#define RTC_WDT_RESET_LENGTH_200_NS 1
#define RTC_WDT_RESET_LENGTH_300_NS 2
#define RTC_WDT_RESET_LENGTH_400_NS 3
#define RTC_WDT_RESET_LENGTH_500_NS 4
#define RTC_WDT_RESET_LENGTH_800_NS 5
#define RTC_WDT_RESET_LENGTH_1600_NS 6
#define RTC_WDT_RESET_LENGTH_3200_NS 7
#define LP_WDT_RTC_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
/* LP_WDT_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: .*/
#define LP_WDT_WDT_EN (BIT(31))
#define LP_WDT_WDT_EN_M (BIT(31))
#define LP_WDT_WDT_EN_V 0x1
#define LP_WDT_WDT_EN_S 31
/* LP_WDT_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
reset stage en.*/
#define LP_WDT_WDT_STG0 0x00000007
#define LP_WDT_WDT_STG0_M ((LP_WDT_WDT_STG0_V)<<(LP_WDT_WDT_STG0_S))
#define LP_WDT_WDT_STG0_V 0x7
#define LP_WDT_WDT_STG0_S 28
/* LP_WDT_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
reset stage en.*/
#define LP_WDT_WDT_STG1 0x00000007
#define LP_WDT_WDT_STG1_M ((LP_WDT_WDT_STG1_V)<<(LP_WDT_WDT_STG1_S))
#define LP_WDT_WDT_STG1_V 0x7
#define LP_WDT_WDT_STG1_S 25
/* LP_WDT_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
reset stage en.*/
#define LP_WDT_WDT_STG2 0x00000007
#define LP_WDT_WDT_STG2_M ((LP_WDT_WDT_STG2_V)<<(LP_WDT_WDT_STG2_S))
#define LP_WDT_WDT_STG2_V 0x7
#define LP_WDT_WDT_STG2_S 22
/* LP_WDT_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
/*description: 1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC
reset stage en.*/
#define LP_WDT_WDT_STG3 0x00000007
#define LP_WDT_WDT_STG3_M ((LP_WDT_WDT_STG3_V)<<(LP_WDT_WDT_STG3_S))
#define LP_WDT_WDT_STG3_V 0x7
#define LP_WDT_WDT_STG3_S 19
/* LP_WDT_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
/*description: CPU reset counter length.*/
#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007
#define LP_WDT_WDT_CPU_RESET_LENGTH_M ((LP_WDT_WDT_CPU_RESET_LENGTH_V)<<(LP_WDT_WDT_CPU_RESET_LENGTH_S))
#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x7
#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
/* LP_WDT_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
/*description: system reset counter length.*/
#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007
#define LP_WDT_WDT_SYS_RESET_LENGTH_M ((LP_WDT_WDT_SYS_RESET_LENGTH_V)<<(LP_WDT_WDT_SYS_RESET_LENGTH_S))
#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x7
#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
/* LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
/*description: enable WDT in flash boot.*/
#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (BIT(12))
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x1
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12
/* LP_WDT_WDT_PAUSE_IN_SLP : R/W ;bitpos:[11] ;default: 1'd1 ; */
/*description: pause WDT in sleep.*/
#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(11))
#define LP_WDT_WDT_PAUSE_IN_SLP_M (BIT(11))
#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x1
#define LP_WDT_WDT_PAUSE_IN_SLP_S 11
/* LP_WDT_WDT_CHIP_RESET_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: wdt reset whole chip enable.*/
#define LP_WDT_WDT_CHIP_RESET_EN (BIT(10))
#define LP_WDT_WDT_CHIP_RESET_EN_M (BIT(10))
#define LP_WDT_WDT_CHIP_RESET_EN_V 0x1
#define LP_WDT_WDT_CHIP_RESET_EN_S 10
/* LP_WDT_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[9:2] ;default: 8'd20 ; */
/*description: chip reset siginal pulse width.*/
#define LP_WDT_WDT_CHIP_RESET_WIDTH 0x000000FF
#define LP_WDT_WDT_CHIP_RESET_WIDTH_M ((LP_WDT_WDT_CHIP_RESET_WIDTH_V)<<(LP_WDT_WDT_CHIP_RESET_WIDTH_S))
#define LP_WDT_WDT_CHIP_RESET_WIDTH_V 0xFF
#define LP_WDT_WDT_CHIP_RESET_WIDTH_S 2
#define LP_WDT_RTC_WDTCPURST_REG (DR_REG_LP_WDT_BASE + 0x4)
/* LP_WDT_WDT_CORE0CPU_RESET_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*description: enable WDT reset CORE0 CPU.*/
#define LP_WDT_WDT_CORE0CPU_RESET_EN (BIT(31))
#define LP_WDT_WDT_CORE0CPU_RESET_EN_M (BIT(31))
#define LP_WDT_WDT_CORE0CPU_RESET_EN_V 0x1
#define LP_WDT_WDT_CORE0CPU_RESET_EN_S 31
/* LP_WDT_WDT_CORE1CPU_RESET_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
/*description: enable WDT reset CORE1 CPU.*/
#define LP_WDT_WDT_CORE1CPU_RESET_EN (BIT(30))
#define LP_WDT_WDT_CORE1CPU_RESET_EN_M (BIT(30))
#define LP_WDT_WDT_CORE1CPU_RESET_EN_V 0x1
#define LP_WDT_WDT_CORE1CPU_RESET_EN_S 30
/* LP_WDT_WDT_CORE2CPU_RESET_EN : R/W ;bitpos:[29] ;default: 1'd0 ; */
/*description: enable WDT reset CORE2 CPU.*/
#define LP_WDT_WDT_CORE2CPU_RESET_EN (BIT(29))
#define LP_WDT_WDT_CORE2CPU_RESET_EN_M (BIT(29))
#define LP_WDT_WDT_CORE2CPU_RESET_EN_V 0x1
#define LP_WDT_WDT_CORE2CPU_RESET_EN_S 29
/* LP_WDT_WDT_CORE3CPU_RESET_EN : R/W ;bitpos:[28] ;default: 1'd0 ; */
/*description: enable WDT reset CORE3 CPU.*/
#define LP_WDT_WDT_CORE3CPU_RESET_EN (BIT(28))
#define LP_WDT_WDT_CORE3CPU_RESET_EN_M (BIT(28))
#define LP_WDT_WDT_CORE3CPU_RESET_EN_V 0x1
#define LP_WDT_WDT_CORE3CPU_RESET_EN_S 28
/* LP_WDT_WDT_LP_CPU_RESET_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
/*description: enable WDT reset LP CPU.*/
#define LP_WDT_WDT_LP_CPU_RESET_EN (BIT(27))
#define LP_WDT_WDT_LP_CPU_RESET_EN_M (BIT(27))
#define LP_WDT_WDT_LP_CPU_RESET_EN_V 0x1
#define LP_WDT_WDT_LP_CPU_RESET_EN_S 27
/* LP_WDT_WDT_LP_PERI_RESET_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */
/*description: enable WDT reset LP PERI.*/
#define LP_WDT_WDT_LP_PERI_RESET_EN (BIT(26))
#define LP_WDT_WDT_LP_PERI_RESET_EN_M (BIT(26))
#define LP_WDT_WDT_LP_PERI_RESET_EN_V 0x1
#define LP_WDT_WDT_LP_PERI_RESET_EN_S 26
#define LP_WDT_RTC_WDTCONFIG1_REG (DR_REG_LP_WDT_BASE + 0x8)
/* LP_WDT_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
/*description: .*/
#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFF
#define LP_WDT_WDT_STG0_HOLD_M ((LP_WDT_WDT_STG0_HOLD_V)<<(LP_WDT_WDT_STG0_HOLD_S))
#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFF
#define LP_WDT_WDT_STG0_HOLD_S 0
#define LP_WDT_RTC_WDTCONFIG2_REG (DR_REG_LP_WDT_BASE + 0xC)
/* LP_WDT_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
/*description: .*/
#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFF
#define LP_WDT_WDT_STG1_HOLD_M ((LP_WDT_WDT_STG1_HOLD_V)<<(LP_WDT_WDT_STG1_HOLD_S))
#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFF
#define LP_WDT_WDT_STG1_HOLD_S 0
#define LP_WDT_RTC_WDTCONFIG3_REG (DR_REG_LP_WDT_BASE + 0x10)
/* LP_WDT_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
/*description: .*/
#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFF
#define LP_WDT_WDT_STG2_HOLD_M ((LP_WDT_WDT_STG2_HOLD_V)<<(LP_WDT_WDT_STG2_HOLD_S))
#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFF
#define LP_WDT_WDT_STG2_HOLD_S 0
#define LP_WDT_RTC_WDTCONFIG4_REG (DR_REG_LP_WDT_BASE + 0x14)
/* LP_WDT_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
/*description: .*/
#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFF
#define LP_WDT_WDT_STG3_HOLD_M ((LP_WDT_WDT_STG3_HOLD_V)<<(LP_WDT_WDT_STG3_HOLD_S))
#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFF
#define LP_WDT_WDT_STG3_HOLD_S 0
#define LP_WDT_RTC_WDTFEED_REG (DR_REG_LP_WDT_BASE + 0x18)
/* LP_WDT_RTC_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
/*description: .*/
#define LP_WDT_RTC_WDT_FEED (BIT(31))
#define LP_WDT_RTC_WDT_FEED_M (BIT(31))
#define LP_WDT_RTC_WDT_FEED_V 0x1
#define LP_WDT_RTC_WDT_FEED_S 31
#define LP_WDT_RTC_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x1C)
/* LP_WDT_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
/*description: .*/
#define LP_WDT_WDT_WKEY 0xFFFFFFFF
#define LP_WDT_WDT_WKEY_M ((LP_WDT_WDT_WKEY_V)<<(LP_WDT_WDT_WKEY_S))
#define LP_WDT_WDT_WKEY_V 0xFFFFFFFF
#define LP_WDT_WDT_WKEY_S 0
#define LP_WDT_RTC_SWD_CONF_REG (DR_REG_LP_WDT_BASE + 0x20)
/* LP_WDT_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: automatically feed swd when int comes.*/
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(31))
#define LP_WDT_SWD_AUTO_FEED_EN_M (BIT(31))
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x1
#define LP_WDT_SWD_AUTO_FEED_EN_S 31
/* LP_WDT_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b1 ; */
/*description: disabel SWD.*/
#define LP_WDT_SWD_DISABLE (BIT(30))
#define LP_WDT_SWD_DISABLE_M (BIT(30))
#define LP_WDT_SWD_DISABLE_V 0x1
#define LP_WDT_SWD_DISABLE_S 30
/* LP_WDT_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
/*description: Sw feed swd.*/
#define LP_WDT_SWD_FEED (BIT(29))
#define LP_WDT_SWD_FEED_M (BIT(29))
#define LP_WDT_SWD_FEED_V 0x1
#define LP_WDT_SWD_FEED_S 29
/* LP_WDT_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
/*description: reset swd reset flag.*/
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(28))
#define LP_WDT_SWD_RST_FLAG_CLR_M (BIT(28))
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x1
#define LP_WDT_SWD_RST_FLAG_CLR_S 28
/* LP_WDT_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
/*description: adjust signal width send to swd.*/
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FF
#define LP_WDT_SWD_SIGNAL_WIDTH_M ((LP_WDT_SWD_SIGNAL_WIDTH_V)<<(LP_WDT_SWD_SIGNAL_WIDTH_S))
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x3FF
#define LP_WDT_SWD_SIGNAL_WIDTH_S 18
/* LP_WDT_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: swd interrupt for feeding.*/
#define LP_WDT_SWD_FEED_INT (BIT(1))
#define LP_WDT_SWD_FEED_INT_M (BIT(1))
#define LP_WDT_SWD_FEED_INT_V 0x1
#define LP_WDT_SWD_FEED_INT_S 1
/* LP_WDT_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: swd reset flag.*/
#define LP_WDT_SWD_RESET_FLAG (BIT(0))
#define LP_WDT_SWD_RESET_FLAG_M (BIT(0))
#define LP_WDT_SWD_RESET_FLAG_V 0x1
#define LP_WDT_SWD_RESET_FLAG_S 0
#define LP_WDT_RTC_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x24)
/* LP_WDT_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
/*description: swd write protect.*/
#define LP_WDT_SWD_WKEY 0xFFFFFFFF
#define LP_WDT_SWD_WKEY_M ((LP_WDT_SWD_WKEY_V)<<(LP_WDT_SWD_WKEY_S))
#define LP_WDT_SWD_WKEY_V 0xFFFFFFFF
#define LP_WDT_SWD_WKEY_S 0
#define LP_WDT_WDT_CLK_EN_REG (DR_REG_LP_WDT_BASE + 0x28)
/* LP_WDT_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define LP_WDT_CLK_EN (BIT(0))
#define LP_WDT_CLK_EN_M (BIT(0))
#define LP_WDT_CLK_EN_V 0x1
#define LP_WDT_CLK_EN_S 0
#define LP_WDT_INT_ENA_RTC_W1TS_REG (DR_REG_LP_WDT_BASE + 0x2C)
/* LP_WDT_RTC_SWD_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: enable super watch dog interrupt.*/
#define LP_WDT_RTC_SWD_INT_ENA_W1TS (BIT(1))
#define LP_WDT_RTC_SWD_INT_ENA_W1TS_M (BIT(1))
#define LP_WDT_RTC_SWD_INT_ENA_W1TS_V 0x1
#define LP_WDT_RTC_SWD_INT_ENA_W1TS_S 1
/* LP_WDT_RTC_WDT_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: enable RTC WDT interrupt.*/
#define LP_WDT_RTC_WDT_INT_ENA_W1TS (BIT(0))
#define LP_WDT_RTC_WDT_INT_ENA_W1TS_M (BIT(0))
#define LP_WDT_RTC_WDT_INT_ENA_W1TS_V 0x1
#define LP_WDT_RTC_WDT_INT_ENA_W1TS_S 0
#define LP_WDT_INT_ENA_RTC_W1TC_REG (DR_REG_LP_WDT_BASE + 0x30)
/* LP_WDT_RTC_SWD_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: enable super watch dog interrupt.*/
#define LP_WDT_RTC_SWD_INT_ENA_W1TC (BIT(1))
#define LP_WDT_RTC_SWD_INT_ENA_W1TC_M (BIT(1))
#define LP_WDT_RTC_SWD_INT_ENA_W1TC_V 0x1
#define LP_WDT_RTC_SWD_INT_ENA_W1TC_S 1
/* LP_WDT_RTC_WDT_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: enable RTC WDT interrupt.*/
#define LP_WDT_RTC_WDT_INT_ENA_W1TC (BIT(0))
#define LP_WDT_RTC_WDT_INT_ENA_W1TC_M (BIT(0))
#define LP_WDT_RTC_WDT_INT_ENA_W1TC_V 0x1
#define LP_WDT_RTC_WDT_INT_ENA_W1TC_S 0
#define LP_WDT_INT_ENA_RTC_REG (DR_REG_LP_WDT_BASE + 0x34)
/* LP_WDT_RTC_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: enable xtal32k_dead interrupt.*/
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA (BIT(2))
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_M (BIT(2))
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_V 0x1
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ENA_S 2
/* LP_WDT_RTC_SWD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: enable super watch dog interrupt.*/
#define LP_WDT_RTC_SWD_INT_ENA (BIT(1))
#define LP_WDT_RTC_SWD_INT_ENA_M (BIT(1))
#define LP_WDT_RTC_SWD_INT_ENA_V 0x1
#define LP_WDT_RTC_SWD_INT_ENA_S 1
/* LP_WDT_RTC_WDT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: enable RTC WDT interrupt.*/
#define LP_WDT_RTC_WDT_INT_ENA (BIT(0))
#define LP_WDT_RTC_WDT_INT_ENA_M (BIT(0))
#define LP_WDT_RTC_WDT_INT_ENA_V 0x1
#define LP_WDT_RTC_WDT_INT_ENA_S 0
#define LP_WDT_INT_RAW_RTC_REG (DR_REG_LP_WDT_BASE + 0x38)
/* LP_WDT_RTC_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: xtal32k dead detection interrupt raw.*/
#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW (BIT(2))
#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_M (BIT(2))
#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_V 0x1
#define LP_WDT_RTC_XTAL32K_DEAD_INT_RAW_S 2
/* LP_WDT_RTC_SWD_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: super watch dog interrupt raw.*/
#define LP_WDT_RTC_SWD_INT_RAW (BIT(1))
#define LP_WDT_RTC_SWD_INT_RAW_M (BIT(1))
#define LP_WDT_RTC_SWD_INT_RAW_V 0x1
#define LP_WDT_RTC_SWD_INT_RAW_S 1
/* LP_WDT_RTC_WDT_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: RTC WDT interrupt raw.*/
#define LP_WDT_RTC_WDT_INT_RAW (BIT(0))
#define LP_WDT_RTC_WDT_INT_RAW_M (BIT(0))
#define LP_WDT_RTC_WDT_INT_RAW_V 0x1
#define LP_WDT_RTC_WDT_INT_RAW_S 0
#define LP_WDT_INT_SWD_ST_RTC_REG (DR_REG_LP_WDT_BASE + 0x3C)
/* LP_WDT_RTC_XTAL32K_DEAD_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: xtal32k dead detection interrupt state.*/
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST (BIT(2))
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_M (BIT(2))
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_V 0x1
#define LP_WDT_RTC_XTAL32K_DEAD_INT_ST_S 2
/* LP_WDT_RTC_SWD_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: super watch dog interrupt state.*/
#define LP_WDT_RTC_SWD_INT_ST (BIT(1))
#define LP_WDT_RTC_SWD_INT_ST_M (BIT(1))
#define LP_WDT_RTC_SWD_INT_ST_V 0x1
#define LP_WDT_RTC_SWD_INT_ST_S 1
/* LP_WDT_RTC_WDT_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: watch dog interrupt state.*/
#define LP_WDT_RTC_WDT_INT_ST (BIT(0))
#define LP_WDT_RTC_WDT_INT_ST_M (BIT(0))
#define LP_WDT_RTC_WDT_INT_ST_V 0x1
#define LP_WDT_RTC_WDT_INT_ST_S 0
#define LP_WDT_INT_CLR_RTC_REG (DR_REG_LP_WDT_BASE + 0x40)
/* LP_WDT_RTC_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: Clear RTC WDT interrupt state.*/
#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR (BIT(2))
#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_M (BIT(2))
#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_V 0x1
#define LP_WDT_RTC_XTAL32K_DEAD_INT_CLR_S 2
/* LP_WDT_RTC_SWD_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: Clear super watch dog interrupt state.*/
#define LP_WDT_RTC_SWD_INT_CLR (BIT(1))
#define LP_WDT_RTC_SWD_INT_CLR_M (BIT(1))
#define LP_WDT_RTC_SWD_INT_CLR_V 0x1
#define LP_WDT_RTC_SWD_INT_CLR_S 1
/* LP_WDT_RTC_WDT_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Clear RTC WDT interrupt state.*/
#define LP_WDT_RTC_WDT_INT_CLR (BIT(0))
#define LP_WDT_RTC_WDT_INT_CLR_M (BIT(0))
#define LP_WDT_RTC_WDT_INT_CLR_V 0x1
#define LP_WDT_RTC_WDT_INT_CLR_S 0
#define LP_WDT_RTC_EXT_XTL_CONF_REG (DR_REG_LP_WDT_BASE + 0x44)
/* LP_WDT_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define LP_WDT_XTL_EXT_CTR_EN (BIT(31))
#define LP_WDT_XTL_EXT_CTR_EN_M (BIT(31))
#define LP_WDT_XTL_EXT_CTR_EN_V 0x1
#define LP_WDT_XTL_EXT_CTR_EN_S 31
/* LP_WDT_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: 0: power down XTAL at high level; 1: power down XTAL at low level.*/
#define LP_WDT_XTL_EXT_CTR_LV (BIT(30))
#define LP_WDT_XTL_EXT_CTR_LV_M (BIT(30))
#define LP_WDT_XTL_EXT_CTR_LV_V 0x1
#define LP_WDT_XTL_EXT_CTR_LV_S 30
/* LP_WDT_RTC_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: XTAL_32K sel. ; 0: external XTAL_32K; 1: CLK from RTC pad X32P_C.*/
#define LP_WDT_RTC_XTAL32K_GPIO_SEL (BIT(23))
#define LP_WDT_RTC_XTAL32K_GPIO_SEL_M (BIT(23))
#define LP_WDT_RTC_XTAL32K_GPIO_SEL_V 0x1
#define LP_WDT_RTC_XTAL32K_GPIO_SEL_S 23
/* LP_WDT_RTC_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
/*description: state of 32k_wdt.*/
#define LP_WDT_RTC_WDT_STATE 0x00000007
#define LP_WDT_RTC_WDT_STATE_M ((LP_WDT_RTC_WDT_STATE_V)<<(LP_WDT_RTC_WDT_STATE_S))
#define LP_WDT_RTC_WDT_STATE_V 0x7
#define LP_WDT_RTC_WDT_STATE_S 20
/* LP_WDT_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
/*description: DAC_XTAL_32K.*/
#define LP_WDT_DAC_XTAL_32K 0x00000007
#define LP_WDT_DAC_XTAL_32K_M ((LP_WDT_DAC_XTAL_32K_V)<<(LP_WDT_DAC_XTAL_32K_S))
#define LP_WDT_DAC_XTAL_32K_V 0x7
#define LP_WDT_DAC_XTAL_32K_S 17
/* LP_WDT_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
/*description: XPD_XTAL_32K.*/
#define LP_WDT_XPD_XTAL_32K (BIT(16))
#define LP_WDT_XPD_XTAL_32K_M (BIT(16))
#define LP_WDT_XPD_XTAL_32K_V 0x1
#define LP_WDT_XPD_XTAL_32K_S 16
/* LP_WDT_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
/*description: DRES_XTAL_32K.*/
#define LP_WDT_DRES_XTAL_32K 0x00000007
#define LP_WDT_DRES_XTAL_32K_M ((LP_WDT_DRES_XTAL_32K_V)<<(LP_WDT_DRES_XTAL_32K_S))
#define LP_WDT_DRES_XTAL_32K_V 0x7
#define LP_WDT_DRES_XTAL_32K_S 13
/* LP_WDT_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
/*description: xtal_32k gm control.*/
#define LP_WDT_DGM_XTAL_32K 0x00000007
#define LP_WDT_DGM_XTAL_32K_M ((LP_WDT_DGM_XTAL_32K_V)<<(LP_WDT_DGM_XTAL_32K_S))
#define LP_WDT_DGM_XTAL_32K_V 0x7
#define LP_WDT_DGM_XTAL_32K_S 10
/* LP_WDT_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: 0: single-end buffer 1: differential buffer.*/
#define LP_WDT_DBUF_XTAL_32K (BIT(9))
#define LP_WDT_DBUF_XTAL_32K_M (BIT(9))
#define LP_WDT_DBUF_XTAL_32K_V 0x1
#define LP_WDT_DBUF_XTAL_32K_S 9
/* LP_WDT_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: apply an internal clock to help xtal 32k to start.*/
#define LP_WDT_ENCKINIT_XTAL_32K (BIT(8))
#define LP_WDT_ENCKINIT_XTAL_32K_M (BIT(8))
#define LP_WDT_ENCKINIT_XTAL_32K_V 0x1
#define LP_WDT_ENCKINIT_XTAL_32K_S 8
/* LP_WDT_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: Xtal 32k xpd control by sw or fsm.*/
#define LP_WDT_XTAL32K_XPD_FORCE (BIT(7))
#define LP_WDT_XTAL32K_XPD_FORCE_M (BIT(7))
#define LP_WDT_XTAL32K_XPD_FORCE_V 0x1
#define LP_WDT_XTAL32K_XPD_FORCE_S 7
/* LP_WDT_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: xtal 32k switch back xtal when xtal is restarted.*/
#define LP_WDT_XTAL32K_AUTO_RETURN (BIT(6))
#define LP_WDT_XTAL32K_AUTO_RETURN_M (BIT(6))
#define LP_WDT_XTAL32K_AUTO_RETURN_V 0x1
#define LP_WDT_XTAL32K_AUTO_RETURN_S 6
/* LP_WDT_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: xtal 32k restart xtal when xtal is dead.*/
#define LP_WDT_XTAL32K_AUTO_RESTART (BIT(5))
#define LP_WDT_XTAL32K_AUTO_RESTART_M (BIT(5))
#define LP_WDT_XTAL32K_AUTO_RESTART_V 0x1
#define LP_WDT_XTAL32K_AUTO_RESTART_S 5
/* LP_WDT_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: xtal 32k switch to back up clock when xtal is dead.*/
#define LP_WDT_XTAL32K_AUTO_BACKUP (BIT(4))
#define LP_WDT_XTAL32K_AUTO_BACKUP_M (BIT(4))
#define LP_WDT_XTAL32K_AUTO_BACKUP_V 0x1
#define LP_WDT_XTAL32K_AUTO_BACKUP_S 4
/* LP_WDT_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: xtal 32k external xtal clock force on.*/
#define LP_WDT_XTAL32K_EXT_CLK_FO (BIT(3))
#define LP_WDT_XTAL32K_EXT_CLK_FO_M (BIT(3))
#define LP_WDT_XTAL32K_EXT_CLK_FO_V 0x1
#define LP_WDT_XTAL32K_EXT_CLK_FO_S 3
/* LP_WDT_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: xtal 32k watch dog sw reset.*/
#define LP_WDT_XTAL32K_WDT_RESET (BIT(2))
#define LP_WDT_XTAL32K_WDT_RESET_M (BIT(2))
#define LP_WDT_XTAL32K_WDT_RESET_V 0x1
#define LP_WDT_XTAL32K_WDT_RESET_S 2
/* LP_WDT_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: xtal 32k watch dog clock force on.*/
#define LP_WDT_XTAL32K_WDT_CLK_FO (BIT(1))
#define LP_WDT_XTAL32K_WDT_CLK_FO_M (BIT(1))
#define LP_WDT_XTAL32K_WDT_CLK_FO_V 0x1
#define LP_WDT_XTAL32K_WDT_CLK_FO_S 1
/* LP_WDT_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: xtal 32k watch dog enable.*/
#define LP_WDT_XTAL32K_WDT_EN (BIT(0))
#define LP_WDT_XTAL32K_WDT_EN_M (BIT(0))
#define LP_WDT_XTAL32K_WDT_EN_V 0x1
#define LP_WDT_XTAL32K_WDT_EN_S 0
#define LP_WDT_RTC_XTAL32K_CLK_FACTOR_REG (DR_REG_LP_WDT_BASE + 0x48)
/* LP_WDT_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: xtal 32k watch dog backup clock factor.*/
#define LP_WDT_XTAL32K_CLK_FACTOR 0xFFFFFFFF
#define LP_WDT_XTAL32K_CLK_FACTOR_M ((LP_WDT_XTAL32K_CLK_FACTOR_V)<<(LP_WDT_XTAL32K_CLK_FACTOR_S))
#define LP_WDT_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF
#define LP_WDT_XTAL32K_CLK_FACTOR_S 0
#define LP_WDT_RTC_XTAL32K_CONF_REG (DR_REG_LP_WDT_BASE + 0x5C)
/* LP_WDT_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
/*description: if restarted xtal32k period is smaller than this, it is regarded as stable.*/
#define LP_WDT_XTAL32K_STABLE_THRES 0x0000000F
#define LP_WDT_XTAL32K_STABLE_THRES_M ((LP_WDT_XTAL32K_STABLE_THRES_V)<<(LP_WDT_XTAL32K_STABLE_THRES_S))
#define LP_WDT_XTAL32K_STABLE_THRES_V 0xF
#define LP_WDT_XTAL32K_STABLE_THRES_S 28
/* LP_WDT_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
/*description: If no clock detected for this amount of time,32k is regarded as dead.*/
#define LP_WDT_XTAL32K_WDT_TIMEOUT 0x000000FF
#define LP_WDT_XTAL32K_WDT_TIMEOUT_M ((LP_WDT_XTAL32K_WDT_TIMEOUT_V)<<(LP_WDT_XTAL32K_WDT_TIMEOUT_S))
#define LP_WDT_XTAL32K_WDT_TIMEOUT_V 0xFF
#define LP_WDT_XTAL32K_WDT_TIMEOUT_S 20
/* LP_WDT_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
/*description: cycles to wait to repower on xtal 32k.*/
#define LP_WDT_XTAL32K_RESTART_WAIT 0x0000FFFF
#define LP_WDT_XTAL32K_RESTART_WAIT_M ((LP_WDT_XTAL32K_RESTART_WAIT_V)<<(LP_WDT_XTAL32K_RESTART_WAIT_S))
#define LP_WDT_XTAL32K_RESTART_WAIT_V 0xFFFF
#define LP_WDT_XTAL32K_RESTART_WAIT_S 4
/* LP_WDT_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
/*description: cycles to wait to return noral xtal 32k.*/
#define LP_WDT_XTAL32K_RETURN_WAIT 0x0000000F
#define LP_WDT_XTAL32K_RETURN_WAIT_M ((LP_WDT_XTAL32K_RETURN_WAIT_V)<<(LP_WDT_XTAL32K_RETURN_WAIT_S))
#define LP_WDT_XTAL32K_RETURN_WAIT_V 0xF
#define LP_WDT_XTAL32K_RETURN_WAIT_S 0
#define LP_WDT_RTC_EFUSE_FORCE_REG (DR_REG_LP_WDT_BASE + 0x60)
/* LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: lp_wdt flashboot en default choose efuse control bit.*/
#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE (BIT(1))
#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_M (BIT(1))
#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_V 0x1
#define LP_WDT_WDT_FLASHBOOT_EFUSE_FORCE_S 1
/* LP_WDT_SWD_DISABLE_EFUSE_FORCE : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: swd disable default choose efuse control bit.*/
#define LP_WDT_SWD_DISABLE_EFUSE_FORCE (BIT(0))
#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_M (BIT(0))
#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_V 0x1
#define LP_WDT_SWD_DISABLE_EFUSE_FORCE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t reserved0 : 2;
uint32_t wdt_chip_reset_width : 8; /*chip reset siginal pulse width*/
uint32_t wdt_chip_reset_en : 1; /*wdt reset whole chip enable*/
uint32_t wdt_pause_in_slp : 1; /*pause WDT in sleep*/
uint32_t wdt_flashboot_mod_en : 1; /*enable WDT in flash boot*/
uint32_t wdt_sys_reset_length : 3; /*system reset counter length*/
uint32_t wdt_cpu_reset_length : 3; /*CPU reset counter length*/
uint32_t wdt_stg3 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
uint32_t wdt_stg2 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
uint32_t wdt_stg1 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
uint32_t wdt_stg0 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
uint32_t wdt_en : 1;
};
uint32_t val;
} wdtconfig0;
union {
struct {
uint32_t reserved0 : 26;
uint32_t wdt_lp_peri_reset_en : 1; /*enable WDT reset LP PERI*/
uint32_t wdt_lp_cpu_reset_en : 1; /*enable WDT reset LP CPU*/
uint32_t wdt_core3cpu_reset_en : 1; /*enable WDT reset CORE3 CPU*/
uint32_t wdt_core2cpu_reset_en : 1; /*enable WDT reset CORE2 CPU*/
uint32_t wdt_core1cpu_reset_en : 1; /*enable WDT reset CORE1 CPU*/
uint32_t wdt_core0cpu_reset_en : 1; /*enable WDT reset CORE0 CPU*/
};
uint32_t val;
} wdtcpurst;
uint32_t wdtconfig1;
uint32_t wdtconfig2;
uint32_t wdtconfig3;
uint32_t wdtconfig4;
union {
struct {
uint32_t reserved0 : 31;
uint32_t wdt_feed : 1;
};
uint32_t val;
} wdtfeed;
uint32_t wdtwprotect;
union {
struct {
uint32_t swd_reset_flag : 1; /*swd reset flag*/
uint32_t swd_feed_int : 1; /*swd interrupt for feeding*/
uint32_t reserved2 : 16;
uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/
uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/
uint32_t swd_feed : 1; /*Sw feed swd*/
uint32_t swd_disable : 1; /*disabel SWD*/
uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/
};
uint32_t val;
} swd_conf;
uint32_t swd_wprotect;
union {
struct {
uint32_t clk_en : 1;
uint32_t reserved1 : 31;
};
uint32_t val;
} wdt_clk_en;
union {
struct {
uint32_t wdt : 1; /*enable RTC WDT interrupt*/
uint32_t swd : 1; /*enable super watch dog interrupt*/
uint32_t reserved2 : 30;
};
uint32_t val;
} int_ena_w1ts;
union {
struct {
uint32_t wdt : 1; /*enable RTC WDT interrupt*/
uint32_t swd : 1; /*enable super watch dog interrupt*/
uint32_t reserved2 : 30;
};
uint32_t val;
} int_ena_w1tc;
union {
struct {
uint32_t wdt : 1; /*enable RTC WDT interrupt*/
uint32_t swd : 1; /*enable super watch dog interrupt*/
uint32_t xtal32k_dead : 1; /*enable xtal32k_dead interrupt*/
uint32_t reserved3 : 29;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t wdt : 1; /*RTC WDT interrupt raw*/
uint32_t swd : 1; /*super watch dog interrupt raw*/
uint32_t xtal32k_dead : 1; /*xtal32k dead detection interrupt raw*/
uint32_t reserved3 : 29;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t wdt : 1; /*watch dog interrupt state*/
uint32_t swd : 1; /*super watch dog interrupt state*/
uint32_t xtal32k_dead : 1; /*xtal32k dead detection interrupt state*/
uint32_t reserved3 : 29;
};
uint32_t val;
} int_swd_st;
union {
struct {
uint32_t wdt : 1; /*Clear RTC WDT interrupt state*/
uint32_t swd : 1; /*Clear super watch dog interrupt state*/
uint32_t xtal32k_dead : 1; /*Clear RTC WDT interrupt state*/
uint32_t reserved3 : 29;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t xtal32k_wdt_en : 1; /*xtal 32k watch dog enable*/
uint32_t xtal32k_wdt_clk_fo : 1; /*xtal 32k watch dog clock force on*/
uint32_t xtal32k_wdt_reset : 1; /*xtal 32k watch dog sw reset*/
uint32_t xtal32k_ext_clk_fo : 1; /*xtal 32k external xtal clock force on*/
uint32_t xtal32k_auto_backup : 1; /*xtal 32k switch to back up clock when xtal is dead*/
uint32_t xtal32k_auto_restart : 1; /*xtal 32k restart xtal when xtal is dead*/
uint32_t xtal32k_auto_return : 1; /*xtal 32k switch back xtal when xtal is restarted*/
uint32_t xtal32k_xpd_force : 1; /*Xtal 32k xpd control by sw or fsm*/
uint32_t enckinit_xtal_32k : 1; /*apply an internal clock to help xtal 32k to start*/
uint32_t dbuf_xtal_32k : 1; /*0: single-end buffer 1: differential buffer*/
uint32_t dgm_xtal_32k : 3; /*xtal_32k gm control*/
uint32_t dres_xtal_32k : 3; /*DRES_XTAL_32K*/
uint32_t xpd_xtal_32k : 1; /*XPD_XTAL_32K*/
uint32_t dac_xtal_32k : 3; /*DAC_XTAL_32K*/
uint32_t wdt_state : 3; /*state of 32k_wdt*/
uint32_t xtal32k_gpio_sel : 1; /*XTAL_32K sel. ; 0: external XTAL_32K; 1: CLK from RTC pad X32P_C*/
uint32_t reserved24 : 6;
uint32_t xtl_ext_ctr_lv : 1; /*0: power down XTAL at high level; 1: power down XTAL at low level*/
uint32_t xtl_ext_ctr_en : 1;
};
uint32_t val;
} ext_xtl_conf;
uint32_t xtal32k_clk_factor;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
union {
struct {
uint32_t xtal32k_return_wait : 4; /*cycles to wait to return noral xtal 32k*/
uint32_t xtal32k_restart_wait : 16; /*cycles to wait to repower on xtal 32k*/
uint32_t xtal32k_wdt_timeout : 8; /*If no clock detected for this amount of time,32k is regarded as dead*/
uint32_t xtal32k_stable_thres : 4; /*if restarted xtal32k period is smaller than this, it is regarded as stable*/
};
uint32_t val;
} xtal32k_conf;
union {
struct {
uint32_t swd_disable_efuse_force : 1; /*swd disable default choose efuse control bit*/
uint32_t wdt_flashboot_efuse_force : 1; /*lp_wdt flashboot en default choose efuse control bit*/
uint32_t reserved2 : 30;
};
uint32_t val;
} efuse_force;
} lp_wdt_dev_t;
extern lp_wdt_dev_t LP_WDT;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_MEM_MONITOR_REG_H_
#define _SOC_MEM_MONITOR_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/* MEM_MONITOR_LOG_DMA_1_ENA : R/W ;bitpos:[31:24] ;default: 8'b0 ; */
/*description: enable dma_1 log.*/
#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FF
#define MEM_MONITOR_LOG_DMA_1_ENA_M ((MEM_MONITOR_LOG_DMA_1_ENA_V)<<(MEM_MONITOR_LOG_DMA_1_ENA_S))
#define MEM_MONITOR_LOG_DMA_1_ENA_V 0xFF
#define MEM_MONITOR_LOG_DMA_1_ENA_S 24
/* MEM_MONITOR_LOG_DMA_0_ENA : R/W ;bitpos:[23:16] ;default: 8'b0 ; */
/*description: enable dma_0 log.*/
#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FF
#define MEM_MONITOR_LOG_DMA_0_ENA_M ((MEM_MONITOR_LOG_DMA_0_ENA_V)<<(MEM_MONITOR_LOG_DMA_0_ENA_S))
#define MEM_MONITOR_LOG_DMA_0_ENA_V 0xFF
#define MEM_MONITOR_LOG_DMA_0_ENA_S 16
/* MEM_MONITOR_LOG_CORE_ENA : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
/*description: enable core log.*/
#define MEM_MONITOR_LOG_CORE_ENA 0x000000FF
#define MEM_MONITOR_LOG_CORE_ENA_M ((MEM_MONITOR_LOG_CORE_ENA_V)<<(MEM_MONITOR_LOG_CORE_ENA_S))
#define MEM_MONITOR_LOG_CORE_ENA_V 0xFF
#define MEM_MONITOR_LOG_CORE_ENA_S 8
/* MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END.*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (BIT(4))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x1
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4
/* MEM_MONITOR_LOG_MODE : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYT
E monitor.*/
#define MEM_MONITOR_LOG_MODE 0x0000000F
#define MEM_MONITOR_LOG_MODE_M ((MEM_MONITOR_LOG_MODE_V)<<(MEM_MONITOR_LOG_MODE_S))
#define MEM_MONITOR_LOG_MODE_V 0xF
#define MEM_MONITOR_LOG_MODE_S 0
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
/* MEM_MONITOR_LOG_DMA_3_ENA : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
/*description: enable dma_3 log.*/
#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FF
#define MEM_MONITOR_LOG_DMA_3_ENA_M ((MEM_MONITOR_LOG_DMA_3_ENA_V)<<(MEM_MONITOR_LOG_DMA_3_ENA_S))
#define MEM_MONITOR_LOG_DMA_3_ENA_V 0xFF
#define MEM_MONITOR_LOG_DMA_3_ENA_S 8
/* MEM_MONITOR_LOG_DMA_2_ENA : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: enable dma_2 log.*/
#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FF
#define MEM_MONITOR_LOG_DMA_2_ENA_M ((MEM_MONITOR_LOG_DMA_2_ENA_V)<<(MEM_MONITOR_LOG_DMA_2_ENA_S))
#define MEM_MONITOR_LOG_DMA_2_ENA_V 0xFF
#define MEM_MONITOR_LOG_DMA_2_ENA_S 0
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
/* MEM_MONITOR_LOG_CHECK_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The special check data, when write this special data, it will trigger logging..*/
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFF
#define MEM_MONITOR_LOG_CHECK_DATA_M ((MEM_MONITOR_LOG_CHECK_DATA_V)<<(MEM_MONITOR_LOG_CHECK_DATA_S))
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFF
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xC)
/* MEM_MONITOR_LOG_DATA_MASK : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BI
T1 mask second byte, and so on..*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000F
#define MEM_MONITOR_LOG_DATA_MASK_M ((MEM_MONITOR_LOG_DATA_MASK_V)<<(MEM_MONITOR_LOG_DATA_MASK_S))
#define MEM_MONITOR_LOG_DATA_MASK_V 0xF
#define MEM_MONITOR_LOG_DATA_MASK_S 0
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
/* MEM_MONITOR_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: the min address of log range.*/
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFF
#define MEM_MONITOR_LOG_MIN_M ((MEM_MONITOR_LOG_MIN_V)<<(MEM_MONITOR_LOG_MIN_S))
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFF
#define MEM_MONITOR_LOG_MIN_S 0
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
/* MEM_MONITOR_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: the max address of log range.*/
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFF
#define MEM_MONITOR_LOG_MAX_M ((MEM_MONITOR_LOG_MAX_V)<<(MEM_MONITOR_LOG_MAX_S))
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFF
#define MEM_MONITOR_LOG_MAX_S 0
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
/* MEM_MONITOR_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: the start address of writing logging message.*/
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFF
#define MEM_MONITOR_LOG_MEM_START_M ((MEM_MONITOR_LOG_MEM_START_V)<<(MEM_MONITOR_LOG_MEM_START_S))
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFF
#define MEM_MONITOR_LOG_MEM_START_S 0
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x1C)
/* MEM_MONITOR_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: the end address of writing logging message.*/
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFF
#define MEM_MONITOR_LOG_MEM_END_M ((MEM_MONITOR_LOG_MEM_END_V)<<(MEM_MONITOR_LOG_MEM_END_S))
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFF
#define MEM_MONITOR_LOG_MEM_END_S 0
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
/* MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: means next writing address.*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFF
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M ((MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V)<<(MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S))
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFF
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
/* MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_ME
M_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START.*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x1
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
/* MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG.*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x1
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
/* MEM_MONITOR_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: 1 means memory write loop at least one time at the range of MEM_START and MEM_EN
D.*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x1
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2C)
/* MEM_MONITOR_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to force on the clk of mem_monitor register.*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (BIT(0))
#define MEM_MONITOR_CLK_EN_V 0x1
#define MEM_MONITOR_CLK_EN_S 0
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3FC)
/* MEM_MONITOR_DATE : R/W ;bitpos:[27:0] ;default: 28'h2302220 ; */
/*description: version register.*/
#define MEM_MONITOR_DATE 0x0FFFFFFF
#define MEM_MONITOR_DATE_M ((MEM_MONITOR_DATE_V)<<(MEM_MONITOR_DATE_S))
#define MEM_MONITOR_DATE_V 0xFFFFFFF
#define MEM_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_MEM_MONITOR_REG_H_ */

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/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_MEM_MONITOR_STRUCT_H_
#define _SOC_MEM_MONITOR_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/soc.h"
typedef volatile struct {
union {
struct {
uint32_t reg_log_mode : 4; /*Bit[0] : WR monitor, BIT[1]: WORD monitor, BIT[2]: HALFWORD monitor, BIT[3]: BYTE monitor */
uint32_t reg_log_mem_loop_enable : 1; /*Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END*/
uint32_t reserved5 : 3; /*reseved*/
uint32_t reg_log_core_ena : 8; /*enable core log*/
uint32_t reg_log_dma_0_ena : 8; /*enable dma_0 log*/
uint32_t reg_log_dma_1_ena : 8; /*enable dma_1 log*/
};
uint32_t val;
} log_setting;
union {
struct {
uint32_t reg_log_dma_2_ena : 8; /*enable dma_2 log*/
uint32_t reg_log_dma_3_ena : 8; /*enable dma_3 log*/
uint32_t reserved16 : 16; /*reseved*/
};
uint32_t val;
} log_setting1;
uint32_t log_check_data;
union {
struct {
uint32_t reg_log_data_mask : 4; /*byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on.*/
uint32_t reserved4 : 28; /*reseved*/
};
uint32_t val;
} log_data_mask;
uint32_t log_min;
uint32_t log_max;
uint32_t log_mem_start;
uint32_t log_mem_end;
uint32_t log_mem_current_addr;
union {
struct {
uint32_t reg_log_mem_addr_update : 1; /*Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START */
uint32_t reserved1 : 31; /*reseved*/
};
uint32_t val;
} log_mem_addr_update;
union {
struct {
uint32_t reg_log_mem_full_flag : 1; /*1 means memory write loop at least one time at the range of MEM_START and MEM_END*/
uint32_t reg_clr_log_mem_full_flag : 1; /*Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG*/
uint32_t reserved2 : 30; /*reseved*/
};
uint32_t val;
} log_mem_full_flag;
union {
struct {
uint32_t reg_clk_en : 1; /*Set 1 to force on the clk of mem_monitor register */
uint32_t reserved1 : 31; /*reseved*/
};
uint32_t val;
} clock_gate;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
union {
struct {
uint32_t reg_mem_monitor_date : 28; /*version register*/
uint32_t reserved28 : 4; /*reseved*/
};
uint32_t val;
} date;
} mem_monitor_dev_t;
extern mem_monitor_dev_t MEM_MONITOR;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_MEM_MONITOR_STRUCT_H_ */

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#include "esp32p4/rom/cache.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t cat0 : 2;
uint32_t cat1 : 2;
uint32_t cat2 : 2;
uint32_t res0 : 8;
uint32_t splitaddr : 8;
uint32_t res1 : 10;
};
uint32_t val;
} constrain_reg_fields_t;
#ifndef I_D_SRAM_SEGMENT_SIZE
#define I_D_SRAM_SEGMENT_SIZE 0x20000
#endif
#define I_D_SPLIT_LINE_SHIFT 0x9
#define I_D_FAULT_ADDR_SHIFT 0x2
#define DRAM_SRAM_START 0x3FC7C000
//IRAM0
//16kB (ICACHE)
#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000
#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF
//128kB (LEVEL 1)
#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000
#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF
//128kB (LEVEL 2)
#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000
#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF
//128kB (LEVEL 3)
#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000
#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF
//permission bits
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4
//DRAM0
//16kB ICACHE not available from DRAM0
//128kB (LEVEL 1)
#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000
#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF
//128kB (LEVEL 2)
#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000
#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF
//128kB (LEVEL 3)
#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000
#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
//RTC FAST
//permission bits
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4
#define AREA_LOW 0
#define AREA_HIGH 1
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/ext_mem_defs.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Defined for flash mmap */
#define SOC_MMU_REGIONS_COUNT 1
#define SOC_MMU_PAGES_PER_REGION 1024
#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
#define SOC_MMU_ADDR_MASK (MMU_VALID - 1)
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
#define SOC_MMU_VADDR0_START_ADDR (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PERIPH_MSPI_MODULE = 0,
PERIPH_DUALMSPI_MODULE,
PERIPH_EMAC_MODULE,
PERIPH_MIPI_DSI_MODULE,
PERIPH_MIPI_CSI_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S0_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_I2S2_MODULE,
PERIPH_LCD_MODULE = 10,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_UART2_MODULE,
PERIPH_UART3_MODULE,
PERIPH_UART4_MODULE,
PERIPH_TWAI0_MODULE,
PERIPH_TWAI1_MODULE,
PERIPH_TWAI2_MODULE,
PERIPH_GPSPI_MODULE,
PERIPH_GPSPI2_MODULE = 20,
PERIPH_GPSPI3_MODULE,
PERIPH_PARLIO_MODULE,
PERIPH_I3C_MODULE,
PERIPH_CAM_MODULE,
PERIPH_MCPWM0_MODULE,
PERIPH_MCPWM1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_LEDC_MODULE = 30,
PERIPH_RMT_MODULE,
PERIPH_SARADC_MODULE,
PERIPH_PVT_MODULE,
PERIPH_AES_MODULE,
PERIPH_DS_MODULE,
PERIPH_ECC_MODULE,
PERIPH_HMAC_MODULE,
PERIPH_RSA_MODULE,
PERIPH_SEC_MODULE,
PERIPH_SHA_MODULE = 40,
PERIPH_ECDSA_MODULE,
PERIPH_ISP_MODULE,
PERIPH_SDMMC_MODULE,
PERIPH_GDMA_MODULE,
PERIPH_GMAC_MODULE,
PERIPH_JPEG_MODULE,
PERIPH_DMA2D_MODULE,
PERIPH_PPA_MODULE,
PERIPH_AHB_PDMA_MODULE,
PERIPH_AXI_PDMA_MODULE,
PERIPH_UHCI_MODULE,
PERIPH_PCNT_MODULE,
PERIPH_MODULE_MAX
} periph_module_t;
typedef enum {
LP_PERIPH_I2C0_MODULE = 0,
LP_PERIPH_UART0_MODULE,
LP_PERIPH_MODULE_MAX,
} lp_periph_module_t;
typedef enum {
ETS_LP_RTC_INTR_SOURCE = 0,
ETS_LP_WDT_INTR_SOURCE,
ETS_LP_TIMER_REG0_INTR_SOURCE,
ETS_LP_TIMER_REG1_INTR_SOURCE,
ETS_MB_HP_INTR_SOURCE,
ETS_MB_LP_INTR_SOURCE,
ETS_PMU_0_INTR_SOURCE,
ETS_PMU_1_INTR_SOURCE,
ETS_LP_ANAPERI_INTR_SOURCE,
ETS_LP_ADC_INTR_SOURCE,
ETS_LP_GPIO_INTR_SOURCE,
ETS_LP_I2C_INTR_SOURCE,
ETS_LP_I2S_INTR_SOURCE,
ETS_LP_SPI_INTR_SOURCE,
ETS_LP_TOUCH_INTR_SOURCE,
ETS_LP_TSENS_INTR_SOURCE,
ETS_LP_UART_INTR_SOURCE,
ETS_LP_EFUSE_INTR_SOURCE,
ETS_LP_SW_INTR_SOURCE,
ETS_LP_SYSREG_INTR_SOURCE,
ETS_LP_HUK_INTR_SOURCE,
ETS_SYS_ICM_INTR_SOURCE,
ETS_USB_DEVICE_INTR_SOURCE,
ETS_SDIO_HOST_INTR_SOURCE,
ETS_GDMA_INTR_SOURCE,
ETS_SPI2_INTR_SOURCE,
ETS_SPI3_INTR_SOURCE,
ETS_I2S0_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE,
ETS_I2S2_INTR_SOURCE,
ETS_UHCI0_INTR_SOURCE,
ETS_UART0_INTR_SOURCE,
ETS_UART1_INTR_SOURCE,
ETS_UART2_INTR_SOURCE,
ETS_UART3_INTR_SOURCE,
ETS_UART4_INTR_SOURCE,
ETS_LCD_CAM_INTR_SOURCE,
ETS_ADC_INTR_SOURCE,
ETS_PWM0_INTR_SOURCE,
ETS_PWM1_INTR_SOURCE,
ETS_CAN0_INTR_SOURCE,
ETS_CAN1_INTR_SOURCE,
ETS_CAN2_INTR_SOURCE,
ETS_RMT_INTR_SOURCE,
ETS_I2C0_INTR_SOURCE,
ETS_I2C1_INTR_SOURCE,
ETS_TIMERGROUP0_T0_INTR_SOURCE,
ETS_TIMERGROUP0_T1_INTR_SOURCE,
ETS_TIMERGROUP0_WDT_INTR_SOURCE,
ETS_TIMERGROUP1_T0_INTR_SOURCE,
ETS_TIMERGROUP1_T1_INTR_SOURCE,
ETS_TIMERGROUP1_WDT_INTR_SOURCE,
ETS_LEDC_INTR_SOURCE,
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
ETS_AHB_PDMA_IN_CH0_INTR_SOURCE,
ETS_AHB_PDMA_IN_CH1_INTR_SOURCE,
ETS_AHB_PDMA_IN_CH2_INTR_SOURCE,
ETS_AHB_PDMA_OUT_CH0_INTR_SOURCE,
ETS_AHB_PDMA_OUT_CH1_INTR_SOURCE,
ETS_AHB_PDMA_OUT_CH2_INTR_SOURCE,
ETS_AXI_PDMA_IN_CH0_INTR_SOURCE,
ETS_AXI_PDMA_IN_CH1_INTR_SOURCE,
ETS_AXI_PDMA_IN_CH2_INTR_SOURCE,
ETS_AXI_PDMA_OUT_CH0_INTR_SOURCE,
ETS_AXI_PDMA_OUT_CH1_INTR_SOURCE,
ETS_AXI_PDMA_OUT_CH2_INTR_SOURCE,
ETS_RSA_INTA_SOURCE,
ETS_AES_INTR_SOURCE,
ETS_SHA_INTR_SOURCE,
ETS_ECC_INTR_SOURCE,
ETS_ECDSA_INTR_SOURCE,
ETS_KM_INTR_SOURCE,
ETS_GPIO_INTR0_SOURCE,
ETS_GPIO_INTR1_SOURCE,
ETS_GPIO_INTR2_SOURCE,
ETS_GPIO_INTR3_SOURCE,
ETS_GPIO_PAD_COMP_INTR_SOURCE,
ETS_CPU_INT_FROM_CPU0_INTR_SOURCE,
ETS_CPU_INT_FROM_CPU1_INTR_SOURCE,
ETS_CPU_INT_FROM_CPU2_INTR_SOURCE,
ETS_CPU_INT_FROM_CPU3_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_CSI_BRIDGE_INTR_SOURCE,
ETS_DSI_BRIDGE_INTR_SOURCE,
ETS_CSI_INTR_SOURCE,
ETS_DSI_INTR_SOURCE,
ETS_GMII_PHY_INTR_SOURCE,
ETS_LPI_INTR_SOURCE,
ETS_PMT_INTR_SOURCE,
ETS_SBD_INTR_SOURCE,
ETS_USB_OTG_INTR_SOURCE,
ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE,
ETS_JPEG_INTR_SOURCE,
ETS_PPA_INTR_SOURCE,
ETS_CORE0_TRACE_INTR_SOURCE,
ETS_CORE1_TRACE_INTR_SOURCE,
ETS_HP_CORE_CTRL_INTR_SOURCE,
ETS_ISP_INTR_SOURCE,
ETS_I3C_MST_INTR_SOURCE,
ETS_I3C_SLV_INTR_SOURCE,
ETS_USB_OTG11_CH0_INTR_SOURCE,
ETS_DMA2D_IN_CH0_INTR_SOURCE,
ETS_DMA2D_IN_CH1_INTR_SOURCE,
ETS_DMA2D_OUT_CH0_INTR_SOURCE,
ETS_DMA2D_OUT_CH1_INTR_SOURCE,
ETS_DMA2D_OUT_CH2_INTR_SOURCE,
ETS_PSRAM_MSPI_INTR_SOURCE,
ETS_HP_SYSREG_INTR_SOURCE,
ETS_PCNT_INTR_SOURCE,
ETS_HP_PAU_INTR_SOURCE,
ETS_HP_PARLIO_RX_INTR_SOURCE,
ETS_HP_PARLIO_TX_INTR_SOURCE,
ETS_H264_DMA2D_OUT_CH0_INTR_SOURCE,
ETS_H264_DMA2D_OUT_CH1_INTR_SOURCE,
ETS_H264_DMA2D_OUT_CH2_INTR_SOURCE,
ETS_H264_DMA2D_OUT_CH3_INTR_SOURCE,
ETS_H264_DMA2D_OUT_CH4_INTR_SOURCE,
ETS_H264_DMA2D_IN_CH0_INTR_SOURCE,
ETS_H264_DMA2D_IN_CH1_INTR_SOURCE,
ETS_H264_DMA2D_IN_CH2_INTR_SOURCE,
ETS_H264_DMA2D_IN_CH3_INTR_SOURCE,
ETS_H264_DMA2D_IN_CH4_INTR_SOURCE,
ETS_H264_DMA2D_IN_CH5_INTR_SOURCE,
ETS_H264_REG_INTR_SOURCE,
ETS_ASSIST_DEBUG_INTR_SOURCE,
ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */
} periph_interrput_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define PLIC_MXINT_CONF_REG ( 0x200013FC )
#define PLIC_UXINT_CONF_REG ( 0x200017FC )
#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
/*PLIC MX*/
#define PLIC_MXINT_ENABLE_REG (DR_REG_PLIC_MX_BASE + 0x0)
/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_MXINT_ENABLE 0xFFFFFFFF
#define PLIC_CPU_MXINT_ENABLE_M ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S))
#define PLIC_CPU_MXINT_ENABLE_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_ENABLE_S 0
#define PLIC_MXINT_TYPE_REG (DR_REG_PLIC_MX_BASE + 0x4)
/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_MXINT_TYPE 0xFFFFFFFF
#define PLIC_CPU_MXINT_TYPE_M ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S))
#define PLIC_CPU_MXINT_TYPE_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_TYPE_S 0
#define PLIC_MXINT_CLEAR_REG (DR_REG_PLIC_MX_BASE + 0x8)
/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S))
#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLEAR_S 0
#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC)
/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_S 0
#define PLIC_MXINT0_PRI_REG (DR_REG_PLIC_MX_BASE + 0x10)
/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT0_PRI 0x0000000F
#define PLIC_CPU_MXINT0_PRI_M ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S))
#define PLIC_CPU_MXINT0_PRI_V 0xF
#define PLIC_CPU_MXINT0_PRI_S 0
#define PLIC_MXINT1_PRI_REG (DR_REG_PLIC_MX_BASE + 0x14)
/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT1_PRI 0x0000000F
#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S))
#define PLIC_CPU_MXINT1_PRI_V 0xF
#define PLIC_CPU_MXINT1_PRI_S 0
#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18)
/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT2_PRI 0x0000000F
#define PLIC_CPU_MXINT2_PRI_M ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S))
#define PLIC_CPU_MXINT2_PRI_V 0xF
#define PLIC_CPU_MXINT2_PRI_S 0
#define PLIC_MXINT3_PRI_REG (DR_REG_PLIC_MX_BASE + 0x1C)
/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT3_PRI 0x0000000F
#define PLIC_CPU_MXINT3_PRI_M ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S))
#define PLIC_CPU_MXINT3_PRI_V 0xF
#define PLIC_CPU_MXINT3_PRI_S 0
#define PLIC_MXINT4_PRI_REG (DR_REG_PLIC_MX_BASE + 0x20)
/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT4_PRI 0x0000000F
#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S))
#define PLIC_CPU_MXINT4_PRI_V 0xF
#define PLIC_CPU_MXINT4_PRI_S 0
#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24)
/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT5_PRI 0x0000000F
#define PLIC_CPU_MXINT5_PRI_M ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S))
#define PLIC_CPU_MXINT5_PRI_V 0xF
#define PLIC_CPU_MXINT5_PRI_S 0
#define PLIC_MXINT6_PRI_REG (DR_REG_PLIC_MX_BASE + 0x28)
/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT6_PRI 0x0000000F
#define PLIC_CPU_MXINT6_PRI_M ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S))
#define PLIC_CPU_MXINT6_PRI_V 0xF
#define PLIC_CPU_MXINT6_PRI_S 0
#define PLIC_MXINT7_PRI_REG (DR_REG_PLIC_MX_BASE + 0x2C)
/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT7_PRI 0x0000000F
#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S))
#define PLIC_CPU_MXINT7_PRI_V 0xF
#define PLIC_CPU_MXINT7_PRI_S 0
#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30)
/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT8_PRI 0x0000000F
#define PLIC_CPU_MXINT8_PRI_M ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S))
#define PLIC_CPU_MXINT8_PRI_V 0xF
#define PLIC_CPU_MXINT8_PRI_S 0
#define PLIC_MXINT9_PRI_REG (DR_REG_PLIC_MX_BASE + 0x34)
/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT9_PRI 0x0000000F
#define PLIC_CPU_MXINT9_PRI_M ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S))
#define PLIC_CPU_MXINT9_PRI_V 0xF
#define PLIC_CPU_MXINT9_PRI_S 0
#define PLIC_MXINT10_PRI_REG (DR_REG_PLIC_MX_BASE + 0x38)
/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT10_PRI 0x0000000F
#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S))
#define PLIC_CPU_MXINT10_PRI_V 0xF
#define PLIC_CPU_MXINT10_PRI_S 0
#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C)
/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT11_PRI 0x0000000F
#define PLIC_CPU_MXINT11_PRI_M ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S))
#define PLIC_CPU_MXINT11_PRI_V 0xF
#define PLIC_CPU_MXINT11_PRI_S 0
#define PLIC_MXINT12_PRI_REG (DR_REG_PLIC_MX_BASE + 0x40)
/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT12_PRI 0x0000000F
#define PLIC_CPU_MXINT12_PRI_M ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S))
#define PLIC_CPU_MXINT12_PRI_V 0xF
#define PLIC_CPU_MXINT12_PRI_S 0
#define PLIC_MXINT13_PRI_REG (DR_REG_PLIC_MX_BASE + 0x44)
/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT13_PRI 0x0000000F
#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S))
#define PLIC_CPU_MXINT13_PRI_V 0xF
#define PLIC_CPU_MXINT13_PRI_S 0
#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48)
/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT14_PRI 0x0000000F
#define PLIC_CPU_MXINT14_PRI_M ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S))
#define PLIC_CPU_MXINT14_PRI_V 0xF
#define PLIC_CPU_MXINT14_PRI_S 0
#define PLIC_MXINT15_PRI_REG (DR_REG_PLIC_MX_BASE + 0x4C)
/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT15_PRI 0x0000000F
#define PLIC_CPU_MXINT15_PRI_M ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S))
#define PLIC_CPU_MXINT15_PRI_V 0xF
#define PLIC_CPU_MXINT15_PRI_S 0
#define PLIC_MXINT16_PRI_REG (DR_REG_PLIC_MX_BASE + 0x50)
/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT16_PRI 0x0000000F
#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S))
#define PLIC_CPU_MXINT16_PRI_V 0xF
#define PLIC_CPU_MXINT16_PRI_S 0
#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54)
/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT17_PRI 0x0000000F
#define PLIC_CPU_MXINT17_PRI_M ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S))
#define PLIC_CPU_MXINT17_PRI_V 0xF
#define PLIC_CPU_MXINT17_PRI_S 0
#define PLIC_MXINT18_PRI_REG (DR_REG_PLIC_MX_BASE + 0x58)
/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT18_PRI 0x0000000F
#define PLIC_CPU_MXINT18_PRI_M ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S))
#define PLIC_CPU_MXINT18_PRI_V 0xF
#define PLIC_CPU_MXINT18_PRI_S 0
#define PLIC_MXINT19_PRI_REG (DR_REG_PLIC_MX_BASE + 0x5C)
/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT19_PRI 0x0000000F
#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S))
#define PLIC_CPU_MXINT19_PRI_V 0xF
#define PLIC_CPU_MXINT19_PRI_S 0
#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60)
/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT20_PRI 0x0000000F
#define PLIC_CPU_MXINT20_PRI_M ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S))
#define PLIC_CPU_MXINT20_PRI_V 0xF
#define PLIC_CPU_MXINT20_PRI_S 0
#define PLIC_MXINT21_PRI_REG (DR_REG_PLIC_MX_BASE + 0x64)
/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT21_PRI 0x0000000F
#define PLIC_CPU_MXINT21_PRI_M ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S))
#define PLIC_CPU_MXINT21_PRI_V 0xF
#define PLIC_CPU_MXINT21_PRI_S 0
#define PLIC_MXINT22_PRI_REG (DR_REG_PLIC_MX_BASE + 0x68)
/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT22_PRI 0x0000000F
#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S))
#define PLIC_CPU_MXINT22_PRI_V 0xF
#define PLIC_CPU_MXINT22_PRI_S 0
#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C)
/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT23_PRI 0x0000000F
#define PLIC_CPU_MXINT23_PRI_M ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S))
#define PLIC_CPU_MXINT23_PRI_V 0xF
#define PLIC_CPU_MXINT23_PRI_S 0
#define PLIC_MXINT24_PRI_REG (DR_REG_PLIC_MX_BASE + 0x70)
/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT24_PRI 0x0000000F
#define PLIC_CPU_MXINT24_PRI_M ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S))
#define PLIC_CPU_MXINT24_PRI_V 0xF
#define PLIC_CPU_MXINT24_PRI_S 0
#define PLIC_MXINT25_PRI_REG (DR_REG_PLIC_MX_BASE + 0x74)
/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT25_PRI 0x0000000F
#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S))
#define PLIC_CPU_MXINT25_PRI_V 0xF
#define PLIC_CPU_MXINT25_PRI_S 0
#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78)
/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT26_PRI 0x0000000F
#define PLIC_CPU_MXINT26_PRI_M ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S))
#define PLIC_CPU_MXINT26_PRI_V 0xF
#define PLIC_CPU_MXINT26_PRI_S 0
#define PLIC_MXINT27_PRI_REG (DR_REG_PLIC_MX_BASE + 0x7C)
/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT27_PRI 0x0000000F
#define PLIC_CPU_MXINT27_PRI_M ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S))
#define PLIC_CPU_MXINT27_PRI_V 0xF
#define PLIC_CPU_MXINT27_PRI_S 0
#define PLIC_MXINT28_PRI_REG (DR_REG_PLIC_MX_BASE + 0x80)
/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT28_PRI 0x0000000F
#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S))
#define PLIC_CPU_MXINT28_PRI_V 0xF
#define PLIC_CPU_MXINT28_PRI_S 0
#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84)
/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT29_PRI 0x0000000F
#define PLIC_CPU_MXINT29_PRI_M ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S))
#define PLIC_CPU_MXINT29_PRI_V 0xF
#define PLIC_CPU_MXINT29_PRI_S 0
#define PLIC_MXINT30_PRI_REG (DR_REG_PLIC_MX_BASE + 0x88)
/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT30_PRI 0x0000000F
#define PLIC_CPU_MXINT30_PRI_M ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S))
#define PLIC_CPU_MXINT30_PRI_V 0xF
#define PLIC_CPU_MXINT30_PRI_S 0
#define PLIC_MXINT31_PRI_REG (DR_REG_PLIC_MX_BASE + 0x8C)
/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT31_PRI 0x0000000F
#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S))
#define PLIC_CPU_MXINT31_PRI_V 0xF
#define PLIC_CPU_MXINT31_PRI_S 0
#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90)
/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
/*description: .*/
#define PLIC_CPU_MXINT_THRESH 0x000000FF
#define PLIC_CPU_MXINT_THRESH_M ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S))
#define PLIC_CPU_MXINT_THRESH_V 0xFF
#define PLIC_CPU_MXINT_THRESH_S 0
#define PLIC_MXINT_CLAIM_REG (DR_REG_PLIC_MX_BASE + 0x94)
/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/
#define PLIC_CPU_MXINT_CLAIM 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLAIM_M ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S))
#define PLIC_CPU_MXINT_CLAIM_V 0xFFFFFFFF
#define PLIC_CPU_MXINT_CLAIM_S 0
/*PLIC UX*/
#define PLIC_UXINT_ENABLE_REG (DR_REG_PLIC_UX_BASE + 0x0)
/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF
#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S))
#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_ENABLE_S 0
#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4)
/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_TYPE 0xFFFFFFFF
#define PLIC_CPU_UXINT_TYPE_M ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S))
#define PLIC_CPU_UXINT_TYPE_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_TYPE_S 0
#define PLIC_UXINT_CLEAR_REG (DR_REG_PLIC_UX_BASE + 0x8)
/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_CLEAR 0xFFFFFFFF
#define PLIC_CPU_UXINT_CLEAR_M ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S))
#define PLIC_CPU_UXINT_CLEAR_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_CLEAR_S 0
#define PLIC_EUIP_STATUS_REG (DR_REG_PLIC_UX_BASE + 0xC)
/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF
#define PLIC_CPU_EIP_STATUS_S 0
#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10)
/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT0_PRI 0x0000000F
#define PLIC_CPU_UXINT0_PRI_M ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S))
#define PLIC_CPU_UXINT0_PRI_V 0xF
#define PLIC_CPU_UXINT0_PRI_S 0
#define PLIC_UXINT1_PRI_REG (DR_REG_PLIC_UX_BASE + 0x14)
/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT1_PRI 0x0000000F
#define PLIC_CPU_UXINT1_PRI_M ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S))
#define PLIC_CPU_UXINT1_PRI_V 0xF
#define PLIC_CPU_UXINT1_PRI_S 0
#define PLIC_UXINT2_PRI_REG (DR_REG_PLIC_UX_BASE + 0x18)
/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT2_PRI 0x0000000F
#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S))
#define PLIC_CPU_UXINT2_PRI_V 0xF
#define PLIC_CPU_UXINT2_PRI_S 0
#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C)
/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT3_PRI 0x0000000F
#define PLIC_CPU_UXINT3_PRI_M ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S))
#define PLIC_CPU_UXINT3_PRI_V 0xF
#define PLIC_CPU_UXINT3_PRI_S 0
#define PLIC_UXINT4_PRI_REG (DR_REG_PLIC_UX_BASE + 0x20)
/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT4_PRI 0x0000000F
#define PLIC_CPU_UXINT4_PRI_M ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S))
#define PLIC_CPU_UXINT4_PRI_V 0xF
#define PLIC_CPU_UXINT4_PRI_S 0
#define PLIC_UXINT5_PRI_REG (DR_REG_PLIC_UX_BASE + 0x24)
/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT5_PRI 0x0000000F
#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S))
#define PLIC_CPU_UXINT5_PRI_V 0xF
#define PLIC_CPU_UXINT5_PRI_S 0
#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28)
/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT6_PRI 0x0000000F
#define PLIC_CPU_UXINT6_PRI_M ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S))
#define PLIC_CPU_UXINT6_PRI_V 0xF
#define PLIC_CPU_UXINT6_PRI_S 0
#define PLIC_UXINT7_PRI_REG (DR_REG_PLIC_UX_BASE + 0x2C)
/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT7_PRI 0x0000000F
#define PLIC_CPU_UXINT7_PRI_M ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S))
#define PLIC_CPU_UXINT7_PRI_V 0xF
#define PLIC_CPU_UXINT7_PRI_S 0
#define PLIC_UXINT8_PRI_REG (DR_REG_PLIC_UX_BASE + 0x30)
/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT8_PRI 0x0000000F
#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S))
#define PLIC_CPU_UXINT8_PRI_V 0xF
#define PLIC_CPU_UXINT8_PRI_S 0
#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34)
/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT9_PRI 0x0000000F
#define PLIC_CPU_UXINT9_PRI_M ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S))
#define PLIC_CPU_UXINT9_PRI_V 0xF
#define PLIC_CPU_UXINT9_PRI_S 0
#define PLIC_UXINT10_PRI_REG (DR_REG_PLIC_UX_BASE + 0x38)
/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT10_PRI 0x0000000F
#define PLIC_CPU_UXINT10_PRI_M ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S))
#define PLIC_CPU_UXINT10_PRI_V 0xF
#define PLIC_CPU_UXINT10_PRI_S 0
#define PLIC_UXINT11_PRI_REG (DR_REG_PLIC_UX_BASE + 0x3C)
/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT11_PRI 0x0000000F
#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S))
#define PLIC_CPU_UXINT11_PRI_V 0xF
#define PLIC_CPU_UXINT11_PRI_S 0
#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40)
/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT12_PRI 0x0000000F
#define PLIC_CPU_UXINT12_PRI_M ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S))
#define PLIC_CPU_UXINT12_PRI_V 0xF
#define PLIC_CPU_UXINT12_PRI_S 0
#define PLIC_UXINT13_PRI_REG (DR_REG_PLIC_UX_BASE + 0x44)
/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT13_PRI 0x0000000F
#define PLIC_CPU_UXINT13_PRI_M ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S))
#define PLIC_CPU_UXINT13_PRI_V 0xF
#define PLIC_CPU_UXINT13_PRI_S 0
#define PLIC_UXINT14_PRI_REG (DR_REG_PLIC_UX_BASE + 0x48)
/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT14_PRI 0x0000000F
#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S))
#define PLIC_CPU_UXINT14_PRI_V 0xF
#define PLIC_CPU_UXINT14_PRI_S 0
#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C)
/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT15_PRI 0x0000000F
#define PLIC_CPU_UXINT15_PRI_M ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S))
#define PLIC_CPU_UXINT15_PRI_V 0xF
#define PLIC_CPU_UXINT15_PRI_S 0
#define PLIC_UXINT16_PRI_REG (DR_REG_PLIC_UX_BASE + 0x50)
/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT16_PRI 0x0000000F
#define PLIC_CPU_UXINT16_PRI_M ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S))
#define PLIC_CPU_UXINT16_PRI_V 0xF
#define PLIC_CPU_UXINT16_PRI_S 0
#define PLIC_UXINT17_PRI_REG (DR_REG_PLIC_UX_BASE + 0x54)
/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT17_PRI 0x0000000F
#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S))
#define PLIC_CPU_UXINT17_PRI_V 0xF
#define PLIC_CPU_UXINT17_PRI_S 0
#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58)
/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT18_PRI 0x0000000F
#define PLIC_CPU_UXINT18_PRI_M ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S))
#define PLIC_CPU_UXINT18_PRI_V 0xF
#define PLIC_CPU_UXINT18_PRI_S 0
#define PLIC_UXINT19_PRI_REG (DR_REG_PLIC_UX_BASE + 0x5C)
/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT19_PRI 0x0000000F
#define PLIC_CPU_UXINT19_PRI_M ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S))
#define PLIC_CPU_UXINT19_PRI_V 0xF
#define PLIC_CPU_UXINT19_PRI_S 0
#define PLIC_UXINT20_PRI_REG (DR_REG_PLIC_UX_BASE + 0x60)
/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT20_PRI 0x0000000F
#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S))
#define PLIC_CPU_UXINT20_PRI_V 0xF
#define PLIC_CPU_UXINT20_PRI_S 0
#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64)
/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT21_PRI 0x0000000F
#define PLIC_CPU_UXINT21_PRI_M ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S))
#define PLIC_CPU_UXINT21_PRI_V 0xF
#define PLIC_CPU_UXINT21_PRI_S 0
#define PLIC_UXINT22_PRI_REG (DR_REG_PLIC_UX_BASE + 0x68)
/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT22_PRI 0x0000000F
#define PLIC_CPU_UXINT22_PRI_M ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S))
#define PLIC_CPU_UXINT22_PRI_V 0xF
#define PLIC_CPU_UXINT22_PRI_S 0
#define PLIC_UXINT23_PRI_REG (DR_REG_PLIC_UX_BASE + 0x6C)
/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT23_PRI 0x0000000F
#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S))
#define PLIC_CPU_UXINT23_PRI_V 0xF
#define PLIC_CPU_UXINT23_PRI_S 0
#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70)
/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT24_PRI 0x0000000F
#define PLIC_CPU_UXINT24_PRI_M ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S))
#define PLIC_CPU_UXINT24_PRI_V 0xF
#define PLIC_CPU_UXINT24_PRI_S 0
#define PLIC_UXINT25_PRI_REG (DR_REG_PLIC_UX_BASE + 0x74)
/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT25_PRI 0x0000000F
#define PLIC_CPU_UXINT25_PRI_M ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S))
#define PLIC_CPU_UXINT25_PRI_V 0xF
#define PLIC_CPU_UXINT25_PRI_S 0
#define PLIC_UXINT26_PRI_REG (DR_REG_PLIC_UX_BASE + 0x78)
/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT26_PRI 0x0000000F
#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S))
#define PLIC_CPU_UXINT26_PRI_V 0xF
#define PLIC_CPU_UXINT26_PRI_S 0
#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C)
/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT27_PRI 0x0000000F
#define PLIC_CPU_UXINT27_PRI_M ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S))
#define PLIC_CPU_UXINT27_PRI_V 0xF
#define PLIC_CPU_UXINT27_PRI_S 0
#define PLIC_UXINT28_PRI_REG (DR_REG_PLIC_UX_BASE + 0x80)
/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT28_PRI 0x0000000F
#define PLIC_CPU_UXINT28_PRI_M ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S))
#define PLIC_CPU_UXINT28_PRI_V 0xF
#define PLIC_CPU_UXINT28_PRI_S 0
#define PLIC_UXINT29_PRI_REG (DR_REG_PLIC_UX_BASE + 0x84)
/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT29_PRI 0x0000000F
#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S))
#define PLIC_CPU_UXINT29_PRI_V 0xF
#define PLIC_CPU_UXINT29_PRI_S 0
#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88)
/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT30_PRI 0x0000000F
#define PLIC_CPU_UXINT30_PRI_M ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S))
#define PLIC_CPU_UXINT30_PRI_V 0xF
#define PLIC_CPU_UXINT30_PRI_S 0
#define PLIC_UXINT31_PRI_REG (DR_REG_PLIC_UX_BASE + 0x8C)
/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT31_PRI 0x0000000F
#define PLIC_CPU_UXINT31_PRI_M ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S))
#define PLIC_CPU_UXINT31_PRI_V 0xF
#define PLIC_CPU_UXINT31_PRI_S 0
#define PLIC_UXINT_THRESH_REG (DR_REG_PLIC_UX_BASE + 0x90)
/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_THRESH 0x000000FF
#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S))
#define PLIC_CPU_UXINT_THRESH_V 0xFF
#define PLIC_CPU_UXINT_THRESH_S 0
#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94)
/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: .*/
#define PLIC_CPU_UXINT_CLAIM 0xFFFFFFFF
#define PLIC_CPU_UXINT_CLAIM_M ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S))
#define PLIC_CPU_UXINT_CLAIM_V 0xFFFFFFFF
#define PLIC_CPU_UXINT_CLAIM_S 0
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_ICG_MAP_H_
#define _SOC_ICG_MAP_H_
#define PMU_ICG_APB_ENA_CAN0 18
#define PMU_ICG_APB_ENA_CAN1 19
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_APB_ENA_I2S 4
#define PMU_ICG_APB_ENA_INTMTX 3
#define PMU_ICG_APB_ENA_IOMUX 26
#define PMU_ICG_APB_ENA_LEDC 14
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
#define PMU_ICG_APB_ENA_MSPI 5
#define PMU_ICG_APB_ENA_PARL 23
#define PMU_ICG_APB_ENA_PCNT 20
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
#define PMU_ICG_APB_ENA_PWM 21
#define PMU_ICG_APB_ENA_REGDMA 24
#define PMU_ICG_APB_ENA_RMT 15
#define PMU_ICG_APB_ENA_SARADC 9
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_SOC_ETM 22
#define PMU_ICG_APB_ENA_SPI2 2
#define PMU_ICG_APB_ENA_SYSTIMER 16
#define PMU_ICG_APB_ENA_TG0 11
#define PMU_ICG_APB_ENA_TG1 12
#define PMU_ICG_APB_ENA_UART0 6
#define PMU_ICG_APB_ENA_UART1 7
#define PMU_ICG_APB_ENA_UHCI 8
#define PMU_ICG_APB_ENA_USB_DEVICE 17
#define PMU_ICG_FUNC_ENA_CAN0 31
#define PMU_ICG_FUNC_ENA_CAN1 30
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_I2S_RX 2
#define PMU_ICG_FUNC_ENA_I2S_TX 7
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
#define PMU_ICG_FUNC_ENA_PWM 22
#define PMU_ICG_FUNC_ENA_RMT 21
#define PMU_ICG_FUNC_ENA_SARADC 20
#define PMU_ICG_FUNC_ENA_SEC 19
#define PMU_ICG_FUNC_ENA_SPI2 1
#define PMU_ICG_FUNC_ENA_SYSTIMER 18
#define PMU_ICG_FUNC_ENA_TG0 14
#define PMU_ICG_FUNC_ENA_TG1 13
#define PMU_ICG_FUNC_ENA_TSENS 12
#define PMU_ICG_FUNC_ENA_UART0 3
#define PMU_ICG_FUNC_ENA_UART1 4
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
#define PMU_ICG_FUNC_ENA_GDMA 0
#define PMU_ICG_FUNC_ENA_SOC_ETM 16
#define PMU_ICG_FUNC_ENA_REGDMA 8
#define PMU_ICG_FUNC_ENA_RETENTION 9
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
#define PMU_ICG_FUNC_ENA_UHCI 5
#define PMU_ICG_FUNC_ENA_HPCORE 17
#define PMU_ICG_FUNC_ENA_HPBUS 15
#endif /* _SOC_ICG_MAP_H_ */

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
//#define DR_REG_PLIC_MX_BASE 0x20001000
//#define DR_REG_PLIC_UX_BASE 0x20001400
//#define DR_REG_CLINT_M_BASE 0x20001800
//#define DR_REG_CLINT_U_BASE 0x20001C00
/* Basic address */
#define DR_REG_HPCPUTCP_BASE 0x3FF00000
#define DR_REG_HPPERIPH0_BASE 0x50000000
#define DR_REG_HPPERIPH1_BASE 0x500C0000
#define DR_REG_LPAON_BASE 0x50110000
#define DR_REG_LPPERIPH_BASE 0x50120000
/* This is raw module base from digital team
* some of them may not be used in rom
* just keep them for a reference
*/
/*
* @module: CPU-PERIPHERAL
*
* @base: 0x3FF00000
*
* @size: 128KB
*/
#define DR_REG_TRACE0_BASE (DR_REG_HPCPUTCP_BASE + 0x4000)
#define DR_REG_TRACE1_BASE (DR_REG_HPCPUTCP_BASE + 0x5000)
#define DR_REG_CPU_BUS_MON_BASE (DR_REG_HPCPUTCP_BASE + 0x6000)
#define DR_REG_L2MEM_MON_BASE (DR_REG_HPCPUTCP_BASE + 0xE000)
#define DR_REG_TCM_MON_BASE (DR_REG_HPCPUTCP_BASE + 0xF000)
#define DR_REG_CACHE_BASE (DR_REG_HPCPUTCP_BASE + 0x10000)
/*
* @module: PERIPHERAL0
*
* @base: 0x50000000
*
* @size: 768KB
*/
#define DR_REG_USB2_BASE (DR_REG_HPPERIPH0_BASE + 0x0)
#define DR_REG_USB11_BASE (DR_REG_HPPERIPH0_BASE + 0x40000)
#define DR_REG_USB_WRAP_BASE (DR_REG_HPPERIPH0_BASE + 0x80000)
#define DR_REG_GDMA_BASE (DR_REG_HPPERIPH0_BASE + 0x81000)
#define DR_REG_REGDMA_BASE (DR_REG_HPPERIPH0_BASE + 0x82000)
#define DR_REG_SDMMC_BASE (DR_REG_HPPERIPH0_BASE + 0x83000)
#define DR_REG_H264_CORE_BASE (DR_REG_HPPERIPH0_BASE + 0x84000)
#define DR_REG_AHB_PDMA_BASE (DR_REG_HPPERIPH0_BASE + 0x85000)
#define DR_REG_JPEG_BASE (DR_REG_HPPERIPH0_BASE + 0x86000)
#define DR_REG_PPA_BASE (DR_REG_HPPERIPH0_BASE + 0x87000)
#define DR_REG_DMA2D_BASE (DR_REG_HPPERIPH0_BASE + 0x88000)
#define DR_REG_KEY_MANAGER_BASE (DR_REG_HPPERIPH0_BASE + 0x89000)
#define DR_REG_AXI_DMA_BASE (DR_REG_HPPERIPH0_BASE + 0x8A000)
#define DR_REG_SPI0_BASE (DR_REG_HPPERIPH0_BASE + 0x8C000)
#define DR_REG_SPI1_BASE (DR_REG_HPPERIPH0_BASE + 0x8D000)
#define DR_REG_PSRAM_MSPI0_BASE (DR_REG_HPPERIPH0_BASE + 0x8E000)
#define DR_REG_PSRAM_MSPI1_BASE (DR_REG_HPPERIPH0_BASE + 0x8F000)
#define DR_REG_CRYPTO_BASE (DR_REG_HPPERIPH0_BASE + 0x90000)
#define DR_REG_GMAC_BASE (DR_REG_HPPERIPH0_BASE + 0x98000)
#define DR_REG_USBPHY_BASE (DR_REG_HPPERIPH0_BASE + 0x9C000)
#define DR_REG_DDRPHY_BASE (DR_REG_HPPERIPH0_BASE + 0x9D000)
#define DR_REG_PVT_BASE (DR_REG_HPPERIPH0_BASE + 0x9E000)
#define DR_REG_CSI_HOST_BASE (DR_REG_HPPERIPH0_BASE + 0x9F000)
#define DR_REG_DSI_HOST_BASE (DR_REG_HPPERIPH0_BASE + 0xA0000)
#define DR_REG_ISP_BASE (DR_REG_HPPERIPH0_BASE + 0xA1000)
#define DR_REG_RMT_BASE (DR_REG_HPPERIPH0_BASE + 0xA2000)
#define DR_REG_BITSCRAM_BASE (DR_REG_HPPERIPH0_BASE + 0xA3000)
#define DR_REG_AXI_ICM_BASE (DR_REG_HPPERIPH0_BASE + 0xA4000)
#define DR_REG_HP_PERI_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA5000)
#define DR_REG_LP2HP_PERI_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA5800)
#define DR_REG_DMA_PMS_BASE (DR_REG_HPPERIPH0_BASE + 0xA6000)
#define DR_REG_H264_DMA_2D_BASE (DR_REG_HPPERIPH0_BASE + 0xA7000)
/*
* @module: PERIPHERAL1
*
* @base: 0x500C0000
*
* @size: 256KB
*/
#define DR_REG_MCPWM0_BASE (DR_REG_HPPERIPH1_BASE + 0x0)
#define DR_REG_MCPWM1_BASE (DR_REG_HPPERIPH1_BASE + 0x1000)
#define DR_REG_TIMG0_BASE (DR_REG_HPPERIPH1_BASE + 0x2000)
#define DR_REG_TIMG1_BASE (DR_REG_HPPERIPH1_BASE + 0x3000)
#define DR_REG_I2C0_BASE (DR_REG_HPPERIPH1_BASE + 0x4000)
#define DR_REG_I2C1_BASE (DR_REG_HPPERIPH1_BASE + 0x5000)
#define DR_REG_I2S0_BASE (DR_REG_HPPERIPH1_BASE + 0x6000)
#define DR_REG_I2S1_BASE (DR_REG_HPPERIPH1_BASE + 0x7000)
#define DR_REG_I2S2_BASE (DR_REG_HPPERIPH1_BASE + 0x8000)
#define DR_REG_PCNT_BASE (DR_REG_HPPERIPH1_BASE + 0x9000)
#define DR_REG_UART0_BASE (DR_REG_HPPERIPH1_BASE + 0xA000)
#define DR_REG_UART1_BASE (DR_REG_HPPERIPH1_BASE + 0xB000)
#define DR_REG_UART2_BASE (DR_REG_HPPERIPH1_BASE + 0xC000)
#define DR_REG_UART3_BASE (DR_REG_HPPERIPH1_BASE + 0xD000)
#define DR_REG_UART4_BASE (DR_REG_HPPERIPH1_BASE + 0xE000)
#define DR_REG_PARIO_BASE (DR_REG_HPPERIPH1_BASE + 0xF000)
#define DR_REG_SPI2_BASE (DR_REG_HPPERIPH1_BASE + 0x10000)
#define DR_REG_SPI3_BASE (DR_REG_HPPERIPH1_BASE + 0x11000)
#define DR_REG_USB2JTAG_BASE (DR_REG_HPPERIPH1_BASE + 0x12000)
#define DR_REG_LEDC_BASE (DR_REG_HPPERIPH1_BASE + 0x13000)
#define DR_REG_ETM_BASE (DR_REG_HPPERIPH1_BASE + 0x15000)
#define DR_REG_INTR_BASE (DR_REG_HPPERIPH1_BASE + 0x16000)
#define DR_REG_TWAI0_BASE (DR_REG_HPPERIPH1_BASE + 0x17000)
#define DR_REG_TWAI1_BASE (DR_REG_HPPERIPH1_BASE + 0x18000)
#define DR_REG_TWAI2_BASE (DR_REG_HPPERIPH1_BASE + 0x19000)
#define DR_REG_I3C_MST_BASE (DR_REG_HPPERIPH1_BASE + 0x1A000)
#define DR_REG_I3C_SLV_BASE (DR_REG_HPPERIPH1_BASE + 0x1B000)
#define DR_REG_LCDCAM_BASE (DR_REG_HPPERIPH1_BASE + 0x1C000)
#define DR_REG_ADC_BASE (DR_REG_HPPERIPH1_BASE + 0x1E000)
#define DR_REG_UHCI_BASE (DR_REG_HPPERIPH1_BASE + 0x1F000)
#define DR_REG_GPIO_BASE (DR_REG_HPPERIPH1_BASE + 0x20000)
#define DR_REG_GPIO_SD_BASE (DR_REG_HPPERIPH1_BASE + 0x20F00)
#define DR_REG_IO_MUX_BASE (DR_REG_HPPERIPH1_BASE + 0x21000)
#define DR_REG_SYSTIMER_BASE (DR_REG_HPPERIPH1_BASE + 0x22000)
#define DR_REG_MEM_MON_BASE (DR_REG_HPPERIPH1_BASE + 0x23000)
#define DR_REG_AUDIO_ADDC_BASE (DR_REG_HPPERIPH1_BASE + 0x24000)
#define DR_REG_HP_SYS_BASE (DR_REG_HPPERIPH1_BASE + 0x25000)
#define DR_REG_HP_SYS_CLKRST_BASE (DR_REG_HPPERIPH1_BASE + 0x26000)
/*
* @module: LP AON
*
* @base: 0x50110000
*
* @size: 64KB
*/
#define DR_REG_LP_SYS_BASE (DR_REG_LPAON_BASE + 0x0)
#define DR_REG_LP_AONCLKRST_BASE (DR_REG_LPAON_BASE + 0x1000)
#define DR_REG_LP_TIMER_BASE (DR_REG_LPAON_BASE + 0x2000)
#define DR_REG_LP_ANAPERI_BASE (DR_REG_LPAON_BASE + 0x3000)
#define DR_REG_LP_HUK_BASE (DR_REG_LPAON_BASE + 0x4000)
#define DR_REG_PMU_BASE (DR_REG_LPAON_BASE + 0x5000)
#define DR_REG_LP_WDT_BASE (DR_REG_LPAON_BASE + 0x6000)
#define DR_REG_LP_MB_BASE (DR_REG_LPAON_BASE + 0x8000)
#define DR_REG_RTC_BASE (DR_REG_LPAON_BASE + 0x9000)
/*
* @module: LP PERI
*
* @base: 0x50120000
*
* @size: 64KB
*/
#define DR_REG_LP_PERI_CLKRST_BASE (DR_REG_LPPERIPH_BASE + 0x0)
#define DR_REG_LP_PERI_BASE (DR_REG_LPPERIPH_BASE + 0x0)
#define DR_REG_LP_UART_BASE (DR_REG_LPPERIPH_BASE + 0x1000)
#define DR_REG_LP_I2C_BASE (DR_REG_LPPERIPH_BASE + 0x2000)
#define DR_REG_LP_SPI_BASE (DR_REG_LPPERIPH_BASE + 0x3000)
#define DR_REG_LP_I2C_MST_BASE (DR_REG_LPPERIPH_BASE + 0x4000)
#define DR_REG_LP_I2S_BASE (DR_REG_LPPERIPH_BASE + 0x5000)
#define DR_REG_LP_ADC_BASE (DR_REG_LPPERIPH_BASE + 0x7000)
#define DR_REG_LP_TOUCH_BASE (DR_REG_LPPERIPH_BASE + 0x8000)
#define DR_REG_LP_GPIO_BASE (DR_REG_LPPERIPH_BASE + 0xA000)
#define DR_REG_LP_INTR_BASE (DR_REG_LPPERIPH_BASE + 0xC000)
#define DR_REG_LP_IOMUX_BASE 0 // just for compile, need remove later
#define DR_REG_EFUSE_BASE (DR_REG_LPPERIPH_BASE + 0xD000)
#define DR_REG_LP_PERI_PMS_BASE (DR_REG_LPPERIPH_BASE + 0xE000)
#define DR_REG_HP2LP_PERI_PMS_BASE (DR_REG_LPPERIPH_BASE + 0xE800)
#define DR_REG_LP_TSENSOR_BASE (DR_REG_LPPERIPH_BASE + 0xF000)
/* this is some module helper MACROs for quick module reference
* including some module(renamed) address
*/
#define DR_REG_UART_BASE DR_REG_UART0_BASE
// ESP32P4-TODO: check this
#define DR_REG_I2C_EXT_BASE 0x60004000
#define DR_REG_UHCI0_BASE DR_REG_UHCI_BASE
#define DR_REG_TIMERGROUP0_BASE DR_REG_TIMG0_BASE
#define DR_REG_TIMERGROUP1_BASE DR_REG_TIMG1_BASE
#define DR_REG_I2S_BASE DR_REG_I2S0_BASE
// ESP32P4-TODO: check this
#define DR_REG_APB_SARADC_BASE 0x6000E000
#define DR_REG_USB_SERIAL_JTAG_BASE DR_REG_USB2JTAG_BASE
#define DR_REG_INTERRUPT_MATRIX_BASE DR_REG_INTR_BASE
// ESP32P4-TODO: check this
#define DR_REG_ATOMIC_BASE 0x60011000
// ESP32P4-TODO: check this
#define DR_REG_SOC_ETM_BASE DR_REG_ETM_BASE
#define DR_REG_MCPWM_BASE DR_REG_MCPWM0_BASE
#define DR_REG_PARL_IO_BASE DR_REG_PARIO_BASE
#define DR_REG_PVT_MONITOR_BASE DR_REG_PVT_BASE
#define DR_REG_AES_BASE (DR_REG_CRYPTO_BASE + 0x0)
#define DR_REG_SHA_BASE (DR_REG_CRYPTO_BASE + 0x1000)
#define DR_REG_RSA_BASE (DR_REG_CRYPTO_BASE + 0x2000)
#define DR_REG_ECC_MULT_BASE (DR_REG_CRYPTO_BASE + 0x3000)
#define DR_REG_DS_BASE (DR_REG_CRYPTO_BASE + 0x4000)
#define DR_REG_DIGITAL_SIGNATURE_BASE DR_REG_DS_BASE
#define DR_REG_HMAC_BASE (DR_REG_CRYPTO_BASE + 0x5000)
#define DR_REG_ECDSA_BASE (DR_REG_CRYPTO_BASE + 0x6000)
// ESP32P4-TODO: check this
#define DR_REG_GPIO_EXT_BASE 0x60091f00 //ESP32C6-TODO
#define DR_REG_MEM_MONITOR_BASE DR_REG_L2MEM_MON_BASE
// ESP32P4-TODO: check this
#define DR_REG_PAU_BASE 0x60093000
// ESP32P4-TODO: check this
#define DR_REG_HP_SYSTEM_BASE 0x60095000
// ESP32P4-TODO: should remove this
#define DR_REG_SYSTEM_BASE DR_REG_HP_SYS_BASE
// ESP32P4-TODO: should remove this
#define DR_REG_RTCCNTL_BASE 0x60008000
// ESP32P4-TODO: should remove this
#define DR_REG_AES_XTS_BASE 0x600CC000
#define DR_REG_PCR_BASE 0x60096000
#define DR_REG_TEE_BASE 0x60098000
#define DR_REG_HP_APM_BASE 0x60099000
#define DR_REG_LP_APM0_BASE 0x60099800
#define DR_REG_MISC_BASE 0x6009F000
#define DR_REG_HP_CLKRST_BASE DR_REG_HP_SYS_CLKRST_BASE
#define DR_REG_DSPI_MEM_BASE (DR_REG_PSRAM_MSPI0_BASE)
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTR_BASE
#define DR_REG_INTERRUPT_CORE1_BASE (DR_REG_INTR_BASE + 0x800)
#define DR_REG_LP_CLKRST_BASE 0x600B0400
#define DR_REG_LP_AON_BASE 0x600B1000
#define DR_REG_LP_IO_BASE 0x600B2000
#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400
#define DR_REG_LPPERI_BASE DR_REG_LP_PERI_CLKRST_BASE
#define DR_REG_LP_ANALOG_PERI_BASE 0x600B2C00
#define DR_REG_LP_TEE_BASE 0x600B3400
#define DR_REG_LP_APM_BASE 0x600B3800
#define DR_REG_OPT_DEBUG_BASE 0x600B3C00
#define DR_REG_TRACE_BASE 0x600C0000
#define DR_REG_ASSIST_DEBUG_BASE 0x3FF06000
#define DR_REG_CPU_BUS_MONITOR_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_bbpll.h
* @brief Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* rtc_clk_cpu_freq_set function in rtc_clk.c.
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
#define I2C_BBPLL_IR_CAL_RSTB 1
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
#define I2C_BBPLL_IR_CAL_START 1
#define I2C_BBPLL_IR_CAL_START_MSB 6
#define I2C_BBPLL_IR_CAL_START_LSB 6
#define I2C_BBPLL_IR_CAL_UNSTOP 1
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
#define I2C_BBPLL_OR_CAL_CAP 8
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
#define I2C_BBPLL_OR_CAL_UDF 8
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
#define I2C_BBPLL_OR_CAL_OVF 8
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
#define I2C_BBPLL_OR_CAL_END 8
#define I2C_BBPLL_OR_CAL_END_MSB 6
#define I2C_BBPLL_OR_CAL_END_LSB 6
#define I2C_BBPLL_OR_LOCK 8
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_OC_VCO_DBIAS 9
#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1
#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_bias.h
* @brief Register definitions for bias
*
* This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
* bootloader_hardware_init function in bootloader_esp32c6.c.
*/
#define I2C_BIAS 0X6A
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_1P1_PVT 1
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
#define I2C_BIAS_DREG_1P1_PVT_LSB 0

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_brownout.h
* @brief Register definitions for brownout detector
*
* This file lists register fields of the brownout detector, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h.
*/
#define I2C_BOD 0x61
#define I2C_BOD_HOSTID 0
#define I2C_BOD_THRESHOLD 0x5
#define I2C_BOD_THRESHOLD_MSB 2
#define I2C_BOD_THRESHOLD_LSB 0

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x600AF818
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
#define ANA_CONFIG_REG 0x600AF81C
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_CONFIG2_REG 0x600AF820
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_dig_reg.h
* @brief Register definitions for digital to get rtc voltage & digital voltage
* by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
*/
#define I2C_DIG_REG 0x6D
#define I2C_DIG_REG_HOSTID 0
#define I2C_DIG_REG_EXT_RTC_DREG 4
#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
#define I2C_DIG_REG_ENX_RTC_DREG 4
#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_ENIF_RTC_DREG 5
#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7
#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7
#define I2C_DIG_REG_EXT_DIG_DREG 6
#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4
#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0
#define I2C_DIG_REG_ENX_DIG_DREG 6
#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7
#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_ENIF_DIG_DREG 7
#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7
#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7
#define I2C_DIG_REG_OR_EN_CONT_CAL 9
#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
#define I2C_DIG_REG_XPD_RTC_REG 13
#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
#define I2C_DIG_REG_XPD_DIG_REG 13
#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
#define I2C_DIG_REG_SCK_DCAP 14
#define I2C_DIG_REG_SCK_DCAP_MSB 7
#define I2C_DIG_REG_SCK_DCAP_LSB 0

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_lp_bias.h
* @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
*
* This file lists register fields of low power dbais, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* rtc_init function in rtc_init.c.
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_IR_FORCE_XPD_CK 0
#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
#define I2C_ULP_IR_FORCE_XPD_IPH 0
#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6
#define I2C_ULP_O_DONE_FLAG 3
#define I2C_ULP_O_DONE_FLAG_MSB 0
#define I2C_ULP_O_DONE_FLAG_LSB 0
#define I2C_ULP_BG_O_DONE_FLAG 3
#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
#define I2C_ULP_OCODE 4
#define I2C_ULP_OCODE_MSB 7
#define I2C_ULP_OCODE_LSB 0
#define I2C_ULP_IR_FORCE_CODE 5
#define I2C_ULP_IR_FORCE_CODE_MSB 6
#define I2C_ULP_IR_FORCE_CODE_LSB 6
#define I2C_ULP_EXT_CODE 6
#define I2C_ULP_EXT_CODE_MSB 7
#define I2C_ULP_EXT_CODE_LSB 0

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_saradc.h
* @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
*
* This file lists register fields of SAR, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* function in adc_ll.h.
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SARADC_DTEST_RTC_ADDR 0x7
#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
#define ADC_SARADC_ENT_TSENS_ADDR 0x7
#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
#define ADC_SARADC_ENT_RTC_ADDR 0x7
#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
// TODO: IDF-5719
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file rtc.h
* @brief Low-level RTC power, clock functions.
*
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
* RTC_CNTL peripheral handles many functions:
* - enables/disables clocks and power to various parts of the chip; this is
* done using direct register access (forcing power up or power down) or by
* allowing state machines to control power and clocks automatically
* - handles sleep and wakeup functions
* - maintains a 48-bit counter which can be used for timekeeping
*
* These functions are not thread safe, and should not be viewed as high level
* APIs. For example, while this file provides a function which can switch
* CPU frequency, this function is on its own is not sufficient to implement
* frequency switching in ESP-IDF context: some coordination with RTOS,
* peripheral drivers, and WiFi/BT stacks is also required.
*
* These functions will normally not be used in applications directly.
* ESP-IDF provides, or will provide, drivers and other facilities to use
* RTC subsystem functionality.
*
* The functions are loosely split into the following groups:
* - rtc_clk: clock switching, calibration
* - rtc_time: reading RTC counter, conversion between counter values and time
*/
#define MHZ (1000000)
#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
#define OTHER_BLOCKS_POWERUP 1
#define OTHER_BLOCKS_WAIT 1
// TODO: IDF-5781
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
*/
#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
#define RTC_CNTL_DBIAS_0V95 16
#define RTC_CNTL_DBIAS_1V00 18
#define RTC_CNTL_DBIAS_1V05 20
#define RTC_CNTL_DBIAS_1V10 23
#define RTC_CNTL_DBIAS_1V15 25
#define RTC_CNTL_DBIAS_1V20 28
#define RTC_CNTL_DBIAS_1V25 30
#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
/* Delays for various clock sources to be enabled/switched.
* All values are in microseconds.
*/
#define SOC_DELAY_RTC_FAST_CLK_SWITCH 3
#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300
#define SOC_DELAY_RC_FAST_ENABLE 50
#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5
#define SOC_DELAY_RC32K_ENABLE 300
/* Core voltage: // TODO: IDF-5781
* Currently, ESP32C6 never adjust its wake voltage in runtime
* Only sets dig/rtc voltage dbias at startup time
*/
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20
#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
/* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
#define RTC_CNTL_MIN_SLP_VAL_MIN (2)
/*
set sleep_init default param
*/
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
/*
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
storing in efuse (based on ATE 5k ECO3 chips)
*/
#define K_RTC_MID_MUL10000 215
#define K_DIG_MID_MUL10000 213
#define V_RTC_MID_MUL10000 10800
#define V_DIG_MID_MUL10000 10860
/**
* @brief Possible main XTAL frequency values.
*
* Enum values should be equal to frequency in MHz.
*/
typedef enum {
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
} rtc_xtal_freq_t;
/**
* @brief CPU clock configuration structure
*/
typedef struct rtc_cpu_freq_config_s {
soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived
uint32_t source_freq_mhz; //!< Source clock frequency
uint32_t div; //!< Divider, freq_mhz = SOC_ROOT_CLK freq_mhz / div
uint32_t freq_mhz; //!< CPU clock frequency
} rtc_cpu_freq_config_t;
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
/**
* @brief Clock source to be calibrated using rtc_clk_cal function
*
* @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL
* However, this is not true on ESP32C6. The conversion to register field values is explicitly done in
* rtc_clk_cal_internal
*/
typedef enum {
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK
RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator
RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock
RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator
} rtc_cal_sel_t;
/**
* Initialization parameters for rtc_clk_init
*/
typedef struct {
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose
uint32_t clk_rtc_clk_div : 8;
uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency)
uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency)
uint32_t clk_8m_dfreq : 8; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency)
uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency)
} rtc_clk_config_t;
/**
* Default initializer for rtc_clk_config_t
*/
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = CONFIG_XTAL_FREQ, \
.cpu_freq_mhz = 80, \
.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
.clk_rtc_clk_div = 0, \
.clk_8m_clk_div = 0, \
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
.rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
}
/**
* Initialize clocks and set CPU frequency
*
* @param cfg clock configuration as rtc_clk_config_t
*/
void rtc_clk_init(rtc_clk_config_t cfg);
/**
* @brief Get main XTAL frequency
*
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
* rtc_clk_init function
*
* @return XTAL frequency, one of rtc_xtal_freq_t
*/
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
/**
* @brief Update XTAL frequency
*
* Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
* after startup.
*
* @param xtal_freq New frequency value
*/
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
/**
* @brief Enable or disable 32 kHz XTAL oscillator
* @param en true to enable, false to disable
*/
void rtc_clk_32k_enable(bool en);
/**
* @brief Configure 32 kHz XTAL oscillator to accept external clock signal
*/
void rtc_clk_32k_enable_external(void);
/**
* @brief Get the state of 32k XTAL oscillator
* @return true if 32k XTAL oscillator has been enabled
*/
bool rtc_clk_32k_enabled(void);
/**
* @brief Enable 32k oscillator, configuring it for fast startup time.
* Note: to achieve higher frequency stability, rtc_clk_32k_enable function
* must be called one the 32k XTAL oscillator has started up. This function
* will initially disable the 32k XTAL oscillator, so it should not be called
* when the system is using 32k XTAL as RTC_SLOW_CLK.
*
* @param cycle Number of 32kHz cycles to bootstrap external crystal.
* If 0, no square wave will be used to bootstrap crystal oscillation.
*/
void rtc_clk_32k_bootstrap(uint32_t cycle);
/**
* @brief Enable or disable 32 kHz internal rc oscillator
* @param en true to enable, false to disable
*/
void rtc_clk_rc32k_enable(bool enable);
/**
* @brief Enable or disable 8 MHz internal oscillator
*
* @param clk_8m_en true to enable 8MHz generator
*/
void rtc_clk_8m_enable(bool clk_8m_en);
/**
* @brief Get the state of 8 MHz internal oscillator
* @return true if the oscillator is enabled
*/
bool rtc_clk_8m_enabled(void);
/**
* @brief Select source for RTC_SLOW_CLK
* @param clk_src clock source (one of soc_rtc_slow_clk_src_t values)
*/
void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src);
/**
* @brief Get the RTC_SLOW_CLK source
* @return currently selected clock source (one of soc_rtc_slow_clk_src_t values)
*/
soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void);
/**
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
*
* - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000
* - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768
* - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768
* - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768
*
* rtc_clk_cal function can be used to get more precise value by comparing
* RTC_SLOW_CLK frequency to the frequency of main XTAL.
*
* @return RTC_SLOW_CLK frequency, in Hz
*/
uint32_t rtc_clk_slow_freq_get_hz(void);
/**
* @brief Select source for RTC_FAST_CLK
* @param clk_src clock source (one of soc_rtc_fast_clk_src_t values)
*/
void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src);
/**
* @brief Get the RTC_FAST_CLK source
* @return currently selected clock source (one of soc_rtc_fast_clk_src_t values)
*/
soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void);
/**
* @brief Get CPU frequency config for a given frequency
* @param freq_mhz Frequency in MHz
* @param[out] out_config Output, CPU frequency configuration structure
* @return true if frequency can be obtained, false otherwise
*/
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config);
/**
* @brief Switch CPU frequency
*
* This function sets CPU frequency according to the given configuration
* structure. It enables PLLs, if necessary.
*
* @note This function in not intended to be called by applications in FreeRTOS
* environment. This is because it does not adjust various timers based on the
* new CPU frequency.
*
* @param config CPU frequency configuration structure
*/
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
/**
* @brief Switch CPU frequency (optimized for speed)
*
* This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
* It works faster because it does not disable PLLs when switching from PLL to
* XTAL and does not enabled them when switching back. If PLL is not already
* enabled when this function is called to switch from XTAL to PLL frequency,
* or the PLL which is enabled is the wrong one, this function will fall back
* to calling rtc_clk_cpu_freq_set_config.
*
* Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
* so it is less safe to use it e.g. from a panic handler (when memory might
* be corrupted).
*
* @note This function in not intended to be called by applications in FreeRTOS
* environment. This is because it does not adjust various timers based on the
* new CPU frequency.
*
* @param config CPU frequency configuration structure
*/
void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
/**
* @brief Get the currently used CPU frequency configuration
* @param[out] out_config Output, CPU frequency configuration structure
*/
void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
/**
* @brief Switch CPU clock source to XTAL
*
* Short form for filling in rtc_cpu_freq_config_t structure and calling
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
* Assumes that XTAL frequency has been determined — don't call in startup code.
*
* @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
* turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
*/
void rtc_clk_cpu_freq_set_xtal(void);
/**
* @brief Get the current APB frequency.
* @return The calculated APB frequency value, in Hz.
*/
uint32_t rtc_clk_apb_freq_get(void);
/**
* @brief Clock calibration function used by rtc_clk_cal
*
* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
* Slow clock calibration feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit.
*
* @param cal_clk which clock to calibrate
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/**
* @brief Measure RTC slow clock's period, based on main XTAL frequency
*
* This function will time out and return 0 if the time for the given number
* of cycles to be counted exceeds the expected time twice. This may happen if
* 32k XTAL is being calibrated, but the oscillator has not started up (due to
* incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
*
* @note When 32k CLK is being calibrated, this function will check the accuracy
* of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if
* the check fails, then consider this an invalid 32k clock and return 0. This
* check can filter some jamming signal.
*
* @param cal_clk clock to be measured
* @param slow_clk_cycles number of slow clock cycles to average
* @return average slow clock period in microseconds, Q13.19 fixed point format,
* or 0 if calibration has timed out
*/
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
/**
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
* @param time_in_us Time interval in microseconds
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
* fixed point format (as returned by rtc_slowck_cali).
* @return number of slow clock cycles
*/
uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
/**
* @brief Convert time interval from RTC_SLOW_CLK to microseconds
* @param time_in_us Time interval in RTC_SLOW_CLK cycles
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
* fixed point format (as returned by rtc_slowck_cali).
* @return time interval in microseconds
*/
uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
/**
* @brief Get current value of RTC counter
*
* RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
* cycles. Counter value is not writable by software. The value is not adjusted
* when switching to a different RTC_SLOW_CLK source.
*
* Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
*
* @return current value of RTC counter
*/
uint64_t rtc_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
*
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle(void);
/**
* @brief Enable the rtc digital 8M clock
*
* This function is used to enable the digital rtc 8M clock to support peripherals.
* For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above.
*/
void rtc_dig_clk8m_enable(void);
/**
* @brief Disable the rtc digital 8M clock
*
* This function is used to disable the digital rtc 8M clock, which is only used to support peripherals.
*/
void rtc_dig_clk8m_disable(void);
/**
* @brief Get whether the rtc digital 8M clock is enabled
*/
bool rtc_dig_8m_enabled(void);
/**
* @brief Calculate the real clock value after the clock calibration
*
* @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal`
* @return Frequency of the clock in Hz
*/
uint32_t rtc_clk_freq_cal(uint32_t cal_val);
// -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
// **WARNING**: The following are only for backwards compatibility.
// Please use the declarations in soc/clk_tree_defs.h instead.
/**
* @brief CPU clock source
*/
typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL
#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M)
#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator
/**
* @brief RTC SLOW_CLK frequency values
*/
typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator
#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL
/**
* @brief RTC FAST_CLK frequency values
*/
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
/* Alias of frequency related macros */
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX
#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX
/* Alias of deprecated function names */
#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq)
#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get()
#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq)
#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get()
#ifdef __cplusplus
}
#endif

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components/soc/esp32p4/include/soc/rtc_io_channel.h Normal file
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 2
#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 3
#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 4
#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 5
#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 6
#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 7

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