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70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* PMS register configuration structure for I/D splitting address.
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* Category bits define the splitting address being below, inside or above specific memory level range:
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* - for details of ESP32S3 memory layout, see 725_mem_map.* documents
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* - for category bits settings, see MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS*
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* (components/hal/include/hal/memprot_types.h)
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* - for details on assembling full splitting address
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* see function memprot_ll_get_split_addr_from_reg() (components/hal/esp32s3/include/hal/memprot_ll.h)
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*/
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typedef union {
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struct {
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uint32_t cat0 : 2; /**< category bits - level 2 */
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uint32_t cat1 : 2; /**< category bits - level 3 */
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uint32_t cat2 : 2; /**< category bits - level 4 */
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uint32_t cat3 : 2; /**< category bits - level 5 */
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uint32_t cat4 : 2; /**< category bits - level 6 */
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uint32_t cat5 : 2; /**< category bits - level 7 */
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uint32_t cat6 : 2; /**< category bits - level 8 */
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uint32_t splitaddr : 8; /**< splitting address significant bits */
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uint32_t reserved : 10;
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};
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uint32_t val;
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} constrain_reg_fields_t;
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#define I_D_SRAM_SEGMENT_SIZE 0x10000
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#define I_D_SPLIT_LINE_ALIGN 0x100
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#define I_D_SPLIT_LINE_SHIFT 0x8
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#define I_FAULT_ADDR_SHIFT 0x2
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#define D_FAULT_ADDR_SHIFT 0x4
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#define IRAM0_VIOLATE_STATUS_ADDR_OFFSET 0x40000000
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#define DRAM0_VIOLATE_STATUS_ADDR_OFFSET 0x3C000000
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//Icache
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#define SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
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#define SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
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#define SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4
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//IRAM0
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4
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//DRAM0
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#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
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#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
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//RTC FAST
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#define SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1
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#define SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2
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#define SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4
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#ifdef __cplusplus
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}
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#endif
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