alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

memprot: Fix incorrect faulting address reported for esp32c3 & esp32s3

Browse Source 
Co-authored-by: Mahavir Jain <mahavir@espressif.com>
This commit is contained in:
Laukik Hase 2023-02-03 11:15:01 +05:30
parent fa27795048
commit 4cf889b692
No known key found for this signature in database
GPG Key ID: 11C571361F51A199
4 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
components/hal/esp32c3/include/hal/memprot_ll.h
View File

@ -300,7 +300,7 @@ static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_world(void)
static inline intptr_t memprot_ll_iram0_get_monitor_status_fault_addr(void)
{
uint32_t addr = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR);
return (intptr_t)(addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0);
return (intptr_t)(addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + IRAM0_VIOLATE_STATUS_ADDR_OFFSET : 0);
}
static inline uint32_t memprot_ll_iram0_get_monitor_status_register(void)
@ -815,7 +815,7 @@ static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_world(void)
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_addr(void)
{
uint32_t addr = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR);
return addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + DRAM0_ADDRESS_LOW : 0;
return addr > 0 ? (addr << I_D_FAULT_ADDR_SHIFT) + DRAM0_VIOLATE_STATUS_ADDR_OFFSET : 0;
}
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_wr(void)

4
components/hal/esp32s3/include/hal/memprot_ll.h
View File

@ -627,7 +627,7 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_addr(c
return MEMP_HAL_ERR_CORE_INVALID;
}
*addr = (void*)(reg_off > 0 ? (reg_off << I_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0);
*addr = (void*)(reg_off > 0 ? (reg_off << I_FAULT_ADDR_SHIFT) + IRAM0_VIOLATE_STATUS_ADDR_OFFSET : 0);
return MEMP_HAL_OK;
}
@ -1646,7 +1646,7 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_addr(c
return MEMP_HAL_ERR_CORE_INVALID;
}
*addr = (void*)(reg_off > 0 ? (reg_off << D_FAULT_ADDR_SHIFT) + DRAM0_ADDRESS_LOW : 0);
*addr = (void*)(reg_off > 0 ? (reg_off << D_FAULT_ADDR_SHIFT) + DRAM0_VIOLATE_STATUS_ADDR_OFFSET : 0);
return MEMP_HAL_OK;
}

3
components/soc/esp32c3/include/soc/memprot_defs.h
View File

@ -35,6 +35,9 @@ typedef union {
#define DRAM_SRAM_START 0x3FC7C000
#define IRAM0_VIOLATE_STATUS_ADDR_OFFSET 0x40000000
#define DRAM0_VIOLATE_STATUS_ADDR_OFFSET 0x3C000000
//IRAM0
//16kB (ICACHE)

3
components/soc/esp32s3/include/soc/memprot_defs.h
View File

@ -42,6 +42,9 @@ typedef union {
#define I_FAULT_ADDR_SHIFT 0x2
#define D_FAULT_ADDR_SHIFT 0x4
#define IRAM0_VIOLATE_STATUS_ADDR_OFFSET 0x40000000
#define DRAM0_VIOLATE_STATUS_ADDR_OFFSET 0x3C000000
//Icache
#define SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
#define SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2