Mahavir Jain e173895618 fix(soc): change debug addr range to CPU subsystem range ... For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same address range is part of CPU Subsystem range which contains debug mode specific code and interrupt config registers (CLINT, PLIC etc.). For now the PMP entry is provided with RWX permission for both machine and user mode but we can save this entry and allow the access to only machine mode for this range. For P4/C5 case, this PMP entry can have RW permission as the debug mode specific code is not present in this memory range.		2024-01-29 13:57:04 +08:00
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port	fix(soc): change debug addr range to CPU subsystem range	2024-01-29 13:57:04 +08:00
gdbstub_transport.c	uart: Support LP_UART port with UART driver on esp32c6	2023-06-16 07:31:40 +00:00
gdbstub.c	esp_gdbstub: fix bp and wp numbers	2023-05-19 20:15:58 +08:00
packet.c	coverity: fix uninit variable issue in driver	2022-08-03 10:46:50 +08:00