mirror of
https://github.com/espressif/esp-idf.git
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364 lines
12 KiB
C
364 lines
12 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: configuration register */
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/** Type of out register
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* LP GPIO output register
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*/
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typedef union {
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struct {
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/** out_data_orig : R/W/WTC; bitpos: [7:0]; default: 0;
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* Configures the output of GPIO0 ~ GPIO7.\\
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* 0: Low level\\
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* 1: High level\\
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* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
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*/
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uint32_t out_data_orig:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_out_reg_t;
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/** Type of out_w1ts register
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* LP GPIO output set register
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*/
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typedef union {
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struct {
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/** out_w1ts : WT; bitpos: [7:0]; default: 0;
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* Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0 ~
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* GPIO7.\\
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*
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* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
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* - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG
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* will be set to 1.
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* - Recommended operation: use this register to set LP_IO_OUT_REG.
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*/
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uint32_t out_w1ts:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_out_w1ts_reg_t;
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/** Type of out_w1tc register
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* LP GPIO output clear register
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*/
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typedef union {
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struct {
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/** out_w1tc : WT; bitpos: [7:0]; default: 0;
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* Configures whether or not to clear the output register LP_IO_OUT_REG of GPIO0 ~
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* GPIO7.\\
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*
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* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
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* - If the value 1 is written to a bit here, the corresponding bit in LP_IO_OUT_REG
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* will be cleared.
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* - Recommended operation: use this register to clear LP_IO_OUT_REG.
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*/
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uint32_t out_w1tc:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_out_w1tc_reg_t;
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/** Type of enable register
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* LP GPIO output enable register
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*/
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typedef union {
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struct {
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/** enable_data : R/W/WTC; bitpos: [7:0]; default: 0;
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* Configures whether or not to enable the output of GPIO0 ~ GPIO7.\\
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* 0: Not enable\\
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* 1: Enable\\
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* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
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*/
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uint32_t enable_data:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_enable_reg_t;
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/** Type of enable_w1ts register
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* LP GPIO output enable set register
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*/
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typedef union {
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struct {
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/** enable_w1ts : WT; bitpos: [7:0]; default: 0;
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* Configures whether or not to set the output enable register LP_IO_ENABLE_REG of
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* GPIO0 ~ GPIO7.\\
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*
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* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* LP_IO_ENABLE_REG will be set to 1.
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* - Recommended operation: use this register to set LP_IO_ENABLE_REG.
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*/
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uint32_t enable_w1ts:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_enable_w1ts_reg_t;
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/** Type of enable_w1tc register
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* LP GPIO output enable clear register
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*/
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typedef union {
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struct {
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/** enable_w1tc : WT; bitpos: [7:0]; default: 0;
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* Configures whether or not to clear the output enable register LP_IO_ENABLE_REG of
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* GPIO0 ~ GPIO7.\\
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*
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* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* LP_IO_ENABLE_REG will be cleared.
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* - Recommended operation: use this register to clear LP_IO_ENABLE_REG.
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*/
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uint32_t enable_w1tc:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_enable_w1tc_reg_t;
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/** Type of in register
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* LP GPIO input register
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*/
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typedef union {
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struct {
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/** in_data_next : RO; bitpos: [7:0]; default: 0;
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* Represents the input value of GPIO0 ~ GPIO7.\\
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* 0: Low level input\\
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* 1: High level input\\
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* bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.\\
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*/
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uint32_t in_data_next:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_in_reg_t;
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/** Type of status register
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* LP GPIO interrupt status register
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*/
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typedef union {
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struct {
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/** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
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* Configures the interrupt status of GPIO0 ~ GPIO7.\\
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* 0: No interrupt\\
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* 1: Interrupt is triggered\\
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* Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc. This
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* register is used together LP_IO_PIN$n_INT_TYPE in register LP_IO_PIN$n_REG.\\
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*/
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uint32_t status_interrupt:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_status_reg_t;
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/** Type of status_w1ts register
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* LP GPIO interrupt status set register
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*/
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typedef union {
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struct {
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/** status_w1ts : WT; bitpos: [7:0]; default: 0;
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* Configures whether or not to set the interrupt status register LP_IO_STATUS_INT of
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* GPIO0 ~ GPIO7.\\
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*
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* - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* LP_IO_STATUS_INT will be set to 1.
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* - Recommended operation: use this register to set LP_IO_STATUS_INT.
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*/
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uint32_t status_w1ts:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_status_w1ts_reg_t;
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/** Type of status_w1tc register
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* LP GPIO interrupt status clear register
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*/
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typedef union {
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struct {
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/** status_w1tc : WT; bitpos: [7:0]; default: 0;
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* Configures whether or not to clear the interrupt status register LP_IO_STATUS_INT
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* of GPIO0 ~ GPIO7. \\
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*
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* - Bit0 is corresponding to GPIO0, bit1 is corresponding to GPIO1, and etc.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* LP_IO_STATUS_INT will be cleared
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* - ecommended operation: use this register to clear LP_IO_STATUS_INT.
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*/
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uint32_t status_w1tc:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_status_w1tc_reg_t;
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/** Type of status_next register
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* LP GPIO interrupt source register
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*/
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typedef union {
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struct {
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/** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
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* Represents the interrupt source status of GPIO0 ~ GPIO7.\\
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* bit0 ~ bit7 are corresponding to GPIO0 ~ 7. Each bit represents:\\
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* 0: Interrupt source status is invalid.\\
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* 1: Interrupt source status is valid.\\
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* The interrupt here can be rising-edge triggered, falling-edge triggered, any edge
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* triggered, or level triggered.\\
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*/
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uint32_t status_interrupt_next:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} lp_gpio_status_next_reg_t;
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/** Type of pinn register
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* LP GPIO0 configuration register
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*/
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typedef union {
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struct {
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/** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of LP IO
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* MUX operating clock for the second-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pinn_sync2_bypass:2;
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/** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
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* Configures to select the pin dirve mode of GPIOn.\\
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* 0: Normal output\\
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* 1: Open drain output\\
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*/
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uint32_t pinn_pad_driver:1;
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/** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of LP IO
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* MUX operating clock for the first-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pinn_sync1_bypass:2;
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/** pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0;
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* Configures whether or not to clear the edge wake-up status of GPIO0 ~ GPIO7.\\
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*
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* - bit0 ~ bit7 are corresponding to GPIO0 ~ GPIO7.
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* - If the value 1 is written to a bit here, the edge wake-up status of corresponding
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* GPIO will be cleared.
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*/
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uint32_t pinn_edge_wakeup_clr:1;
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uint32_t reserved_6:1;
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/** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
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* Configures GPIOn interrupt type.\\
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* 0: GPIO interrupt disabled \\
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* 1: Rising edge trigger \\
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* 2: Falling edge trigger \\
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* 3: Any edge trigger \\
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* 4: Low level trigger \\
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* 5: High level trigger \\
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*/
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uint32_t pinn_int_type:3;
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/** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
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* Configures whether or not to enable GPIOn wake-up function.\\
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* 0: Not enable\\
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* 1: Enable\\
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* This function is disabled when PD_LP_PERI is powered off.\\
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*/
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uint32_t pinn_wakeup_enable:1;
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uint32_t reserved_11:21;
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};
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uint32_t val;
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} lp_gpio_pinn_reg_t;
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/** Type of funcn_out_sel_cfg register
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* Configuration register for GPIO0 output
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*/
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typedef union {
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struct {
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/** funcn_out_inv_sel : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to invert the output value.\\
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* 0: Not invert\\
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* 1: Invert\\
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*/
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uint32_t funcn_out_inv_sel:1;
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uint32_t reserved_1:1;
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/** funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0;
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* Configures whether or not to invert the output enable signal.\\
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* 0: Not invert\\
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* 1: Invert\\
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*/
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uint32_t funcn_oe_inv_sel:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} lp_gpio_funcn_out_sel_cfg_reg_t;
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/** Type of clock_gate register
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* GPIO clock gate register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 1;
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* set this bit to enable GPIO clock gate.\\
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} lp_gpio_clock_gate_reg_t;
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/** Type of date register
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* GPIO version register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 36773904;
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* version register.\\
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} lp_gpio_date_reg_t;
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typedef struct {
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uint32_t reserved_000;
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volatile lp_gpio_out_reg_t out;
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volatile lp_gpio_out_w1ts_reg_t out_w1ts;
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volatile lp_gpio_out_w1tc_reg_t out_w1tc;
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volatile lp_gpio_enable_reg_t enable;
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volatile lp_gpio_enable_w1ts_reg_t enable_w1ts;
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volatile lp_gpio_enable_w1tc_reg_t enable_w1tc;
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volatile lp_gpio_in_reg_t in;
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volatile lp_gpio_status_reg_t status;
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volatile lp_gpio_status_w1ts_reg_t status_w1ts;
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volatile lp_gpio_status_w1tc_reg_t status_w1tc;
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volatile lp_gpio_status_next_reg_t status_next;
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volatile lp_gpio_pinn_reg_t pinn[8];
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uint32_t reserved_050[152];
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volatile lp_gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[8];
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uint32_t reserved_2d0[74];
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volatile lp_gpio_clock_gate_reg_t clock_gate;
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volatile lp_gpio_date_reg_t date;
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} lp_gpio_dev_t;
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extern lp_gpio_dev_t LP_GPIO;
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#ifndef __cplusplus
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_Static_assert(sizeof(lp_gpio_dev_t) == 0x400, "Invalid size of lp_gpio_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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