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remove(c5beta3): remove c5 beta3 soc files

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This commit is contained in:
laokaiyao 2024-06-11 15:23:36 +08:00
parent b4b1906d2c
commit 717a2ccf15
353 changed files with 2185 additions and 124541 deletions
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2
.codespellrc
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@ -1,4 +1,4 @@
[codespell]
skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*
ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot
ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane
write-changes = true

8
components/soc/CMakeLists.txt
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@ -1,12 +1,6 @@
idf_build_get_property(target IDF_TARGET)
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
set(target_folder "esp32c5/beta3")
elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
set(target_folder "esp32c5/mp")
else()
set(target_folder "${target}")
endif()
set(target_folder "${target}")
# On Linux the soc component is a simple wrapper, without much functionality
if(NOT ${target} STREQUAL "linux")

121
components/soc/esp32c5/beta3/gdma_periph.c
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@ -1,121 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gdma_periph.h"
#include "soc/gdma_reg.h"
const gdma_signal_conn_t gdma_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_GDMA_MODULE,
.pairs = {
[0] = {
.rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE,
.tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE,
},
[1] = {
.rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE,
.tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE,
},
[2] = {
.rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE,
.tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE,
}
}
}
}
};
#if SOC_GDMA_SUPPORT_SLEEP_RETENTION
/* GDMA Channel (Group0, Pair0) Registers Context
Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
*/
#define G0P0_RETENTION_REGS_CNT_0 13
#define G0P0_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH0_REG
#define G0P0_RETENTION_REGS_CNT_1 2
#define G0P0_RETENTION_MAP_BASE_1 GDMA_BT_TX_SEL_REG
static const uint32_t g0p0_regs_map0[4] = {0x4C801001, 0x604C0060, 0, 0};
static const uint32_t g0p0_regs_map1[4] = {0x3, 0, 0, 0};
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
g0p0_regs_map0[0], g0p0_regs_map0[1], \
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
g0p0_regs_map1[0], g0p0_regs_map1[1], \
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
.owner = ENTRY(0) | ENTRY(2) },
};
/* GDMA Channel (Group0, Pair1) Registers Context
Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
*/
#define G0P1_RETENTION_REGS_CNT_0 13
#define G0P1_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH1_REG
#define G0P1_RETENTION_REGS_CNT_1 2
#define G0P1_RETENTION_MAP_BASE_1 GDMA_BT_TX_SEL_REG
static const uint32_t g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604};
static const uint32_t g0p1_regs_map1[4] = {0x3, 0, 0, 0};
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
g0p1_regs_map0[0], g0p1_regs_map0[1], \
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
g0p1_regs_map1[0], g0p1_regs_map1[1], \
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
.owner = ENTRY(0) | ENTRY(2) },
};
/* GDMA Channel (Group0, Pair2) Registers Context
Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
*/
#define G0P2_RETENTION_REGS_CNT_0 6
#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
#define G0P2_RETENTION_REGS_CNT_1 9
#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
static const uint32_t g0p2_regs_map1[4] = {0xf026003, 0, 0, 0};
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
g0p2_regs_map0[0], g0p2_regs_map0[1], \
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
.owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
g0p2_regs_map1[0], g0p2_regs_map1[1], \
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
.owner = ENTRY(0) | ENTRY(2) },
};
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
[0] = {
[0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)},
[1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)},
[2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)}
}
};
#endif

41
components/soc/esp32c5/beta3/gpio_periph.c
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@ -1,41 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_periph.h"
_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
const uint32_t GPIO_HOLD_MASK[] = {
BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG
BIT(1), //GPIO1
BIT(2), //GPIO2
BIT(3), //GPIO3
BIT(4), //GPIO4
BIT(5), //GPIO5
BIT(6), //GPIO6
BIT(7), //GPIO7
BIT(8), //GPIO8
BIT(9), //GPIO9
BIT(10), //GPIO10
BIT(11), //GPIO11
BIT(12), //GPIO12
BIT(13), //GPIO13
BIT(14), //GPIO14
BIT(15), //GPIO15
BIT(16), //GPIO16
BIT(17), //GPIO17
BIT(18), //GPIO18
BIT(19), //GPIO19
BIT(20), //GPIO20
BIT(21), //GPIO21
BIT(22), //GPIO22
BIT(23), //GPIO23
BIT(24), //GPIO24
BIT(25), //GPIO25
BIT(26), //GPIO26
};
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

22
components/soc/esp32c5/beta3/i2c_periph.c
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@ -1,22 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
.module = PERIPH_I2C0_MODULE,
},
};

12
components/soc/esp32c5/beta3/ieee802154_periph.c
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@ -1,12 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ieee802154_periph.h"
const ieee802154_conn_t ieee802154_periph = {
.module = PERIPH_IEEE802154_MODULE,
.irq_id = ETS_ZB_MAC_INTR_SOURCE,
};

164
components/soc/esp32c5/beta3/include/modem/modem_syscon_struct.h
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@ -1,164 +0,0 @@
/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t clk_en : 1;
uint32_t modem_ant_force_sel_bt : 1;
uint32_t modem_ant_force_sel_wifi : 1;
uint32_t reserved3 : 29;
};
uint32_t val;
} test_conf;
union {
struct {
uint32_t reserved0 : 21;
uint32_t clk_data_dump_mux : 1;
uint32_t clk_etm_en : 1;
uint32_t clk_zb_apb_en : 1;
uint32_t clk_zbmac_en : 1;
uint32_t clk_modem_sec_ecb_en : 1;
uint32_t clk_modem_sec_ccm_en : 1;
uint32_t clk_modem_sec_bah_en : 1;
uint32_t clk_modem_sec_apb_en : 1;
uint32_t clk_modem_sec_en : 1;
uint32_t clk_ble_timer_en : 1;
uint32_t clk_data_dump_en : 1;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t clk_wifibb_fo : 1;
uint32_t clk_wifimac_fo : 1;
uint32_t clk_wifi_apb_fo : 1;
uint32_t clk_fe_fo : 1;
uint32_t clk_fe_apb_fo : 1;
uint32_t clk_btbb_fo : 1;
uint32_t clk_btmac_fo : 1;
uint32_t clk_bt_apb_fo : 1;
uint32_t clk_zbmac_fo : 1;
uint32_t clk_zbmac_apb_fo : 1;
uint32_t reserved10 : 13;
uint32_t reserved23 : 1;
uint32_t reserved24 : 1;
uint32_t reserved25 : 1;
uint32_t reserved26 : 1;
uint32_t reserved27 : 1;
uint32_t clk_etm_fo : 1;
uint32_t clk_modem_sec_fo : 1;
uint32_t clk_ble_timer_fo : 1;
uint32_t clk_data_dump_fo : 1;
};
uint32_t val;
} clk_conf_force_on;
union {
struct {
uint32_t reserved0 : 8;
uint32_t clk_zb_st_map : 4;
uint32_t clk_fe_st_map : 4;
uint32_t clk_bt_st_map : 4;
uint32_t clk_wifi_st_map : 4;
uint32_t clk_modem_peri_st_map : 4;
uint32_t clk_modem_apb_st_map : 4;
};
uint32_t val;
} clk_conf_power_st;
union {
struct {
uint32_t reserved0 : 1;
uint32_t reserved1 : 1;
uint32_t reserved2 : 1;
uint32_t reserved3 : 1;
uint32_t reserved4 : 1;
uint32_t reserved5 : 1;
uint32_t reserved6 : 1;
uint32_t reserved7 : 1;
uint32_t rst_wifibb : 1;
uint32_t rst_wifimac : 1;
uint32_t rst_fe_pwdet_adc : 1;
uint32_t rst_fe_dac : 1;
uint32_t rst_fe_adc : 1;
uint32_t rst_fe_ahb : 1;
uint32_t rst_fe : 1;
uint32_t rst_btmac_apb : 1;
uint32_t rst_btmac : 1;
uint32_t rst_btbb_apb : 1;
uint32_t rst_btbb : 1;
uint32_t reserved19 : 3;
uint32_t rst_etm : 1;
uint32_t reserved23 : 1;
uint32_t rst_zbmac : 1;
uint32_t rst_modem_ecb : 1;
uint32_t rst_modem_ccm : 1;
uint32_t rst_modem_bah : 1;
uint32_t reserved28 : 1;
uint32_t rst_modem_sec : 1;
uint32_t rst_ble_timer : 1;
uint32_t rst_data_dump : 1;
};
uint32_t val;
} modem_rst_conf;
union {
struct {
uint32_t clk_wifibb_22m_en : 1;
uint32_t clk_wifibb_40m_en : 1;
uint32_t clk_wifibb_44m_en : 1;
uint32_t clk_wifibb_80m_en : 1;
uint32_t clk_wifibb_40x_en : 1;
uint32_t clk_wifibb_80x_en : 1;
uint32_t clk_wifibb_40x1_en : 1;
uint32_t clk_wifibb_80x1_en : 1;
uint32_t clk_wifibb_160x1_en : 1;
uint32_t clk_wifimac_en : 1;
uint32_t clk_wifi_apb_en : 1;
uint32_t clk_fe_20m_en : 1;
uint32_t clk_fe_40m_en : 1;
uint32_t clk_fe_80m_en : 1;
uint32_t clk_fe_160m_en : 1;
uint32_t clk_fe_apb_en : 1;
uint32_t clk_bt_apb_en : 1;
uint32_t clk_btbb_en : 1;
uint32_t clk_btmac_en : 1;
uint32_t clk_fe_pwdet_adc_en : 1;
uint32_t clk_fe_adc_en : 1;
uint32_t clk_fe_dac_en : 1;
uint32_t reserved22 : 1;
uint32_t reserved23 : 1;
uint32_t reserved24 : 8;
};
uint32_t val;
} clk_conf1;
uint32_t wifi_bb_cfg;
uint32_t mem_rf1_conf;
uint32_t mem_rf2_conf;
union {
struct {
uint32_t date : 28;
uint32_t reserved28 : 4;
};
uint32_t val;
} date;
} modem_syscon_dev_t;
extern modem_syscon_dev_t MODEM_SYSCON;
#ifndef __cplusplus
_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

9
components/soc/esp32c5/beta3/include/modem/reg_base.h
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@ -1,9 +0,0 @@
/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define DR_REG_MODEM_SYSCON_BASE 0x600A9800
#define DR_REG_MODEM_LPCON_BASE 0x600AF000

872
components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
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@ -1,872 +0,0 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_UART_SUPPORTED
bool
default y
config SOC_GDMA_SUPPORTED
bool
default y
config SOC_AHB_GDMA_SUPPORTED
bool
default y
config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_PCNT_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_PHY_SUPPORTED
bool
default y
config SOC_WIFI_SUPPORTED
bool
default y
config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
config SOC_EFUSE_SUPPORTED
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_IEEE802154_SUPPORTED
bool
default y
config SOC_RMT_SUPPORTED
bool
default y
config SOC_GPSPI_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
config SOC_AES_SUPPORTED
bool
default y
config SOC_MPI_SUPPORTED
bool
default y
config SOC_SHA_SUPPORTED
bool
default y
config SOC_RSA_SUPPORTED
bool
default y
config SOC_HMAC_SUPPORTED
bool
default y
config SOC_DIG_SIGN_SUPPORTED
bool
default y
config SOC_ECC_SUPPORTED
bool
default y
config SOC_ECC_EXTENDED_MODES_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_SECURE_BOOT_SUPPORTED
bool
default y
config SOC_PMU_SUPPORTED
bool
default y
config SOC_PAU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
bool
default y
config SOC_LP_AON_SUPPORTED
bool
default y
config SOC_LP_PERIPHERALS_SUPPORTED
bool
default y
config SOC_ULP_SUPPORTED
bool
default y
config SOC_LP_CORE_SUPPORTED
bool
default y
config SOC_SPI_FLASH_SUPPORTED
bool
default y
config SOC_ECDSA_SUPPORTED
bool
default y
config SOC_LIGHT_SLEEP_SUPPORTED
bool
default y
config SOC_MODEM_CLOCK_SUPPORTED
bool
default y
config SOC_BT_SUPPORTED
bool
default y
config SOC_PM_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_40M
bool
default y
config SOC_XTAL_SUPPORT_48M
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_GDMA
bool
default y
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 7
config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
config SOC_CACHE_FREEZE_SUPPORTED
bool
default y
config SOC_CPU_CORES_NUM
int
default 1
config SOC_CPU_INTR_NUM
int
default 32
config SOC_CPU_HAS_FLEXIBLE_INTC
bool
default y
config SOC_INT_CLIC_SUPPORTED
bool
default y
config SOC_INT_HW_NESTED_SUPPORTED
bool
default y
config SOC_BRANCH_PREDICTOR_SUPPORTED
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 4
config SOC_CPU_WATCHPOINTS_NUM
int
default 4
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex
default 0x100
config SOC_CPU_HAS_PMA
bool
default y
config SOC_CPU_IDRAM_SPLIT_USING_PMP
bool
default y
config SOC_DS_SIGNATURE_MAX_BIT_LEN
int
default 3072
config SOC_DS_KEY_PARAM_MD_IV_LENGTH
int
default 16
config SOC_DS_KEY_CHECK_MAX_WAIT_US
int
default 1100
config SOC_AHB_GDMA_VERSION
int
default 1
config SOC_GDMA_NUM_GROUPS_MAX
int
default 1
config SOC_GDMA_PAIRS_PER_GROUP_MAX
int
default 3
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 27
config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
default y
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 26
config SOC_GPIO_OUT_RANGE_MAX
int
default 26
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x0000000007FFFF00
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_RTCIO_PIN_COUNT
int
default 0
config SOC_I2C_NUM
int
default 1
config SOC_HP_I2C_NUM
int
default 1
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_CMD_REG_NUM
int
default 8
config SOC_I2C_SUPPORT_SLAVE
bool
default y
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_10BIT_ADDR
bool
default y
config SOC_I2C_SLAVE_SUPPORT_BROADCAST
bool
default y
config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
bool
default y
config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6
config SOC_MMU_PERIPH_NUM
int
default 1
config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
int
default 1
config SOC_MMU_DI_VADDR_SHARED
bool
default y
config SOC_PCNT_GROUPS
int
default 1
config SOC_PCNT_UNITS_PER_GROUP
int
default 4
config SOC_PCNT_CHANNELS_PER_UNIT
int
default 2
config SOC_PCNT_THRES_POINT_PER_UNIT
int
default 2
config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
bool
default y
config SOC_PCNT_SUPPORT_CLEAR_SIGNAL
bool
default y
config SOC_RMT_GROUPS
int
default 1
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_CHANNELS_PER_GROUP
int
default 4
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
default 48
config SOC_RMT_SUPPORT_RX_PINGPONG
bool
default y
config SOC_RMT_SUPPORT_RX_DEMODULATION
bool
default y
config SOC_RMT_SUPPORT_TX_ASYNC_STOP
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
bool
default y
config SOC_RMT_SUPPORT_TX_SYNCHRO
bool
default y
config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
bool
default y
config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_MPI_MEM_BLOCKS_NUM
int
default 4
config SOC_MPI_OPERATIONS_NUM
int
default 3
config SOC_RSA_MAX_BIT_LEN
int
default 3072
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2
config SOC_SPI_MAX_CS_NUM
int
default 6
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 256
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2
config SOC_SYSTIMER_ALARM_NUM
int
default 3
config SOC_SYSTIMER_BIT_WIDTH_LO
int
default 32
config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_DIVIDER
bool
default y
config SOC_SYSTIMER_SUPPORT_RC_FAST
bool
default y
config SOC_SYSTIMER_INT_LEVEL
bool
default y
config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_TIMER_GROUPS
int
default 2
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
int
default 1
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 54
config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y
config SOC_SECURE_BOOT_V2_ECC
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 64
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
config SOC_UART_NUM
int
default 3
config SOC_UART_HP_NUM
int
default 2
config SOC_UART_LP_NUM
int
default 1
config SOC_UART_FIFO_LEN
int
default 128
config SOC_LP_UART_FIFO_LEN
int
default 16
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_PLL_F80M_CLK
bool
default y
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_HAS_LP_UART
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_UART_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_COEX_HW_PTI
bool
default y
config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int
default 12
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_MODEM_PD
bool
default y
config SOC_PM_SUPPORT_XTAL32K_PD
bool
default y
config SOC_PM_SUPPORT_RC32K_PD
bool
default y
config SOC_PM_SUPPORT_RC_FAST_PD
bool
default y
config SOC_PM_SUPPORT_VDDSDIO_PD
bool
default y
config SOC_PM_SUPPORT_TOP_PD
bool
default y
config SOC_PM_SUPPORT_HP_AON_PD
bool
default y
config SOC_PM_SUPPORT_RTC_PERIPH_PD
bool
default y
config SOC_PM_SUPPORT_PMU_MODEM_STATE
bool
default n
config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
bool
default y
config SOC_PM_CPU_RETENTION_BY_SW
bool
default y
config SOC_PM_MODEM_RETENTION_BY_REGDMA
bool
default y
config SOC_PM_PAU_LINK_NUM
int
default 4
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool
default y
config SOC_MODEM_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_CLK_XTAL32K_SUPPORTED
bool
default y
config SOC_CLK_OSC_SLOW_SUPPORTED
bool
default y
config SOC_CLK_RC32K_SUPPORTED
bool
default y
config SOC_RCC_IS_INDEPENDENT
bool
default y
config SOC_WIFI_HW_TSF
bool
default y
config SOC_WIFI_FTM_SUPPORT
bool
default n
config SOC_WIFI_GCMP_SUPPORT
bool
default y
config SOC_WIFI_WAPI_SUPPORT
bool
default y
config SOC_WIFI_CSI_SUPPORT
bool
default y
config SOC_WIFI_MESH_SUPPORT
bool
default y
config SOC_WIFI_HE_SUPPORT
bool
default y
config SOC_WIFI_HE_SUPPORT_5G
bool
default y
config SOC_BLE_SUPPORTED
bool
default y
config SOC_BLE_MESH_SUPPORTED
bool
default y
config SOC_ESP_NIMBLE_CONTROLLER
bool
default y
config SOC_BLE_50_SUPPORTED
bool
default y
config SOC_BLE_DEVICE_PRIVACY_SUPPORTED
bool
default y
config SOC_BLE_POWER_CONTROL_SUPPORTED
bool
default y
config SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED
bool
default y
config SOC_BLUFI_SUPPORTED
bool
default y
config SOC_BLE_MULTI_CONN_OPTIMIZATION
bool
default y

368
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@ -1,368 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* Key material key_0 configure register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* Key material key_1 configure register
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_1 that is a part of key material.
*/
#define AES_KEY_1 0xFFFFFFFFU
#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S)
#define AES_KEY_1_V 0xFFFFFFFFU
#define AES_KEY_1_S 0
/** AES_KEY_2_REG register
* Key material key_2 configure register
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_2 that is a part of key material.
*/
#define AES_KEY_2 0xFFFFFFFFU
#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S)
#define AES_KEY_2_V 0xFFFFFFFFU
#define AES_KEY_2_S 0
/** AES_KEY_3_REG register
* Key material key_3 configure register
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_3 that is a part of key material.
*/
#define AES_KEY_3 0xFFFFFFFFU
#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S)
#define AES_KEY_3_V 0xFFFFFFFFU
#define AES_KEY_3_S 0
/** AES_KEY_4_REG register
* Key material key_4 configure register
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_4 that is a part of key material.
*/
#define AES_KEY_4 0xFFFFFFFFU
#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S)
#define AES_KEY_4_V 0xFFFFFFFFU
#define AES_KEY_4_S 0
/** AES_KEY_5_REG register
* Key material key_5 configure register
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_5 that is a part of key material.
*/
#define AES_KEY_5 0xFFFFFFFFU
#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S)
#define AES_KEY_5_V 0xFFFFFFFFU
#define AES_KEY_5_S 0
/** AES_KEY_6_REG register
* Key material key_6 configure register
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_6 that is a part of key material.
*/
#define AES_KEY_6 0xFFFFFFFFU
#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S)
#define AES_KEY_6_V 0xFFFFFFFFU
#define AES_KEY_6_S 0
/** AES_KEY_7_REG register
* Key material key_7 configure register
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_7 that is a part of key material.
*/
#define AES_KEY_7 0xFFFFFFFFU
#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S)
#define AES_KEY_7_V 0xFFFFFFFFU
#define AES_KEY_7_S 0
/** AES_TEXT_IN_0_REG register
* source text material text_in_0 configure register
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* source text material text_in_1 configure register
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_1 that is a part of source text material.
*/
#define AES_TEXT_IN_1 0xFFFFFFFFU
#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S)
#define AES_TEXT_IN_1_V 0xFFFFFFFFU
#define AES_TEXT_IN_1_S 0
/** AES_TEXT_IN_2_REG register
* source text material text_in_2 configure register
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_2 that is a part of source text material.
*/
#define AES_TEXT_IN_2 0xFFFFFFFFU
#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S)
#define AES_TEXT_IN_2_V 0xFFFFFFFFU
#define AES_TEXT_IN_2_S 0
/** AES_TEXT_IN_3_REG register
* source text material text_in_3 configure register
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_3 that is a part of source text material.
*/
#define AES_TEXT_IN_3 0xFFFFFFFFU
#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S)
#define AES_TEXT_IN_3_V 0xFFFFFFFFU
#define AES_TEXT_IN_3_S 0
/** AES_TEXT_OUT_0_REG register
* result text material text_out_0 configure register
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* result text material text_out_1 configure register
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_1 that is a part of result text material.
*/
#define AES_TEXT_OUT_1 0xFFFFFFFFU
#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S)
#define AES_TEXT_OUT_1_V 0xFFFFFFFFU
#define AES_TEXT_OUT_1_S 0
/** AES_TEXT_OUT_2_REG register
* result text material text_out_2 configure register
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_2 that is a part of result text material.
*/
#define AES_TEXT_OUT_2 0xFFFFFFFFU
#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S)
#define AES_TEXT_OUT_2_V 0xFFFFFFFFU
#define AES_TEXT_OUT_2_S 0
/** AES_TEXT_OUT_3_REG register
* result text material text_out_3 configure register
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_3 that is a part of result text material.
*/
#define AES_TEXT_OUT_3 0xFFFFFFFFU
#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S)
#define AES_TEXT_OUT_3_V 0xFFFFFFFFU
#define AES_TEXT_OUT_3_S 0
/** AES_MODE_REG register
* AES Mode register
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_TRIGGER_REG register
* AES trigger register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Set this bit to start AES calculation.
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* AES state register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
* idle, 1: busy, 2: calculation_done.
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* DMA-AES working mode register
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* AES cipher block mode register
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* AES block number register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of Plaintext/ciphertext block.
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function configure register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_INT_CLEAR_REG register
* AES Interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the AES interrupt.
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* AES Interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x3FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x3FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* AES-DMA exit config
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Set this register to leave calculation done stage. Recommend to use it after
* software finishes reading DMA's output buffer.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
#ifdef __cplusplus
}
#endif

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@ -1,438 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: key register */
/** Type of key_0 register
* Key material key_0 configure register
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_0_reg_t;
/** Type of key_1 register
* Key material key_1 configure register
*/
typedef union {
struct {
/** key_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_1 that is a part of key material.
*/
uint32_t key_1:32;
};
uint32_t val;
} aes_key_1_reg_t;
/** Type of key_2 register
* Key material key_2 configure register
*/
typedef union {
struct {
/** key_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_2 that is a part of key material.
*/
uint32_t key_2:32;
};
uint32_t val;
} aes_key_2_reg_t;
/** Type of key_3 register
* Key material key_3 configure register
*/
typedef union {
struct {
/** key_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_3 that is a part of key material.
*/
uint32_t key_3:32;
};
uint32_t val;
} aes_key_3_reg_t;
/** Type of key_4 register
* Key material key_4 configure register
*/
typedef union {
struct {
/** key_4 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_4 that is a part of key material.
*/
uint32_t key_4:32;
};
uint32_t val;
} aes_key_4_reg_t;
/** Type of key_5 register
* Key material key_5 configure register
*/
typedef union {
struct {
/** key_5 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_5 that is a part of key material.
*/
uint32_t key_5:32;
};
uint32_t val;
} aes_key_5_reg_t;
/** Type of key_6 register
* Key material key_6 configure register
*/
typedef union {
struct {
/** key_6 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_6 that is a part of key material.
*/
uint32_t key_6:32;
};
uint32_t val;
} aes_key_6_reg_t;
/** Type of key_7 register
* Key material key_7 configure register
*/
typedef union {
struct {
/** key_7 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_7 that is a part of key material.
*/
uint32_t key_7:32;
};
uint32_t val;
} aes_key_7_reg_t;
/** Group: text in register */
/** Type of text_in_0 register
* source text material text_in_0 configure register
*/
typedef union {
struct {
/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
uint32_t text_in_0:32;
};
uint32_t val;
} aes_text_in_0_reg_t;
/** Type of text_in_1 register
* source text material text_in_1 configure register
*/
typedef union {
struct {
/** text_in_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_1 that is a part of source text material.
*/
uint32_t text_in_1:32;
};
uint32_t val;
} aes_text_in_1_reg_t;
/** Type of text_in_2 register
* source text material text_in_2 configure register
*/
typedef union {
struct {
/** text_in_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_2 that is a part of source text material.
*/
uint32_t text_in_2:32;
};
uint32_t val;
} aes_text_in_2_reg_t;
/** Type of text_in_3 register
* source text material text_in_3 configure register
*/
typedef union {
struct {
/** text_in_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_3 that is a part of source text material.
*/
uint32_t text_in_3:32;
};
uint32_t val;
} aes_text_in_3_reg_t;
/** Group: text out register */
/** Type of text_out_0 register
* result text material text_out_0 configure register
*/
typedef union {
struct {
/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
uint32_t text_out_0:32;
};
uint32_t val;
} aes_text_out_0_reg_t;
/** Type of text_out_1 register
* result text material text_out_1 configure register
*/
typedef union {
struct {
/** text_out_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_1 that is a part of result text material.
*/
uint32_t text_out_1:32;
};
uint32_t val;
} aes_text_out_1_reg_t;
/** Type of text_out_2 register
* result text material text_out_2 configure register
*/
typedef union {
struct {
/** text_out_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_2 that is a part of result text material.
*/
uint32_t text_out_2:32;
};
uint32_t val;
} aes_text_out_2_reg_t;
/** Type of text_out_3 register
* result text material text_out_3 configure register
*/
typedef union {
struct {
/** text_out_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_3 that is a part of result text material.
*/
uint32_t text_out_3:32;
};
uint32_t val;
} aes_text_out_3_reg_t;
/** Group: Configuration register */
/** Type of mode register
* AES Mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_mode_reg_t;
/** Type of block_mode register
* AES cipher block mode register
*/
typedef union {
struct {
/** block_mode : R/W; bitpos: [2:0]; default: 0;
* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
*/
uint32_t block_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_block_mode_reg_t;
/** Type of block_num register
* AES block number register
*/
typedef union {
struct {
/** block_num : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of Plaintext/ciphertext block.
*/
uint32_t block_num:32;
};
uint32_t val;
} aes_block_num_reg_t;
/** Type of inc_sel register
* Standard incrementing function configure register
*/
typedef union {
struct {
/** inc_sel : R/W; bitpos: [0]; default: 0;
* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
*/
uint32_t inc_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_inc_sel_reg_t;
/** Group: Control/Status register */
/** Type of trigger register
* AES trigger register
*/
typedef union {
struct {
/** trigger : WT; bitpos: [0]; default: 0;
* Set this bit to start AES calculation.
*/
uint32_t trigger:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_trigger_reg_t;
/** Type of state register
* AES state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
* idle, 1: busy, 2: calculation_done.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} aes_state_reg_t;
/** Type of dma_enable register
* DMA-AES working mode register
*/
typedef union {
struct {
/** dma_enable : R/W; bitpos: [0]; default: 0;
* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
*/
uint32_t dma_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of dma_exit register
* AES-DMA exit config
*/
typedef union {
struct {
/** dma_exit : WT; bitpos: [0]; default: 0;
* Set this register to leave calculation done stage. Recommend to use it after
* software finishes reading DMA's output buffer.
*/
uint32_t dma_exit:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_exit_reg_t;
/** Group: memory type */
/** Group: interrupt register */
/** Type of int_clear register
* AES Interrupt clear register
*/
typedef union {
struct {
/** int_clear : WT; bitpos: [0]; default: 0;
* Set this bit to clear the AES interrupt.
*/
uint32_t int_clear:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_clear_reg_t;
/** Type of int_ena register
* AES Interrupt enable register
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_ena_reg_t;
/** Group: Version control register */
/** Type of date register
* AES version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538513936;
* This bits stores the version information of AES.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} aes_date_reg_t;
typedef struct aes_dev_t {
volatile aes_key_0_reg_t key_0;
volatile aes_key_1_reg_t key_1;
volatile aes_key_2_reg_t key_2;
volatile aes_key_3_reg_t key_3;
volatile aes_key_4_reg_t key_4;
volatile aes_key_5_reg_t key_5;
volatile aes_key_6_reg_t key_6;
volatile aes_key_7_reg_t key_7;
volatile aes_text_in_0_reg_t text_in_0;
volatile aes_text_in_1_reg_t text_in_1;
volatile aes_text_in_2_reg_t text_in_2;
volatile aes_text_in_3_reg_t text_in_3;
volatile aes_text_out_0_reg_t text_out_0;
volatile aes_text_out_1_reg_t text_out_1;
volatile aes_text_out_2_reg_t text_out_2;
volatile aes_text_out_3_reg_t text_out_3;
volatile aes_mode_reg_t mode;
uint32_t reserved_044;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
volatile uint32_t h[4];
volatile uint32_t j0[4];
volatile uint32_t t0[4];
volatile aes_dma_enable_reg_t dma_enable;
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
uint32_t reserved_0a0[3];
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
volatile aes_dma_exit_reg_t dma_exit;
} aes_dev_t;
extern aes_dev_t AES;
#ifndef __cplusplus
_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

813
components/soc/esp32c5/beta3/include/soc/apb_saradc_reg.h
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@ -1,813 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** APB_SARADC_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
#define APB_SARADC_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U
#define APB_SARADC_SARADC_START_FORCE_S 0
/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
#define APB_SARADC_SARADC_START (BIT(1))
#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
#define APB_SARADC_SARADC_START_V 0x00000001U
#define APB_SARADC_SARADC_START_S 1
/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U
#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6
/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU
#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7
/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U
#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15
/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U
#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23
/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U
#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27
/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
#define APB_SARADC_SARADC2_PWDET_DRV (BIT(29))
#define APB_SARADC_SARADC2_PWDET_DRV_M (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
#define APB_SARADC_SARADC2_PWDET_DRV_V 0x00000001U
#define APB_SARADC_SARADC2_PWDET_DRV_S 29
/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U
#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30
/** APB_SARADC_CTRL2_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U
#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0
/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU
#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1
/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR1_INV_S 9
/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
#define APB_SARADC_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U
#define APB_SARADC_SARADC_SAR2_INV_S 10
/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU
#define APB_SARADC_SARADC_TIMER_TARGET_S 12
/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
#define APB_SARADC_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U
#define APB_SARADC_SARADC_TIMER_EN_S 24
/** APB_SARADC_FILTER_CTRL1_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S 26
/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V 0x00000007U
#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S 29
/** APB_SARADC_SAR_PATT_TAB1_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0
/** APB_SARADC_SAR_PATT_TAB2_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU
#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0
/** APB_SARADC_ONETIME_SAMPLE_REG register
* digital saradc configure register
*/
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U
#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23
/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU
#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25
/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
#define APB_SARADC_SARADC_ONETIME_START (BIT(29))
#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U
#define APB_SARADC_SARADC_ONETIME_START_S 29
/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30))
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30
/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31))
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U
#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31
/** APB_SARADC_ARB_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/** APB_SARADC_FILTER_CTRL0_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28)
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S 18
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V 0x0000000FU
#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S 22
/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
#define APB_SARADC_APB_SARADC_FILTER_RESET (BIT(31))
#define APB_SARADC_APB_SARADC_FILTER_RESET_M (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
#define APB_SARADC_APB_SARADC_FILTER_RESET_V 0x00000001U
#define APB_SARADC_APB_SARADC_FILTER_RESET_S 31
/** APB_SARADC_SAR1DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c)
/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
#define APB_SARADC_APB_SARADC1_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_M (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
#define APB_SARADC_APB_SARADC1_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC1_DATA_S 0
/** APB_SARADC_SAR2DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30)
/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
#define APB_SARADC_APB_SARADC2_DATA 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_M (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
#define APB_SARADC_APB_SARADC2_DATA_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC2_DATA_S 0
/** APB_SARADC_THRES0_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34)
/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_M (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_M (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES0_LOW_S 18
/** APB_SARADC_THRES1_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V 0x0000000FU
#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S 0
/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_M (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_HIGH_S 5
/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_M (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_V 0x00001FFFU
#define APB_SARADC_APB_SARADC_THRES1_LOW_S 18
/** APB_SARADC_THRES_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c)
/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
#define APB_SARADC_APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S 27
/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
#define APB_SARADC_APB_SARADC_THRES1_EN (BIT(30))
#define APB_SARADC_APB_SARADC_THRES1_EN_M (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
#define APB_SARADC_APB_SARADC_THRES1_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_EN_S 30
/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
#define APB_SARADC_APB_SARADC_THRES0_EN (BIT(31))
#define APB_SARADC_APB_SARADC_THRES0_EN_M (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
#define APB_SARADC_APB_SARADC_THRES0_EN_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_EN_S 31
/** APB_SARADC_INT_ENA_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40)
/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S 31
/** APB_SARADC_INT_RAW_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44)
/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S 31
/** APB_SARADC_INT_ST_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48)
/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_ST (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S 31
/** APB_SARADC_INT_CLR_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c)
/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR (BIT(25))
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S 25
/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S 26
/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S 27
/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S 28
/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S 29
/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S 30
/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S 31
/** APB_SARADC_DMA_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50)
/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_M (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
#define APB_SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x00000001U
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
#define APB_SARADC_APB_ADC_TRANS_V 0x00000001U
#define APB_SARADC_APB_ADC_TRANS_S 31
/** APB_SARADC_CLKM_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54)
/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_M (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
#define APB_SARADC_CLKM_DIV_NUM_V 0x000000FFU
#define APB_SARADC_CLKM_DIV_NUM_S 0
/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
#define APB_SARADC_CLKM_DIV_B 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_M (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
#define APB_SARADC_CLKM_DIV_B_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_B_S 8
/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
#define APB_SARADC_CLKM_DIV_A 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_M (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
#define APB_SARADC_CLKM_DIV_A_V 0x0000003FU
#define APB_SARADC_CLKM_DIV_A_S 14
/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
#define APB_SARADC_CLK_EN_V 0x00000001U
#define APB_SARADC_CLK_EN_S 20
/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
#define APB_SARADC_CLK_SEL 0x00000003U
#define APB_SARADC_CLK_SEL_M (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
#define APB_SARADC_CLK_SEL_V 0x00000003U
#define APB_SARADC_CLK_SEL_S 21
/** APB_SARADC_APB_TSENS_CTRL_REG register
* digital tsens configure register
*/
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
#define APB_SARADC_TSENS_OUT 0x000000FFU
#define APB_SARADC_TSENS_OUT_M (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
#define APB_SARADC_TSENS_OUT_V 0x000000FFU
#define APB_SARADC_TSENS_OUT_S 0
/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
#define APB_SARADC_TSENS_IN_INV (BIT(13))
#define APB_SARADC_TSENS_IN_INV_M (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
#define APB_SARADC_TSENS_IN_INV_V 0x00000001U
#define APB_SARADC_TSENS_IN_INV_S 13
/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
#define APB_SARADC_TSENS_CLK_DIV 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_M (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
#define APB_SARADC_TSENS_CLK_DIV_V 0x000000FFU
#define APB_SARADC_TSENS_CLK_DIV_S 14
/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
#define APB_SARADC_TSENS_PU (BIT(22))
#define APB_SARADC_TSENS_PU_M (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
#define APB_SARADC_TSENS_PU_V 0x00000001U
#define APB_SARADC_TSENS_PU_S 22
/** APB_SARADC_TSENS_CTRL2_REG register
* digital tsens configure register
*/
#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c)
/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
#define APB_SARADC_TSENS_CLK_SEL_M (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
#define APB_SARADC_TSENS_CLK_SEL_V 0x00000001U
#define APB_SARADC_TSENS_CLK_SEL_S 15
/** APB_SARADC_CALI_REG register
* digital saradc configure register
*/
#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60)
/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
#define APB_SARADC_APB_SARADC_CALI_CFG 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_M (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
#define APB_SARADC_APB_SARADC_CALI_CFG_V 0x0001FFFFU
#define APB_SARADC_APB_SARADC_CALI_CFG_S 0
/** APB_TSENS_WAKE_REG register
* digital tsens configure register
*/
#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64)
/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
#define APB_SARADC_WAKEUP_TH_LOW 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_M (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
#define APB_SARADC_WAKEUP_TH_LOW_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_LOW_S 0
/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
#define APB_SARADC_WAKEUP_TH_HIGH 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_M (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
#define APB_SARADC_WAKEUP_TH_HIGH_V 0x000000FFU
#define APB_SARADC_WAKEUP_TH_HIGH_S 8
/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
#define APB_SARADC_WAKEUP_OVER_UPPER_TH (BIT(16))
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U
#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S 16
/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
#define APB_SARADC_WAKEUP_MODE (BIT(17))
#define APB_SARADC_WAKEUP_MODE_M (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
#define APB_SARADC_WAKEUP_MODE_V 0x00000001U
#define APB_SARADC_WAKEUP_MODE_S 17
/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
#define APB_SARADC_WAKEUP_EN (BIT(18))
#define APB_SARADC_WAKEUP_EN_M (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
#define APB_SARADC_WAKEUP_EN_V 0x00000001U
#define APB_SARADC_WAKEUP_EN_S 18
/** APB_TSENS_SAMPLE_REG register
* digital tsens configure register
*/
#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68)
/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
#define APB_SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_M (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
#define APB_SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU
#define APB_SARADC_TSENS_SAMPLE_RATE_S 0
/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
#define APB_SARADC_TSENS_SAMPLE_EN (BIT(16))
#define APB_SARADC_TSENS_SAMPLE_EN_M (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
#define APB_SARADC_TSENS_SAMPLE_EN_V 0x00000001U
#define APB_SARADC_TSENS_SAMPLE_EN_S 16
/** APB_SARADC_CTRL_DATE_REG register
* version
*/
#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
#define APB_SARADC_DATE 0xFFFFFFFFU
#define APB_SARADC_DATE_M (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
#define APB_SARADC_DATE_V 0xFFFFFFFFU
#define APB_SARADC_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/apb_saradc_struct.h
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@ -1,696 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Register */
/** Type of saradc_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
uint32_t saradc_saradc_start_force:1;
/** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
* software enable saradc sample
*/
uint32_t saradc_saradc_start:1;
uint32_t reserved_2:4;
/** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
* SAR clock gated
*/
uint32_t saradc_saradc_sar_clk_gated:1;
/** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
* SAR clock divider
*/
uint32_t saradc_saradc_sar_clk_div:8;
/** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
* 0 ~ 15 means length 1 ~ 16
*/
uint32_t saradc_saradc_sar_patt_len:3;
uint32_t reserved_18:5;
/** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
* clear the pointer of pattern table for DIG ADC1 CTRL
*/
uint32_t saradc_saradc_sar_patt_p_clear:1;
uint32_t reserved_24:3;
/** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
* force option to xpd sar blocks
*/
uint32_t saradc_saradc_xpd_sar_force:2;
/** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
* enable saradc2 power detect driven func.
*/
uint32_t saradc_saradc2_pwdet_drv:1;
/** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
* wait arbit signal stable after sar_done
*/
uint32_t saradc_saradc_wait_arb_cycle:2;
};
uint32_t val;
} apb_saradc_ctrl_reg_t;
/** Type of saradc_ctrl2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
uint32_t saradc_saradc_meas_num_limit:1;
/** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
* max conversion number
*/
uint32_t saradc_saradc_max_meas_num:8;
/** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar1_inv:1;
/** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
*/
uint32_t saradc_saradc_sar2_inv:1;
uint32_t reserved_11:1;
/** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
* to set saradc timer target
*/
uint32_t saradc_saradc_timer_target:12;
/** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
* to enable saradc timer trigger
*/
uint32_t saradc_saradc_timer_en:1;
uint32_t reserved_25:7;
};
uint32_t val;
} apb_saradc_ctrl2_reg_t;
/** Type of saradc_filter_ctrl1 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
uint32_t saradc_apb_saradc_filter_factor1:3;
/** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
* Factor of saradc filter0
*/
uint32_t saradc_apb_saradc_filter_factor0:3;
};
uint32_t val;
} apb_saradc_filter_ctrl1_reg_t;
/** Type of saradc_sar_patt_tab1 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab1_reg_t;
/** Type of saradc_sar_patt_tab2 register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
uint32_t saradc_saradc_sar_patt_tab2:24;
uint32_t reserved_24:8;
};
uint32_t val;
} apb_saradc_sar_patt_tab2_reg_t;
/** Type of saradc_onetime_sample register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
uint32_t saradc_saradc_onetime_atten:2;
/** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
* configure onetime channel
*/
uint32_t saradc_saradc_onetime_channel:4;
/** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
* trigger adc onetime sample
*/
uint32_t saradc_saradc_onetime_start:1;
/** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
* enable adc2 onetime sample
*/
uint32_t saradc_saradc2_onetime_sample:1;
/** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
* enable adc1 onetime sample
*/
uint32_t saradc_saradc1_onetime_sample:1;
};
uint32_t val;
} apb_saradc_onetime_sample_reg_t;
/** Type of saradc_arb_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
uint32_t saradc_adc_arb_apb_force:1;
/** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
* adc2 arbiter force to enable rtc controller
*/
uint32_t saradc_adc_arb_rtc_force:1;
/** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
* adc2 arbiter force to enable wifi controller
*/
uint32_t saradc_adc_arb_wifi_force:1;
/** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
* adc2 arbiter force grant
*/
uint32_t saradc_adc_arb_grant_force:1;
/** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
* Set adc2 arbiterapb priority
*/
uint32_t saradc_adc_arb_apb_priority:2;
/** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
* Set adc2 arbiter rtc priority
*/
uint32_t saradc_adc_arb_rtc_priority:2;
/** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
* Set adc2 arbiter wifi priority
*/
uint32_t saradc_adc_arb_wifi_priority:2;
/** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
* adc2 arbiter uses fixed priority
*/
uint32_t saradc_adc_arb_fix_priority:1;
uint32_t reserved_13:19;
};
uint32_t val;
} apb_saradc_arb_ctrl_reg_t;
/** Type of saradc_filter_ctrl0 register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:18;
/** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel1:4;
/** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
* configure filter0 to adc channel
*/
uint32_t saradc_apb_saradc_filter_channel0:4;
uint32_t reserved_26:5;
/** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
* enable apb_adc1_filter
*/
uint32_t saradc_apb_saradc_filter_reset:1;
};
uint32_t val;
} apb_saradc_filter_ctrl0_reg_t;
/** Type of saradc_sar1data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
uint32_t saradc_apb_saradc1_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar1data_status_reg_t;
/** Type of saradc_sar2data_status register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
uint32_t saradc_apb_saradc2_data:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_sar2data_status_reg_t;
/** Type of saradc_thres0_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
uint32_t saradc_apb_saradc_thres0_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_high:13;
/** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres0 monitor thres
*/
uint32_t saradc_apb_saradc_thres0_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres0_ctrl_reg_t;
/** Type of saradc_thres1_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
uint32_t saradc_apb_saradc_thres1_channel:4;
uint32_t reserved_4:1;
/** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_high:13;
/** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
* saradc thres1 monitor thres
*/
uint32_t saradc_apb_saradc_thres1_low:13;
uint32_t reserved_31:1;
};
uint32_t val;
} apb_saradc_thres1_ctrl_reg_t;
/** Type of saradc_thres_ctrl register
* digital saradc configure register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
uint32_t saradc_apb_saradc_thres_all_en:1;
uint32_t reserved_28:2;
/** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
* enable thres1
*/
uint32_t saradc_apb_saradc_thres1_en:1;
/** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
* enable thres0
*/
uint32_t saradc_apb_saradc_thres0_en:1;
};
uint32_t val;
} apb_saradc_thres_ctrl_reg_t;
/** Type of saradc_int_ena register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
uint32_t saradc_apb_saradc_tsens_int_ena:1;
/** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
* saradc thres1 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
/** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
* saradc thres0 low interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
/** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
* saradc thres1 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
/** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
* saradc thres0 high interrupt enable
*/
uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
/** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
* saradc2 done interrupt enable
*/
uint32_t saradc_apb_saradc2_done_int_ena:1;
/** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
* saradc1 done interrupt enable
*/
uint32_t saradc_apb_saradc1_done_int_ena:1;
};
uint32_t val;
} apb_saradc_int_ena_reg_t;
/** Type of saradc_int_raw register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
uint32_t saradc_apb_saradc_tsens_int_raw:1;
/** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
* saradc thres1 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
/** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* saradc thres0 low interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
/** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* saradc thres1 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
/** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* saradc thres0 high interrupt raw
*/
uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
/** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* saradc2 done interrupt raw
*/
uint32_t saradc_apb_saradc2_done_int_raw:1;
/** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* saradc1 done interrupt raw
*/
uint32_t saradc_apb_saradc1_done_int_raw:1;
};
uint32_t val;
} apb_saradc_int_raw_reg_t;
/** Type of saradc_int_st register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
uint32_t saradc_apb_saradc_tsens_int_st:1;
/** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
* saradc thres1 low interrupt state
*/
uint32_t saradc_apb_saradc_thres1_low_int_st:1;
/** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
* saradc thres0 low interrupt state
*/
uint32_t saradc_apb_saradc_thres0_low_int_st:1;
/** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
* saradc thres1 high interrupt state
*/
uint32_t saradc_apb_saradc_thres1_high_int_st:1;
/** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
* saradc thres0 high interrupt state
*/
uint32_t saradc_apb_saradc_thres0_high_int_st:1;
/** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
* saradc2 done interrupt state
*/
uint32_t saradc_apb_saradc2_done_int_st:1;
/** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
* saradc1 done interrupt state
*/
uint32_t saradc_apb_saradc1_done_int_st:1;
};
uint32_t val;
} apb_saradc_int_st_reg_t;
/** Type of saradc_int_clr register
* digital saradc int register
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
uint32_t saradc_apb_saradc_tsens_int_clr:1;
/** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
* saradc thres1 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
/** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
* saradc thres0 low interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
/** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
* saradc thres1 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
/** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
* saradc thres0 high interrupt clear
*/
uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
/** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
* saradc2 done interrupt clear
*/
uint32_t saradc_apb_saradc2_done_int_clr:1;
/** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
* saradc1 done interrupt clear
*/
uint32_t saradc_apb_saradc1_done_int_clr:1;
};
uint32_t val;
} apb_saradc_int_clr_reg_t;
/** Type of saradc_dma_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
uint32_t saradc_apb_adc_eof_num:16;
uint32_t reserved_16:14;
/** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
* reset_apb_adc_state
*/
uint32_t saradc_apb_adc_reset_fsm:1;
/** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
* enable apb_adc use spi_dma
*/
uint32_t saradc_apb_adc_trans:1;
};
uint32_t val;
} apb_saradc_dma_conf_reg_t;
/** Type of saradc_clkm_conf register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
uint32_t saradc_clkm_div_num:8;
/** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
* Fractional clock divider numerator value
*/
uint32_t saradc_clkm_div_b:6;
/** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
* Fractional clock divider denominator value
*/
uint32_t saradc_clkm_div_a:6;
/** saradc_clk_en : R/W; bitpos: [20]; default: 0;
* reg clk en
*/
uint32_t saradc_clk_en:1;
/** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
* Set this bit to enable clk_apll
*/
uint32_t saradc_clk_sel:2;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_clkm_conf_reg_t;
/** Type of saradc_apb_tsens_ctrl register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
uint32_t saradc_tsens_out:8;
uint32_t reserved_8:5;
/** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
* invert temperature sensor data
*/
uint32_t saradc_tsens_in_inv:1;
/** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
* temperature sensor clock divider
*/
uint32_t saradc_tsens_clk_div:8;
/** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
* temperature sensor power up
*/
uint32_t saradc_tsens_pu:1;
uint32_t reserved_23:9;
};
uint32_t val;
} apb_saradc_apb_tsens_ctrl_reg_t;
/** Type of saradc_tsens_ctrl2 register
* digital tsens configure register
*/
typedef union {
struct {
uint32_t reserved_0:15;
/** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
uint32_t saradc_tsens_clk_sel:1;
uint32_t reserved_16:16;
};
uint32_t val;
} apb_saradc_tsens_ctrl2_reg_t;
/** Type of saradc_cali register
* digital saradc configure register
*/
typedef union {
struct {
/** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
uint32_t saradc_apb_saradc_cali_cfg:17;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_saradc_cali_reg_t;
/** Type of tsens_wake register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
uint32_t saradc_wakeup_th_low:8;
/** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
* reg_wakeup_th_high
*/
uint32_t saradc_wakeup_th_high:8;
/** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
* reg_wakeup_over_upper_th
*/
uint32_t saradc_wakeup_over_upper_th:1;
/** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
* reg_wakeup_mode
*/
uint32_t saradc_wakeup_mode:1;
/** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
* reg_wakeup_en
*/
uint32_t saradc_wakeup_en:1;
uint32_t reserved_19:13;
};
uint32_t val;
} apb_tsens_wake_reg_t;
/** Type of tsens_sample register
* digital tsens configure register
*/
typedef union {
struct {
/** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
uint32_t saradc_tsens_sample_rate:16;
/** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
* HW sample en
*/
uint32_t saradc_tsens_sample_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} apb_tsens_sample_reg_t;
/** Type of saradc_ctrl_date register
* version
*/
typedef union {
struct {
/** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
* version
*/
uint32_t saradc_date:32;
};
uint32_t val;
} apb_saradc_ctrl_date_reg_t;
typedef struct apb_dev_t {
volatile apb_saradc_ctrl_reg_t saradc_ctrl;
volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
uint32_t reserved_00c[3];
volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
volatile apb_saradc_int_ena_reg_t saradc_int_ena;
volatile apb_saradc_int_raw_reg_t saradc_int_raw;
volatile apb_saradc_int_st_reg_t saradc_int_st;
volatile apb_saradc_int_clr_reg_t saradc_int_clr;
volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
volatile apb_saradc_cali_reg_t saradc_cali;
volatile apb_tsens_wake_reg_t tsens_wake;
volatile apb_tsens_sample_reg_t tsens_sample;
uint32_t reserved_06c[228];
volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
} apb_dev_t;
extern apb_dev_t APB_SARADC;
#ifndef __cplusplus
_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

582
components/soc/esp32c5/beta3/include/soc/assist_debug_reg.h
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@ -1,582 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register
* core0 monitor enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
* core0 monitor interrupt status register
*/
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt status
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
* core0 monitor interrupt enable register
*/
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
* core0 monitor interrupt clr register
*/
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt clr
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
* core0 dram0 region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region0 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
* core0 dram0 region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region0 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
* core0 dram0 region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region1 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
* core0 dram0 region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region1 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
* core0 PIF region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region0 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
* core0 PIF region0 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region0 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
* core0 PIF region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region1 start addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
* core0 PIF region1 addr configuration register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region1 end addr
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
* core0 area pc status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
* the stackpointer when first touch region monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
* core0 area sp status register
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
* the PC when first touch region monitor interrupt
*/
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
* stack min value
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
* core0 sp region configuration regsiter
*/
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
* stack max value
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
* core0 sp pc status register
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
* stack monitor pc status register
*/
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
* This regsiter stores the PC when trigger stack monitor.
*/
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
* record enable configuration register
*/
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
* Set 1 to enable record PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
* record status regsiter
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
* recorded PC
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
* record status regsiter
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
* recorded sp
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
* cpu's lastpc before exception
*/
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
* cpu debug mode status, 1 means cpu enter debug mode.
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
* cpu debug_module active status
*/
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
/** ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG register
* cpu status register
*/
#define ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
/** ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0;
* need desc
*/
#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE (BIT(0))
#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_M (ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V << ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S)
#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V 0x00000001U
#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S 0
/** ASSIST_DEBUG_CLOCK_GATE_REG register
* clock register
*/
#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7c)
/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Set 1 force on the clock gate
*/
#define ASSIST_DEBUG_CLK_EN (BIT(0))
#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
#define ASSIST_DEBUG_CLK_EN_V 0x00000001U
#define ASSIST_DEBUG_CLK_EN_S 0
/** ASSIST_DEBUG_DATE_REG register
* version register
*/
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 35725648;
* version register
*/
#define ASSIST_DEBUG_DATE 0x0FFFFFFFU
#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
#define ASSIST_DEBUG_DATE_S 0
#ifdef __cplusplus
}
#endif

549
components/soc/esp32c5/beta3/include/soc/assist_debug_struct.h
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@ -1,549 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: monitor configuration registers */
/** Type of core_0_montr_ena register
* core0 monitor enable configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor enable
*/
uint32_t core_0_area_dram0_0_rd_ena:1;
/** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor enable
*/
uint32_t core_0_area_dram0_0_wr_ena:1;
/** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor enable
*/
uint32_t core_0_area_dram0_1_rd_ena:1;
/** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor enable
*/
uint32_t core_0_area_dram0_1_wr_ena:1;
/** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor enable
*/
uint32_t core_0_area_pif_0_rd_ena:1;
/** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor enable
*/
uint32_t core_0_area_pif_0_wr_ena:1;
/** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor enable
*/
uint32_t core_0_area_pif_1_rd_ena:1;
/** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor enable
*/
uint32_t core_0_area_pif_1_wr_ena:1;
/** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor enable
*/
uint32_t core_0_sp_spill_min_ena:1;
/** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor enable
*/
uint32_t core_0_sp_spill_max_ena:1;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_montr_ena_reg_t;
/** Type of core_0_area_dram0_0_min register
* core0 dram0 region0 addr configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region0 start addr
*/
uint32_t core_0_area_dram0_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_min_reg_t;
/** Type of core_0_area_dram0_0_max register
* core0 dram0 region0 addr configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region0 end addr
*/
uint32_t core_0_area_dram0_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_0_max_reg_t;
/** Type of core_0_area_dram0_1_min register
* core0 dram0 region1 addr configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 dram0 region1 start addr
*/
uint32_t core_0_area_dram0_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_min_reg_t;
/** Type of core_0_area_dram0_1_max register
* core0 dram0 region1 addr configuration register
*/
typedef union {
struct {
/** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
* Core0 dram0 region1 end addr
*/
uint32_t core_0_area_dram0_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_dram0_1_max_reg_t;
/** Type of core_0_area_pif_0_min register
* core0 PIF region0 addr configuration register
*/
typedef union {
struct {
/** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region0 start addr
*/
uint32_t core_0_area_pif_0_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_min_reg_t;
/** Type of core_0_area_pif_0_max register
* core0 PIF region0 addr configuration register
*/
typedef union {
struct {
/** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region0 end addr
*/
uint32_t core_0_area_pif_0_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_0_max_reg_t;
/** Type of core_0_area_pif_1_min register
* core0 PIF region1 addr configuration register
*/
typedef union {
struct {
/** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
* Core0 PIF region1 start addr
*/
uint32_t core_0_area_pif_1_min:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_min_reg_t;
/** Type of core_0_area_pif_1_max register
* core0 PIF region1 addr configuration register
*/
typedef union {
struct {
/** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
* Core0 PIF region1 end addr
*/
uint32_t core_0_area_pif_1_max:32;
};
uint32_t val;
} assist_debug_core_0_area_pif_1_max_reg_t;
/** Type of core_0_area_pc register
* core0 area pc status register
*/
typedef union {
struct {
/** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
* the stackpointer when first touch region monitor interrupt
*/
uint32_t core_0_area_pc:32;
};
uint32_t val;
} assist_debug_core_0_area_pc_reg_t;
/** Type of core_0_area_sp register
* core0 area sp status register
*/
typedef union {
struct {
/** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
* the PC when first touch region monitor interrupt
*/
uint32_t core_0_area_sp:32;
};
uint32_t val;
} assist_debug_core_0_area_sp_reg_t;
/** Type of core_0_sp_min register
* stack min value
*/
typedef union {
struct {
/** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
* core0 sp region configuration regsiter
*/
uint32_t core_0_sp_min:32;
};
uint32_t val;
} assist_debug_core_0_sp_min_reg_t;
/** Type of core_0_sp_max register
* stack max value
*/
typedef union {
struct {
/** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
* core0 sp pc status register
*/
uint32_t core_0_sp_max:32;
};
uint32_t val;
} assist_debug_core_0_sp_max_reg_t;
/** Type of core_0_sp_pc register
* stack monitor pc status register
*/
typedef union {
struct {
/** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
* This regsiter stores the PC when trigger stack monitor.
*/
uint32_t core_0_sp_pc:32;
};
uint32_t val;
} assist_debug_core_0_sp_pc_reg_t;
/** Group: interrupt configuration register */
/** Type of core_0_intr_raw register
* core0 monitor interrupt status register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt status
*/
uint32_t core_0_area_dram0_0_rd_raw:1;
/** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt status
*/
uint32_t core_0_area_dram0_0_wr_raw:1;
/** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt status
*/
uint32_t core_0_area_dram0_1_rd_raw:1;
/** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt status
*/
uint32_t core_0_area_dram0_1_wr_raw:1;
/** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt status
*/
uint32_t core_0_area_pif_0_rd_raw:1;
/** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt status
*/
uint32_t core_0_area_pif_0_wr_raw:1;
/** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt status
*/
uint32_t core_0_area_pif_1_rd_raw:1;
/** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt status
*/
uint32_t core_0_area_pif_1_wr_raw:1;
/** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt status
*/
uint32_t core_0_sp_spill_min_raw:1;
/** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt status
*/
uint32_t core_0_sp_spill_max_raw:1;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_raw_reg_t;
/** Type of core_0_intr_ena register
* core0 monitor interrupt enable register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt enable
*/
uint32_t core_0_area_dram0_0_rd_intr_ena:1;
/** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt enable
*/
uint32_t core_0_area_dram0_0_wr_intr_ena:1;
/** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt enable
*/
uint32_t core_0_area_dram0_1_rd_intr_ena:1;
/** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt enable
*/
uint32_t core_0_area_dram0_1_wr_intr_ena:1;
/** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt enable
*/
uint32_t core_0_area_pif_0_rd_intr_ena:1;
/** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt enable
*/
uint32_t core_0_area_pif_0_wr_intr_ena:1;
/** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt enable
*/
uint32_t core_0_area_pif_1_rd_intr_ena:1;
/** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt enable
*/
uint32_t core_0_area_pif_1_wr_intr_ena:1;
/** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt enable
*/
uint32_t core_0_sp_spill_min_intr_ena:1;
/** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt enable
*/
uint32_t core_0_sp_spill_max_intr_ena:1;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_ena_reg_t;
/** Type of core_0_intr_clr register
* core0 monitor interrupt clr register
*/
typedef union {
struct {
/** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
* Core0 dram0 area0 read monitor interrupt clr
*/
uint32_t core_0_area_dram0_0_rd_clr:1;
/** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
* Core0 dram0 area0 write monitor interrupt clr
*/
uint32_t core_0_area_dram0_0_wr_clr:1;
/** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
* Core0 dram0 area1 read monitor interrupt clr
*/
uint32_t core_0_area_dram0_1_rd_clr:1;
/** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
* Core0 dram0 area1 write monitor interrupt clr
*/
uint32_t core_0_area_dram0_1_wr_clr:1;
/** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
* Core0 PIF area0 read monitor interrupt clr
*/
uint32_t core_0_area_pif_0_rd_clr:1;
/** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
* Core0 PIF area0 write monitor interrupt clr
*/
uint32_t core_0_area_pif_0_wr_clr:1;
/** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
* Core0 PIF area1 read monitor interrupt clr
*/
uint32_t core_0_area_pif_1_rd_clr:1;
/** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
* Core0 PIF area1 write monitor interrupt clr
*/
uint32_t core_0_area_pif_1_wr_clr:1;
/** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
* Core0 stackpoint underflow monitor interrupt clr
*/
uint32_t core_0_sp_spill_min_clr:1;
/** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
* Core0 stackpoint overflow monitor interrupt clr
*/
uint32_t core_0_sp_spill_max_clr:1;
uint32_t reserved_10:22;
};
uint32_t val;
} assist_debug_core_0_intr_clr_reg_t;
/** Group: pc reording configuration register */
/** Type of core_0_rcd_en register
* record enable configuration register
*/
typedef union {
struct {
/** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
* Set 1 to enable record PC
*/
uint32_t core_0_rcd_recorden:1;
/** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
* Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
*/
uint32_t core_0_rcd_pdebugen:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_rcd_en_reg_t;
/** Group: pc reording status register */
/** Type of core_0_rcd_pdebugpc register
* record status regsiter
*/
typedef union {
struct {
/** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
* recorded PC
*/
uint32_t core_0_rcd_pdebugpc:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugpc_reg_t;
/** Type of core_0_rcd_pdebugsp register
* record status regsiter
*/
typedef union {
struct {
/** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
* recorded sp
*/
uint32_t core_0_rcd_pdebugsp:32;
};
uint32_t val;
} assist_debug_core_0_rcd_pdebugsp_reg_t;
/** Group: cpu status registers */
/** Type of core_0_lastpc_before_exception register
* cpu status register
*/
typedef union {
struct {
/** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
* cpu's lastpc before exception
*/
uint32_t core_0_lastpc_before_exc:32;
};
uint32_t val;
} assist_debug_core_0_lastpc_before_exception_reg_t;
/** Type of core_0_debug_mode register
* cpu status register
*/
typedef union {
struct {
/** core_0_debug_mode : RO; bitpos: [0]; default: 0;
* cpu debug mode status, 1 means cpu enter debug mode.
*/
uint32_t core_0_debug_mode:1;
/** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
* cpu debug_module active status
*/
uint32_t core_0_debug_module_active:1;
uint32_t reserved_2:30;
};
uint32_t val;
} assist_debug_core_0_debug_mode_reg_t;
/** Type of core_0_dmactive_mode register
* cpu status register
*/
typedef union {
struct {
/** core_0_dmactive_lpcore : RO; bitpos: [0]; default: 0;
* need desc
*/
uint32_t core_0_dmactive_lpcore:1;
uint32_t reserved_1:31;
};
uint32_t val;
} assist_debug_core_0_dmactive_mode_reg_t;
/** Group: Configuration Registers */
/** Type of clock_gate register
* clock register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 force on the clock gate
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} assist_debug_clock_gate_reg_t;
/** Type of date register
* version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725648;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} assist_debug_date_reg_t;
typedef struct assist_debug_dev_t {
volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
uint32_t reserved_050[8];
volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
volatile assist_debug_core_0_dmactive_mode_reg_t core_0_dmactive_mode;
volatile assist_debug_clock_gate_reg_t clock_gate;
uint32_t reserved_080[223];
volatile assist_debug_date_reg_t date;
} assist_debug_dev_t;
extern assist_debug_dev_t ASSIST_DEBUG;
#ifndef __cplusplus
_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/bitscrambler_reg.h
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@ -1,481 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** BITSCRAMBLER_TX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_TX_INST_IDX 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_M (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
#define BITSCRAMBLER_TX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_TX_INST_IDX_S 0
/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_TX_INST_POS 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_M (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
#define BITSCRAMBLER_TX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_TX_INST_POS_S 3
/** BITSCRAMBLER_TX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
#define BITSCRAMBLER_TX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_M (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
#define BITSCRAMBLER_TX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_INST_S 0
/** BITSCRAMBLER_RX_INST_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
#define BITSCRAMBLER_RX_INST_IDX 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_M (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
#define BITSCRAMBLER_RX_INST_IDX_V 0x00000007U
#define BITSCRAMBLER_RX_INST_IDX_S 0
/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
#define BITSCRAMBLER_RX_INST_POS 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_M (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
#define BITSCRAMBLER_RX_INST_POS_V 0x0000000FU
#define BITSCRAMBLER_RX_INST_POS_S 3
/** BITSCRAMBLER_RX_INST_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
#define BITSCRAMBLER_RX_INST 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_M (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
#define BITSCRAMBLER_RX_INST_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_INST_S 0
/** BITSCRAMBLER_TX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
#define BITSCRAMBLER_TX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_M (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
#define BITSCRAMBLER_TX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_TX_LUT_IDX_S 0
/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_TX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_M (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
#define BITSCRAMBLER_TX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_TX_LUT_MODE_S 11
/** BITSCRAMBLER_TX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_TX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_M (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
#define BITSCRAMBLER_TX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_TX_LUT_S 0
/** BITSCRAMBLER_RX_LUT_CFG0_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
#define BITSCRAMBLER_RX_LUT_IDX 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_M (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
#define BITSCRAMBLER_RX_LUT_IDX_V 0x000007FFU
#define BITSCRAMBLER_RX_LUT_IDX_S 0
/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
#define BITSCRAMBLER_RX_LUT_MODE 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_M (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
#define BITSCRAMBLER_RX_LUT_MODE_V 0x00000003U
#define BITSCRAMBLER_RX_LUT_MODE_S 11
/** BITSCRAMBLER_RX_LUT_CFG1_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
#define BITSCRAMBLER_RX_LUT 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_M (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
#define BITSCRAMBLER_RX_LUT_V 0xFFFFFFFFU
#define BITSCRAMBLER_RX_LUT_S 0
/** BITSCRAMBLER_TX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_TX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_M (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
#define BITSCRAMBLER_TX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_TX_TAILING_BITS_S 0
/** BITSCRAMBLER_RX_TAILING_BITS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
#define BITSCRAMBLER_RX_TAILING_BITS 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_M (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
#define BITSCRAMBLER_RX_TAILING_BITS_V 0x0000FFFFU
#define BITSCRAMBLER_RX_TAILING_BITS_S 0
/** BITSCRAMBLER_TX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
#define BITSCRAMBLER_TX_ENA (BIT(0))
#define BITSCRAMBLER_TX_ENA_M (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
#define BITSCRAMBLER_TX_ENA_V 0x00000001U
#define BITSCRAMBLER_TX_ENA_S 0
/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_PAUSE (BIT(1))
#define BITSCRAMBLER_TX_PAUSE_M (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
#define BITSCRAMBLER_TX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_PAUSE_S 1
/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
#define BITSCRAMBLER_TX_HALT (BIT(2))
#define BITSCRAMBLER_TX_HALT_M (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
#define BITSCRAMBLER_TX_HALT_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_S 2
/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
#define BITSCRAMBLER_TX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_TX_EOF_MODE_M (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
#define BITSCRAMBLER_TX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_MODE_S 3
/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_TX_COND_MODE (BIT(4))
#define BITSCRAMBLER_TX_COND_MODE_M (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
#define BITSCRAMBLER_TX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_COND_MODE_S 4
/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
#define BITSCRAMBLER_TX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_TX_FETCH_MODE_M (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
#define BITSCRAMBLER_TX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_FETCH_MODE_S 5
/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_TX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_TX_HALT_MODE_M (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
#define BITSCRAMBLER_TX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_TX_HALT_MODE_S 6
/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_TX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_TX_RD_DUMMY_M (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
#define BITSCRAMBLER_TX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_TX_RD_DUMMY_S 7
/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
#define BITSCRAMBLER_TX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_TX_FIFO_RST_M (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
#define BITSCRAMBLER_TX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_RST_S 8
/** BITSCRAMBLER_RX_CTRL_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
#define BITSCRAMBLER_RX_ENA (BIT(0))
#define BITSCRAMBLER_RX_ENA_M (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
#define BITSCRAMBLER_RX_ENA_V 0x00000001U
#define BITSCRAMBLER_RX_ENA_S 0
/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_PAUSE (BIT(1))
#define BITSCRAMBLER_RX_PAUSE_M (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
#define BITSCRAMBLER_RX_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_PAUSE_S 1
/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
#define BITSCRAMBLER_RX_HALT (BIT(2))
#define BITSCRAMBLER_RX_HALT_M (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
#define BITSCRAMBLER_RX_HALT_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_S 2
/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
#define BITSCRAMBLER_RX_EOF_MODE (BIT(3))
#define BITSCRAMBLER_RX_EOF_MODE_M (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
#define BITSCRAMBLER_RX_EOF_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_MODE_S 3
/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
#define BITSCRAMBLER_RX_COND_MODE (BIT(4))
#define BITSCRAMBLER_RX_COND_MODE_M (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
#define BITSCRAMBLER_RX_COND_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_COND_MODE_S 4
/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
#define BITSCRAMBLER_RX_FETCH_MODE (BIT(5))
#define BITSCRAMBLER_RX_FETCH_MODE_M (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
#define BITSCRAMBLER_RX_FETCH_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_FETCH_MODE_S 5
/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
#define BITSCRAMBLER_RX_HALT_MODE (BIT(6))
#define BITSCRAMBLER_RX_HALT_MODE_M (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
#define BITSCRAMBLER_RX_HALT_MODE_V 0x00000001U
#define BITSCRAMBLER_RX_HALT_MODE_S 6
/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
#define BITSCRAMBLER_RX_RD_DUMMY (BIT(7))
#define BITSCRAMBLER_RX_RD_DUMMY_M (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
#define BITSCRAMBLER_RX_RD_DUMMY_V 0x00000001U
#define BITSCRAMBLER_RX_RD_DUMMY_S 7
/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
#define BITSCRAMBLER_RX_FIFO_RST (BIT(8))
#define BITSCRAMBLER_RX_FIFO_RST_M (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
#define BITSCRAMBLER_RX_FIFO_RST_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_RST_S 8
/** BITSCRAMBLER_TX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
#define BITSCRAMBLER_TX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_TX_IN_IDLE_M (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
#define BITSCRAMBLER_TX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_IDLE_S 0
/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
#define BITSCRAMBLER_TX_IN_RUN (BIT(1))
#define BITSCRAMBLER_TX_IN_RUN_M (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
#define BITSCRAMBLER_TX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_TX_IN_RUN_S 1
/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_TX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_TX_IN_WAIT_M (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
#define BITSCRAMBLER_TX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_TX_IN_WAIT_S 2
/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
#define BITSCRAMBLER_TX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_TX_IN_PAUSE_M (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
#define BITSCRAMBLER_TX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_TX_IN_PAUSE_S 3
/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 0;
* represents the bitscrambler tx fifo in empty state
*/
#define BITSCRAMBLER_TX_FIFO_EMPTY (BIT(4))
#define BITSCRAMBLER_TX_FIFO_EMPTY_M (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
#define BITSCRAMBLER_TX_FIFO_EMPTY_V 0x00000001U
#define BITSCRAMBLER_TX_FIFO_EMPTY_S 4
/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
#define BITSCRAMBLER_TX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_M (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
#define BITSCRAMBLER_TX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_TX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
#define BITSCRAMBLER_TX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_TX_EOF_OVERLOAD_M (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_TX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
#define BITSCRAMBLER_TX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_RX_STATE_REG register
* Status registers
*/
#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
#define BITSCRAMBLER_RX_IN_IDLE (BIT(0))
#define BITSCRAMBLER_RX_IN_IDLE_M (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
#define BITSCRAMBLER_RX_IN_IDLE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_IDLE_S 0
/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
#define BITSCRAMBLER_RX_IN_RUN (BIT(1))
#define BITSCRAMBLER_RX_IN_RUN_M (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
#define BITSCRAMBLER_RX_IN_RUN_V 0x00000001U
#define BITSCRAMBLER_RX_IN_RUN_S 1
/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
#define BITSCRAMBLER_RX_IN_WAIT (BIT(2))
#define BITSCRAMBLER_RX_IN_WAIT_M (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
#define BITSCRAMBLER_RX_IN_WAIT_V 0x00000001U
#define BITSCRAMBLER_RX_IN_WAIT_S 2
/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
#define BITSCRAMBLER_RX_IN_PAUSE (BIT(3))
#define BITSCRAMBLER_RX_IN_PAUSE_M (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
#define BITSCRAMBLER_RX_IN_PAUSE_V 0x00000001U
#define BITSCRAMBLER_RX_IN_PAUSE_S 3
/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
#define BITSCRAMBLER_RX_FIFO_FULL (BIT(4))
#define BITSCRAMBLER_RX_FIFO_FULL_M (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
#define BITSCRAMBLER_RX_FIFO_FULL_V 0x00000001U
#define BITSCRAMBLER_RX_FIFO_FULL_S 4
/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
#define BITSCRAMBLER_RX_EOF_GET_CNT 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_M (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
#define BITSCRAMBLER_RX_EOF_GET_CNT_V 0x00003FFFU
#define BITSCRAMBLER_RX_EOF_GET_CNT_S 16
/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
#define BITSCRAMBLER_RX_EOF_OVERLOAD (BIT(30))
#define BITSCRAMBLER_RX_EOF_OVERLOAD_M (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
#define BITSCRAMBLER_RX_EOF_OVERLOAD_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_OVERLOAD_S 30
/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
#define BITSCRAMBLER_RX_EOF_TRACE_CLR (BIT(31))
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V 0x00000001U
#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S 31
/** BITSCRAMBLER_SYS_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
#define BITSCRAMBLER_LOOP_MODE (BIT(0))
#define BITSCRAMBLER_LOOP_MODE_M (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
#define BITSCRAMBLER_LOOP_MODE_V 0x00000001U
#define BITSCRAMBLER_LOOP_MODE_S 0
/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
* Reserved
*/
#define BITSCRAMBLER_CLK_EN (BIT(31))
#define BITSCRAMBLER_CLK_EN_M (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
#define BITSCRAMBLER_CLK_EN_V 0x00000001U
#define BITSCRAMBLER_CLK_EN_S 31
/** BITSCRAMBLER_VERSION_REG register
* Control and configuration registers
*/
#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36713024;
* Reserved
*/
#define BITSCRAMBLER_BITSCRAMBLER_VER 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_M (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
#define BITSCRAMBLER_BITSCRAMBLER_VER_V 0x0FFFFFFFU
#define BITSCRAMBLER_BITSCRAMBLER_VER_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/bitscrambler_struct.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control and configuration registers */
/** Type of tx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t tx_inst_idx:3;
/** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t tx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_tx_inst_cfg0_reg_t;
/** Type of tx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_inst : R/W; bitpos: [31:0]; default: 4;
* write this bits to update instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_TX_INST_CFG0_REG
*/
uint32_t tx_inst:32;
};
uint32_t val;
} bitscrambler_tx_inst_cfg1_reg_t;
/** Type of rx_inst_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
* write this bits to specify the one of 8 instruction
*/
uint32_t rx_inst_idx:3;
/** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
* write this bits to specify the bit position of 257 bit instruction which in units
* of 32 bits
*/
uint32_t rx_inst_pos:4;
uint32_t reserved_7:25;
};
uint32_t val;
} bitscrambler_rx_inst_cfg0_reg_t;
/** Type of rx_inst_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_inst : R/W; bitpos: [31:0]; default: 12;
* write this bits to update instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
* BITSCRAMBLER_RX_INST_CFG0_REG
*/
uint32_t rx_inst:32;
};
uint32_t val;
} bitscrambler_rx_inst_cfg1_reg_t;
/** Type of tx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_tx_lut_mode
*/
uint32_t tx_lut_idx:11;
/** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t tx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_tx_lut_cfg0_reg_t;
/** Type of tx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_lut : R/W; bitpos: [31:0]; default: 20;
* write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
*/
uint32_t tx_lut:32;
};
uint32_t val;
} bitscrambler_tx_lut_cfg1_reg_t;
/** Type of rx_lut_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
* write this bits to specify the bytes position of LUT RAM based on
* reg_bitscrambler_rx_lut_mode
*/
uint32_t rx_lut_idx:11;
/** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
* write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
* bytes
*/
uint32_t rx_lut_mode:2;
uint32_t reserved_13:19;
};
uint32_t val;
} bitscrambler_rx_lut_cfg0_reg_t;
/** Type of rx_lut_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_lut : R/W; bitpos: [31:0]; default: 28;
* write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
* this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
*/
uint32_t rx_lut:32;
};
uint32_t val;
} bitscrambler_rx_lut_cfg1_reg_t;
/** Group: Configuration registers */
/** Type of tx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t tx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_tx_tailing_bits_reg_t;
/** Type of rx_tailing_bits register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
* write this bits to specify the extra data bit length after getting EOF
*/
uint32_t rx_tailing_bits:16;
uint32_t reserved_16:16;
};
uint32_t val;
} bitscrambler_rx_tailing_bits_reg_t;
/** Type of tx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** tx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler tx
*/
uint32_t tx_ena:1;
/** tx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler tx core
*/
uint32_t tx_pause:1;
/** tx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler tx core
*/
uint32_t tx_halt:1;
/** tx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler tx core EOF signal generating mode which is
* combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
* counter by write peripheral buffer
*/
uint32_t tx_eof_mode:1;
/** tx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler tx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t tx_cond_mode:1;
/** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
uint32_t tx_fetch_mode:1;
/** tx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t tx_halt_mode:1;
/** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler tx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t tx_rd_dummy:1;
/** tx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler tx fifo
*/
uint32_t tx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_tx_ctrl_reg_t;
/** Type of rx_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** rx_ena : R/W; bitpos: [0]; default: 0;
* write this bit to enable the bitscrambler rx
*/
uint32_t rx_ena:1;
/** rx_pause : R/W; bitpos: [1]; default: 0;
* write this bit to pause the bitscrambler rx core
*/
uint32_t rx_pause:1;
/** rx_halt : R/W; bitpos: [2]; default: 1;
* write this bit to halt the bitscrambler rx core
*/
uint32_t rx_halt:1;
/** rx_eof_mode : R/W; bitpos: [3]; default: 0;
* write this bit to ser the bitscrambler rx core EOF signal generating mode which is
* combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
* buffer, 0 counter by write dma fifo
*/
uint32_t rx_eof_mode:1;
/** rx_cond_mode : R/W; bitpos: [4]; default: 0;
* write this bit to specify the LOOP instruction condition mode of bitscrambler rx
* core, 0: use the little than operator to get the condition, 1: use not equal
* operator to get the condition
*/
uint32_t rx_cond_mode:1;
/** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
* write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
* by reset, 1: fetch by instrutions
*/
uint32_t rx_fetch_mode:1;
/** rx_halt_mode : R/W; bitpos: [6]; default: 0;
* write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
* wait write data back done, , 1: ignore write data back
*/
uint32_t rx_halt_mode:1;
/** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
* write this bit to set the bitscrambler rx core read data mode when EOF received.0:
* wait read data, 1: ignore read data
*/
uint32_t rx_rd_dummy:1;
/** rx_fifo_rst : WT; bitpos: [8]; default: 0;
* write this bit to reset the bitscrambler rx fifo
*/
uint32_t rx_fifo_rst:1;
uint32_t reserved_9:23;
};
uint32_t val;
} bitscrambler_rx_ctrl_reg_t;
/** Type of sys register
* Control and configuration registers
*/
typedef union {
struct {
/** loop_mode : R/W; bitpos: [0]; default: 0;
* write this bit to set the bitscrambler tx loop back to DMA rx
*/
uint32_t loop_mode:1;
uint32_t reserved_1:30;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t clk_en:1;
};
uint32_t val;
} bitscrambler_sys_reg_t;
/** Group: Status registers */
/** Type of tx_state register
* Status registers
*/
typedef union {
struct {
/** tx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler tx core in halt mode
*/
uint32_t tx_in_idle:1;
/** tx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler tx core in run mode
*/
uint32_t tx_in_run:1;
/** tx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler tx core in wait mode to wait write back done
*/
uint32_t tx_in_wait:1;
/** tx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler tx core in pause mode
*/
uint32_t tx_in_pause:1;
/** tx_fifo_empty : RO; bitpos: [4]; default: 0;
* represents the bitscrambler tx fifo in empty state
*/
uint32_t tx_fifo_empty:1;
uint32_t reserved_5:11;
/** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler tx core when get EOF
*/
uint32_t tx_eof_get_cnt:14;
/** tx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler tx core
*/
uint32_t tx_eof_overload:1;
/** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_tx_eof_overload and
* reg_bitscrambler_tx_eof_get_cnt registers
*/
uint32_t tx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_tx_state_reg_t;
/** Type of rx_state register
* Status registers
*/
typedef union {
struct {
/** rx_in_idle : RO; bitpos: [0]; default: 1;
* represents the bitscrambler rx core in halt mode
*/
uint32_t rx_in_idle:1;
/** rx_in_run : RO; bitpos: [1]; default: 0;
* represents the bitscrambler rx core in run mode
*/
uint32_t rx_in_run:1;
/** rx_in_wait : RO; bitpos: [2]; default: 0;
* represents the bitscrambler rx core in wait mode to wait write back done
*/
uint32_t rx_in_wait:1;
/** rx_in_pause : RO; bitpos: [3]; default: 0;
* represents the bitscrambler rx core in pause mode
*/
uint32_t rx_in_pause:1;
/** rx_fifo_full : RO; bitpos: [4]; default: 0;
* represents the bitscrambler rx fifo in full state
*/
uint32_t rx_fifo_full:1;
uint32_t reserved_5:11;
/** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
* represents the bytes numbers of bitscrambler rx core when get EOF
*/
uint32_t rx_eof_get_cnt:14;
/** rx_eof_overload : RO; bitpos: [30]; default: 0;
* represents the some EOFs will be lost for bitscrambler rx core
*/
uint32_t rx_eof_overload:1;
/** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
* write this bit to clear reg_bitscrambler_rx_eof_overload and
* reg_bitscrambler_rx_eof_get_cnt registers
*/
uint32_t rx_eof_trace_clr:1;
};
uint32_t val;
} bitscrambler_rx_state_reg_t;
/** Group: Version register */
/** Type of version register
* Control and configuration registers
*/
typedef union {
struct {
/** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
* Reserved
*/
uint32_t bitscrambler_ver:28;
uint32_t reserved_28:4;
};
uint32_t val;
} bitscrambler_version_reg_t;
typedef struct bitscrambler_dev_t {
volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
volatile bitscrambler_tx_state_reg_t tx_state;
volatile bitscrambler_rx_state_reg_t rx_state;
uint32_t reserved_038[48];
volatile bitscrambler_sys_reg_t sys;
volatile bitscrambler_version_reg_t version;
} bitscrambler_dev_t;
extern bitscrambler_dev_t BITSCRAMBLER;
#ifndef __cplusplus
_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/cache_reg.h
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components/soc/esp32c5/beta3/include/soc/cache_struct.h
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components/soc/esp32c5/beta3/include/soc/clic_reg.h
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NLBITS 3
#define CLIC_EXT_INTR_NUM_OFFSET 16
#define DUALCORE_CLIC_CTRL_OFF 0x10000
#define DR_REG_CLIC_BASE ( 0x20800000 )
#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 )
#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0)
/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */
/*description: .*/
#define CLIC_INT_CONFIG_NMBITS 0x00000003
#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S))
#define CLIC_INT_CONFIG_NMBITS_V 0x3
#define CLIC_INT_CONFIG_NMBITS_S 5
/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
/*description: .*/
#define CLIC_INT_CONFIG_NLBITS 0x0000000F
#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S))
#define CLIC_INT_CONFIG_NLBITS_V 0xF
#define CLIC_INT_CONFIG_NLBITS_S 1
/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */
/*description: .*/
#define CLIC_INT_CONFIG_NVBITS (BIT(0))
#define CLIC_INT_CONFIG_NVBITS_M (BIT(0))
#define CLIC_INT_CONFIG_NVBITS_V 0x1
#define CLIC_INT_CONFIG_NVBITS_S 0
#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4)
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
/*description: .*/
#define CLIC_INT_INFO_CTLBITS 0x0000000F
#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S))
#define CLIC_INT_INFO_CTLBITS_V 0xF
#define CLIC_INT_INFO_CTLBITS_S 21
/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */
/*description: .*/
#define CLIC_INT_INFO_VERSION 0x000000FF
#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S))
#define CLIC_INT_INFO_VERSION_V 0xFF
#define CLIC_INT_INFO_VERSION_S 13
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */
/*description: .*/
#define CLIC_INT_INFO_NUM_INT 0x00001FFF
#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S))
#define CLIC_INT_INFO_NUM_INT_V 0x1FFF
#define CLIC_INT_INFO_NUM_INT_S 0
#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8)
/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
/*description: .*/
#define CLIC_CPU_INT_THRESH 0x000000FF
#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S))
#define CLIC_CPU_INT_THRESH_V 0xFF
#define CLIC_CPU_INT_THRESH_S 24
#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4)
/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
/*description: .*/
#define CLIC_INT_CTL 0x000000FF
#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S))
#define CLIC_INT_CTL_V 0xFF
#define CLIC_INT_CTL_S 24
/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
/*description: .*/
#define CLIC_INT_ATTR_MODE 0x00000003
#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S))
#define CLIC_INT_ATTR_MODE_V 0x3
#define CLIC_INT_ATTR_MODE_S 22
/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: .*/
#define CLIC_INT_ATTR_TRIG 0x00000003
#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S))
#define CLIC_INT_ATTR_TRIG_V 0x3
#define CLIC_INT_ATTR_TRIG_S 17
/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_ATTR_SHV (BIT(16))
#define CLIC_INT_ATTR_SHV_M (BIT(16))
#define CLIC_INT_ATTR_SHV_V 0x1
#define CLIC_INT_ATTR_SHV_S 16
/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_IE (BIT(8))
#define CLIC_INT_IE_M (BIT(8))
#define CLIC_INT_IE_V 0x1
#define CLIC_INT_IE_S 8
/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_IP (BIT(0))
#define CLIC_INT_IP_M (BIT(0))
#define CLIC_INT_IP_V 0x1
#define CLIC_INT_IP_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/clint_reg.h
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/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/*CLINT MINT*/
#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define CLINT_CPU_MINT_SIP BIT(0)
#define CLINT_CPU_MINT_SIP_M BIT(0)
#define CLINT_CPU_MINT_SIP_V 1
#define CLINT_CPU_MINT_SIP_S 0
#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x4000)
/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_L_S 0
#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x4004)
/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_S 0
#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4010)
/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
/*description: .*/
#define CLINT_MINT_SAMPLING_MODE 0x00000003
#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
#define CLINT_MINT_SAMPLING_MODE_V 0x3
#define CLINT_MINT_SAMPLING_MODE_S 4
/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3))
#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3))
#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1
#define CLINT_MINT_COUNTER_OVERFLOW_S 3
/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define CLINT_MINT_COUNTER_EN (BIT(0))
#define CLINT_MINT_COUNTER_EN_M (BIT(0))
#define CLINT_MINT_COUNTER_EN_V 0x1
#define CLINT_MINT_COUNTER_EN_S 0
#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0xBFF8)
/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_S 0
#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xBFFC)
/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_H_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h
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@ -1,524 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
************************* ESP32C5 Root Clock Source ****************************
* 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
*
* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
*
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
*
* 2) External 40/48MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
*
* 4) Internal 32kHz RC Oscillator: RC32K
*
* The exact frequency of this clock can be computed in runtime through calibration.
*
* 5) External 32kHz Crystal Clock (optional): XTAL32K
*
* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
* pins.
*
* XTAL32K_CLK can also be calibrated to get its exact frequency.
*
* 6) External Slow Clock (optional): OSC_SLOW
*
* A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the
* RTC_SLOW_CLK.
*
* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
*/
// TODO: [ESP32C5] IDF-8642 (inherit from C6)
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
// {loc}: EXT, INT
// {type}: XTAL, RC
// [attr] - optional: [frequency], FAST, SLOW
/**
* @brief Root clock
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */
SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */
SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */
} soc_root_clk_t;
/**
* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL_F160M = 2, /*!< Select PLL_F160M_CLK as CPU_CLK source (PLL_F160M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */
SOC_CPU_CLK_SRC_PLL_F240M = 3, /*!< Select PLL_F240M_CLK as CPU_CLK source (PLL_F240M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
} soc_cpu_clk_src_t;
/**
* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
// SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ !!! can't do calibration on esp32c5, don't use it
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
} soc_rtc_slow_clk_src_t;
/**
* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_XTAL = 2, /*!< Select XTAL_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
} soc_rtc_fast_clk_src_t;
/**
* @brief Possible main XTAL frequency options on the target
* @note Enum values equal to the frequency value in MHz
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
* the supported ones.
*/
typedef enum {
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
SOC_XTAL_FREQ_48M = 48, /*!< 48MHz XTAL */
} soc_xtal_freq_t;
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
/**
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
*
* @note enum starts from 1, to save 0 for special purpose
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
// For CPU domain
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
// For RTC domain
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
SOC_MOD_CLK_SPLL, /*!< SPLL is from the main XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
// For LP peripherals
SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
/**
* @brief Type of SYSTIMER clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6)
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */
SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t;
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of GPTimer
*
* The following code can be used to iterate all possible clocks:
* @code{c}
* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
* // Test GPTimer with the clock `clk`
* }
* @endcode
*/
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M/*, SOC_MOD_CLK_RC_FAST*/, SOC_MOD_CLK_XTAL}
/**
* @brief Type of GPTimer clock source
*/
typedef enum {
GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of RMT
*/
#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M,/* SOC_MOD_CLK_RC_FAST,*/ SOC_MOD_CLK_XTAL}
/**
* @brief Type of RMT clock source
*/
typedef enum {
RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_rmt_clk_src_t;
/**
* @brief Type of RMT clock source, reserved for the legacy RMT driver
*/
typedef enum {
RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Temperature Sensor
*/
#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of Temp Sensor clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8727 (inherit from C6)
TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
} soc_periph_temperature_sensor_clk_src_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of UART
*/
#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of UART clock source, reserved for the legacy UART driver
*/
typedef enum {
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
} soc_periph_uart_clk_src_legacy_t;
/**
* @brief Array initializer for all supported clock sources of LP_UART
*/
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
/**
* @brief Type of LP_UART clock source
*/
typedef enum {
LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is RC_FAST */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock default choice is RC_FAST */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Carrier
*/
#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM carrier clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
/**
* @brief I2S clock source enum
*/
typedef enum { // TODO: [ESP32C5] IDF-8713 (inherit from C6)
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2C
*/
#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of I2C clock source.
*/
typedef enum {
I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
} soc_periph_i2c_clk_src_t;
///////////////////////////////////////////////LP_I2C///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of LP_I2C
*/
#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
/**
* @brief Type of LP_I2C clock source.
*/
typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6)
LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */
LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */
LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */
} soc_periph_lp_i2c_clk_src_t;
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of SPI clock source.
*/
typedef enum {
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as SPI source clock */
} soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
*/
#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Sigma Delta Modulator clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8687 (inherit from C6)
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Glitch filter clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8718 (inherit from C6)
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of TWAI
*/
#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL}
/**
* @brief TWAI clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8691, IDF-8692 (inherit from C6)
TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of ADC digital controller
*/
#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief ADC digital controller clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8701, IDF-8702, IDF-8703 (inherit from C6)
ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
} soc_periph_adc_digi_clk_src_t;
//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MWDT
*/
#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief MWDT clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8650 (inherit from C6)
MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */
MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of LEDC
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of LEDC clock source, reserved for the legacy LEDC driver
*/
typedef enum { // TODO: [ESP32C5] IDF-8684 (inherit from C6)
LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PARLIO
*/
#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M}
/**
* @brief PARLIO clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6)
PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
} soc_periph_parlio_clk_src_t;
//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MSPI digital controller
*/
#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
/**
* @brief MSPI digital controller clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8649
MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */
MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_mspi_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
CLKOUT_SIG_CPU = 16, /*!< CPU clock */
CLKOUT_SIG_AHB = 17, /*!< AHB clock */
CLKOUT_SIG_APB = 18, /*!< APB clock */
CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */
CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */
CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */
CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
* @brief Read a sequence of DPORT registers to the buffer.
*
* @param[out] buff_out Contains the read data.
* @param[in] address Initial address for reading registers.
* @param[in] num_words The number of words.
*/
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
// Write value to DPORT register (does not require protecting)
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
//get bit or get bits from register
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
//set bit or set bits to register
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
//clear bit or clear bits of register
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
//set bits of register controlled by mask
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
//get field from register, uses field _S & _V to determine mask
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
//set field to register, used when _f is not left shifted by _f##_S
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
//get field value from a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
//write value to register
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
//clear bits of register controlled by mask
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
//set bits of register controlled by mask
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
//get bits of register controlled by mask
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
//get bits of register controlled by highest bit and lowest bit
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
//set bits of register controlled by mask and shift
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
//get field of register
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
//}}
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
* memory that stores Y
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
* memory that stores M
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
* memory that stores Rb
*/
#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
#define DS_RB_MEM_SIZE_BYTES 512
/** DS_BOX_MEM register
* memory that stores BOX
*/
#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
#define DS_BOX_MEM_SIZE_BYTES 48
/** DS_IV_MEM register
* memory that stores IV
*/
#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
#define DS_IV_MEM_SIZE_BYTES 16
/** DS_X_MEM register
* memory that stores X
*/
#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
#define DS_X_MEM_SIZE_BYTES 512
/** DS_Z_MEM register
* memory that stores Z
*/
#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
#define DS_Z_MEM_SIZE_BYTES 512
/** DS_SET_START_REG register
* DS start control register
*/
#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
/** DS_SET_START : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
#define DS_SET_START (BIT(0))
#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S)
#define DS_SET_START_V 0x00000001U
#define DS_SET_START_S 0
/** DS_SET_CONTINUE_REG register
* DS continue control register
*/
#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
#define DS_SET_CONTINUE (BIT(0))
#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
#define DS_SET_CONTINUE_V 0x00000001U
#define DS_SET_CONTINUE_S 0
/** DS_SET_FINISH_REG register
* DS finish control register
*/
#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
#define DS_SET_FINISH (BIT(0))
#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S)
#define DS_SET_FINISH_V 0x00000001U
#define DS_SET_FINISH_S 0
/** DS_QUERY_BUSY_REG register
* DS query busy register
*/
#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
#define DS_QUERY_BUSY (BIT(0))
#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
#define DS_QUERY_BUSY_V 0x00000001U
#define DS_QUERY_BUSY_S 0
/** DS_QUERY_KEY_WRONG_REG register
* DS query key-wrong counter register
*/
#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
#define DS_QUERY_KEY_WRONG 0x0000000FU
#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
#define DS_QUERY_KEY_WRONG_V 0x0000000FU
#define DS_QUERY_KEY_WRONG_S 0
/** DS_QUERY_CHECK_REG register
* DS query check result register
*/
#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
#define DS_MD_ERROR (BIT(0))
#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S)
#define DS_MD_ERROR_V 0x00000001U
#define DS_MD_ERROR_S 0
/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
#define DS_PADDING_BAD (BIT(1))
#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
#define DS_PADDING_BAD_V 0x00000001U
#define DS_PADDING_BAD_S 1
/** DS_DATE_REG register
* DS version control register
*/
#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
#define DS_DATE 0x3FFFFFFFU
#define DS_DATE_M (DS_DATE_V << DS_DATE_S)
#define DS_DATE_V 0x3FFFFFFFU
#define DS_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
* DS start control register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_start_reg_t;
/** Type of set_continue register
* DS continue control register
*/
typedef union {
struct {
/** set_continue : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
uint32_t set_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_continue_reg_t;
/** Type of set_finish register
* DS finish control register
*/
typedef union {
struct {
/** set_finish : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
uint32_t set_finish:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_finish_reg_t;
/** Type of query_busy register
* DS query busy register
*/
typedef union {
struct {
/** query_busy : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
uint32_t query_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_query_busy_reg_t;
/** Type of query_key_wrong register
* DS query key-wrong counter register
*/
typedef union {
struct {
/** query_key_wrong : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
uint32_t query_key_wrong:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ds_query_key_wrong_reg_t;
/** Type of query_check register
* DS query check result register
*/
typedef union {
struct {
/** md_error : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
uint32_t md_error:1;
/** padding_bad : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
uint32_t padding_bad:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ds_query_check_reg_t;
/** Group: version control register */
/** Type of date register
* DS version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} ds_date_reg_t;
typedef struct ds_dev_t {
volatile uint32_t y[128];
volatile uint32_t m[128];
volatile uint32_t rb[128];
volatile uint32_t box[12];
volatile uint32_t iv[4];
uint32_t reserved_640[112];
volatile uint32_t x[128];
volatile uint32_t z[128];
uint32_t reserved_c00[128];
volatile ds_set_start_reg_t set_start;
volatile ds_set_continue_reg_t set_continue;
volatile ds_set_finish_reg_t set_finish;
volatile ds_query_busy_reg_t query_busy;
volatile ds_query_key_wrong_reg_t query_key_wrong;
volatile ds_query_check_reg_t query_check;
uint32_t reserved_e18[2];
volatile ds_date_reg_t date;
} ds_dev_t;
extern ds_dev_t DS;
#ifndef __cplusplus
_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
* ECC interrupt raw register, valid in level.
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register
* ECC interrupt status register.
*/
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register
* ECC interrupt enable register.
*/
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register
* ECC interrupt clear register.
*/
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecc_calc_done_int interrupt
*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register
* ECC configure register
*/
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
* the caculatrion is done.
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Write 1 to reset ECC Accelerator.
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
* The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
*/
#define ECC_MULT_KEY_LENGTH (BIT(2))
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000001U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
* The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
* 1: p(mod base of curve)
*/
#define ECC_MULT_MOD_BASE (BIT(3))
#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
#define ECC_MULT_MOD_BASE_V 0x00000001U
#define ECC_MULT_MOD_BASE_S 3
/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
* The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
* verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
* Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
* 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
*/
#define ECC_MULT_WORK_MODE 0x0000000FU
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x0000000FU
#define ECC_MULT_WORK_MODE_S 4
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
* Reserved
*/
#define ECC_MULT_SECURITY_MODE (BIT(8))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 8
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
* The verification result bit of ECC Accelerator, only valid when calculation is done.
*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(29))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 29
/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECC_MULT_CLK_EN (BIT(30))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 30
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
* ECC memory clock gate force on register
*/
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
/** ECC_MULT_DATE_REG register
* Version control register
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 36720704;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
#define ECC_MULT_DATE_V 0x0FFFFFFFU
#define ECC_MULT_DATE_S 0
/** ECC_MULT_K_MEM register
* The memory that stores k.
*/
#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
#define ECC_MULT_K_MEM_SIZE_BYTES 32
/** ECC_MULT_PX_MEM register
* The memory that stores Px.
*/
#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
#define ECC_MULT_PX_MEM_SIZE_BYTES 32
/** ECC_MULT_PY_MEM register
* The memory that stores Py.
*/
#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
#define ECC_MULT_PY_MEM_SIZE_BYTES 32
/** ECC_MULT_QX_MEM register
* The memory that stores Qx.
*/
#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160)
#define ECC_MULT_QX_MEM_SIZE_BYTES 32
/** ECC_MULT_QY_MEM register
* The memory that stores Qy.
*/
#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180)
#define ECC_MULT_QY_MEM_SIZE_BYTES 32
/** ECC_MULT_QZ_MEM register
* The memory that stores Qz.
*/
#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1A0)
#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of int_raw register
* ECC interrupt raw register, valid in level.
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_raw_reg_t;
/** Type of int_st register
* ECC interrupt status register.
*/
typedef union {
struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_st_reg_t;
/** Type of int_ena register
* ECC interrupt enable register.
*/
typedef union {
struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_ena_reg_t;
/** Type of int_clr register
* ECC interrupt clear register.
*/
typedef union {
struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecc_calc_done_int interrupt
*/
uint32_t calc_done_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */
/** Type of conf register
* ECC configure register
*/
typedef union {
struct {
/** start : R/W/SC; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
* the caculatrion is done.
*/
uint32_t start:1;
/** reset : WT; bitpos: [1]; default: 0;
* Write 1 to reset ECC Accelerator.
*/
uint32_t reset:1;
/** key_length : R/W; bitpos: [2]; default: 0;
* The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
*/
uint32_t key_length:1;
/** mod_base : R/W; bitpos: [3]; default: 0;
* The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
* 1: p(mod base of curve)
*/
uint32_t mod_base:1;
/** work_mode : R/W; bitpos: [7:4]; default: 0;
* The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
* verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
* Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
* 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
*/
uint32_t work_mode:4;
/** security_mode : R/W; bitpos: [8]; default: 0;
* Reserved
*/
uint32_t security_mode:1;
uint32_t reserved_9:20;
/** verification_result : RO/SS; bitpos: [29]; default: 0;
* The verification result bit of ECC Accelerator, only valid when calculation is done.
*/
uint32_t verification_result:1;
/** clk_en : R/W; bitpos: [30]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
* ECC memory clock gate force on register
*/
uint32_t mem_clock_gate_force_on:1;
};
uint32_t val;
} ecc_mult_conf_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
* ECC mult version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecc_mult_date_reg_t;
typedef struct ecc_mult_dev_t {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t int_raw;
volatile ecc_mult_int_st_reg_t int_st;
volatile ecc_mult_int_ena_reg_t int_ena;
volatile ecc_mult_int_clr_reg_t int_clr;
volatile ecc_mult_conf_reg_t conf;
uint32_t reserved_020[55];
volatile ecc_mult_date_reg_t date;
volatile uint32_t k[8];
volatile uint32_t px[8];
volatile uint32_t py[8];
} ecc_mult_dev_t;
extern ecc_mult_dev_t ECC;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
* ECDSA configure register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
*/
#define ECDSA_ECC_CURVE (BIT(2))
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000001U
#define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
#define ECDSA_SOFTWARE_SET_K (BIT(3))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 3
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
#define ECDSA_SOFTWARE_SET_Z (BIT(4))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 4
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
#define ECDSA_DETERMINISTIC_K (BIT(5))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 5
/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
*/
#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU
#define ECDSA_DETERMINISTIC_LOOP_S 6
/** ECDSA_CLK_REG register
* ECDSA clock gate register
*/
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
#define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level.
*/
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_RAW (BIT(0))
#define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
#define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_CALC_DONE_INT_RAW_S 0
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(1))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_RAW_S 1
/** ECDSA_INT_ST_REG register
* ECDSA interrupt status register.
*/
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_ST (BIT(0))
#define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
#define ECDSA_CALC_DONE_INT_ST_V 0x00000001U
#define ECDSA_CALC_DONE_INT_ST_S 0
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ST (BIT(1))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ST_S 1
/** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register.
*/
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_ENA (BIT(0))
#define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
#define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_CALC_DONE_INT_ENA_S 0
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(1))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ENA_S 1
/** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register.
*/
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_calc_done_int interrupt
*/
#define ECDSA_CALC_DONE_INT_CLR (BIT(0))
#define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
#define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_CALC_DONE_INT_CLR_S 0
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(1))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_CLR_S 1
/** ECDSA_START_REG register
* ECDSA start register
*/
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
#define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
#define ECDSA_GET_DONE_V 0x00000001U
#define ECDSA_GET_DONE_S 2
/** ECDSA_STATE_REG register
* ECDSA status register
*/
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
#define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
#define ECDSA_BUSY_V 0x00000003U
#define ECDSA_BUSY_S 0
/** ECDSA_RESULT_REG register
* ECDSA result register
*/
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
#define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
* curve order, then actually taken k = k mod n.
*/
#define ECDSA_K_VALUE_WARNING (BIT(1))
#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
#define ECDSA_K_VALUE_WARNING_V 0x00000001U
#define ECDSA_K_VALUE_WARNING_S 1
/** ECDSA_DATE_REG register
* Version control register
*/
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
* ECDSA version control register
*/
#define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
#define ECDSA_DATE_V 0x0FFFFFFFU
#define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
* Others: invalid.
*/
#define ECDSA_SHA_MODE 0x00000007U
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
#define ECDSA_SHA_MODE_V 0x00000007U
#define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
#define ECDSA_SHA_START_V 0x00000001U
#define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
#define ECDSA_SHA_CONTINUE_V 0x00000001U
#define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register
* ECDSA status register
*/
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
#define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
#define ECDSA_SHA_BUSY_V 0x00000001U
#define ECDSA_SHA_BUSY_S 0
/** ECDSA_MESSAGE_MEM register
* The memory that stores message.
*/
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
/** ECDSA_R_MEM register
* The memory that stores r.
*/
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
#define ECDSA_R_MEM_SIZE_BYTES 32
/** ECDSA_S_MEM register
* The memory that stores s.
*/
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
#define ECDSA_S_MEM_SIZE_BYTES 32
/** ECDSA_Z_MEM register
* The memory that stores software written z.
*/
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
#define ECDSA_Z_MEM_SIZE_BYTES 32
/** ECDSA_QAX_MEM register
* The memory that stores x coordinates of QA or software written k.
*/
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
#define ECDSA_QAX_MEM_SIZE_BYTES 32
/** ECDSA_QAY_MEM register
* The memory that stores y coordinates of QA.
*/
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
#define ECDSA_QAY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/ecdsa_struct.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
* ECDSA configure register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
uint32_t work_mode:2;
/** ecc_curve : R/W; bitpos: [2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256.
*/
uint32_t ecc_curve:1;
/** software_set_k : R/W; bitpos: [3]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
uint32_t software_set_k:1;
/** software_set_z : R/W; bitpos: [4]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
uint32_t software_set_z:1;
/** deterministic_k : R/W; bitpos: [5]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
uint32_t deterministic_k:1;
/** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
* The (loop number - 1) value in the deterministic derivation algorithm to derive k.
*/
uint32_t deterministic_loop:16;
uint32_t reserved_22:10;
};
uint32_t val;
} ecdsa_conf_reg_t;
/** Type of start register
* ECDSA start register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
uint32_t start:1;
/** load_done : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t load_done:1;
/** get_done : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t get_done:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_start_reg_t;
/** Group: Clock and reset registers */
/** Type of clk register
* ECDSA clock gate register
*/
typedef union {
struct {
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_gate_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* ECDSA interrupt raw register, valid in level.
*/
typedef union {
struct {
/** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_calc_done_int interrupt
*/
uint32_t calc_done_int_raw:1;
/** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_int_raw_reg_t;
/** Type of int_st register
* ECDSA interrupt status register.
*/
typedef union {
struct {
/** calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_calc_done_int interrupt
*/
uint32_t calc_done_int_st:1;
/** sha_release_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_int_st_reg_t;
/** Type of int_ena register
* ECDSA interrupt enable register.
*/
typedef union {
struct {
/** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_calc_done_int interrupt
*/
uint32_t calc_done_int_ena:1;
/** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_int_ena_reg_t;
/** Type of int_clr register
* ECDSA interrupt clear register.
*/
typedef union {
struct {
/** calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_calc_done_int interrupt
*/
uint32_t calc_done_int_clr:1;
/** sha_release_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_int_clr_reg_t;
/** Group: Status registers */
/** Type of state register
* ECDSA status register
*/
typedef union {
struct {
/** busy : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
uint32_t busy:2;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_state_reg_t;
/** Group: Result registers */
/** Type of result register
* ECDSA result register
*/
typedef union {
struct {
/** operation_result : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
uint32_t operation_result:1;
/** k_value_warning : RO/SS; bitpos: [1]; default: 0;
* The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
* curve order, then actually taken k = k mod n.
*/
uint32_t k_value_warning:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_result_reg_t;
/** Group: SHA register */
/** Type of sha_mode register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_mode : R/W; bitpos: [2:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
* Others: invalid.
*/
uint32_t sha_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_sha_mode_reg_t;
/** Type of sha_start register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_start : WT; bitpos: [0]; default: 0;
* Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_start_reg_t;
/** Type of sha_continue register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_continue : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_continue_reg_t;
/** Type of sha_busy register
* ECDSA status register
*/
typedef union {
struct {
/** sha_busy : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
uint32_t sha_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_busy_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36716656;
* ECDSA version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecdsa_date_reg_t;
typedef struct ecdsa_dev_t {
uint32_t reserved_000;
volatile ecdsa_conf_reg_t conf;
volatile ecdsa_clk_reg_t clk;
volatile ecdsa_int_raw_reg_t int_raw;
volatile ecdsa_int_st_reg_t int_st;
volatile ecdsa_int_ena_reg_t int_ena;
volatile ecdsa_int_clr_reg_t int_clr;
volatile ecdsa_start_reg_t start;
volatile ecdsa_state_reg_t state;
volatile ecdsa_result_reg_t result;
uint32_t reserved_028[53];
volatile ecdsa_date_reg_t date;
uint32_t reserved_100[64];
volatile ecdsa_sha_mode_reg_t sha_mode;
uint32_t reserved_204[3];
volatile ecdsa_sha_start_reg_t sha_start;
volatile ecdsa_sha_continue_reg_t sha_continue;
volatile ecdsa_sha_busy_reg_t sha_busy;
uint32_t reserved_21c[25];
volatile uint32_t message[8];
uint32_t reserved_2a0[472];
volatile uint32_t r[8];
volatile uint32_t s[8];
volatile uint32_t z[8];
volatile uint32_t qax[8];
volatile uint32_t qay[8];
} ecdsa_dev_t;
extern ecdsa_dev_t ECDSA;
#ifndef __cplusplus
_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/efuse_reg.h
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/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !SOC_MMU_PAGE_SIZE
/**
* We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
* Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
*/
#define SOC_MMU_PAGE_SIZE 0x10000
#endif
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x41000000
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM))
#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW
#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH
#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW
#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
#define SOC_MMU_ACCESS_FLASH 0
#define SOC_MMU_VALID BIT(9)
#define SOC_MMU_SENSITIVE BIT(10)
#define SOC_MMU_INVALID_MASK BIT(9)
#define SOC_MMU_INVALID 0
/**
* MMU entry valid bit mask for mapping value. For an entry:
* valid bit + value bits
* valid bit is BIT(9), so value bits are 0x1ff
*/
#define SOC_MMU_VALID_VAL_MASK 0x1ff
/**
* Max MMU available paddr page num.
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
* 256 * 64KB, means MMU can support 16MB paddr at most
*/
#define SOC_MMU_MAX_PADDR_PAGE_NUM 256
//MMU entry num
#define SOC_MMU_ENTRY_NUM 256
/**
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & SOC_MMU_VADDR_MASK
*/
#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
#define SOC_MMU_DBUS_VADDR_BASE 0x41000000
#define SOC_MMU_IBUS_VADDR_BASE 0x41000000
/*------------------------------------------------------------------------------
* MMU Linear Address
*----------------------------------------------------------------------------*/
#if (SOC_MMU_PAGE_SIZE == 0x10000)
/**
* - 64KB MMU page size: the last 0xFFFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
*
* Therefore, 0x7F,FFFF
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF
#elif (SOC_MMU_PAGE_SIZE == 0x8000)
/**
* - 32KB MMU page size: the last 0x7FFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
*
* Therefore, 0x3F,FFFF
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF
#elif (SOC_MMU_PAGE_SIZE == 0x4000)
/**
* - 16KB MMU page size: the last 0x3FFF, which is the offset
* - 128 MMU entries, needs 0x7F to hold it.
*
* Therefore, 0x1F,FFFF
*/
#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF
#endif //SOC_MMU_PAGE_SIZE
/**
* - If high linear address isn't 0, this means MMU can recognize these addresses
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
* Under this condition, we use the max linear space.
*/
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
#else
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
#endif
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
#else
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
#endif
/**
* I/D share the MMU linear address range
*/
#ifndef __cplusplus
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
// On which system bus is the DMA instance of the peripheral connection mounted
#define SOC_GDMA_BUS_ANY (-1)
#define SOC_GDMA_BUS_AHB (0)
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadeltan register
* Duty Cycle Configure Register of SDMn
*/
typedef union {
struct {
/** sdn_in : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t sdn_in:8;
/** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t sdn_prescale:8;
uint32_t reserved_16:16;
};
uint32_t val;
} gpio_ext_sigmadeltan_reg_t;
/** Type of sigmadelta_misc register
* MISC Register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** function_clk_en : R/W; bitpos: [30]; default: 0;
* Clock enable bit of sigma delta modulation.
*/
uint32_t function_clk_en:1;
/** spi_swap : R/W; bitpos: [31]; default: 0;
* Reserved.
*/
uint32_t spi_swap:1;
};
uint32_t val;
} gpio_ext_sigmadelta_misc_reg_t;
/** Group: Configure Registers */
/** Type of pad_comp_config register
* PAD Compare configure Register
*/
typedef union {
struct {
/** xpd_comp : R/W; bitpos: [0]; default: 0;
* Pad compare enable bit.
*/
uint32_t xpd_comp:1;
/** mode_comp : R/W; bitpos: [1]; default: 0;
* 1 to enable external reference from PAD[0]. 0 to enable internal reference,
* meanwhile PAD[0] can be used as a regular GPIO.
*/
uint32_t mode_comp:1;
/** dref_comp : R/W; bitpos: [4:2]; default: 0;
* internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
*/
uint32_t dref_comp:3;
/** zero_det_mode : R/W; bitpos: [6:5]; default: 0;
* Zero Detect mode select.
*/
uint32_t zero_det_mode:2;
uint32_t reserved_7:25;
};
uint32_t val;
} gpio_ext_pad_comp_config_reg_t;
/** Type of pad_comp_filter register
* Zero Detect filter Register
*/
typedef union {
struct {
/** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 0;
* Zero Detect filter cycle length
*/
uint32_t zero_det_filter_cnt:32;
};
uint32_t val;
} gpio_ext_pad_comp_filter_reg_t;
/** Group: Glitch filter Configure Registers */
/** Type of glitch_filter_chn register
* Glitch Filter Configure Register of Channeln
*/
typedef union {
struct {
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t filter_ch0_en:1;
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t filter_ch0_input_io_num:6;
/** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t filter_ch0_window_thres:6;
/** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
* Glitch Filter window width.
*/
uint32_t filter_ch0_window_width:6;
uint32_t reserved_19:13;
};
uint32_t val;
} gpio_ext_glitch_filter_chn_reg_t;
/** Group: Etm Configure Registers */
/** Type of etm_event_chn_cfg register
* Etm Config register of Channeln
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_ch0_event_sel:5;
uint32_t reserved_5:2;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_ch0_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_ext_etm_event_chn_cfg_reg_t;
/** Type of etm_task_pn_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio0_en:1;
/** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio0_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio1_en:1;
/** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio1_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio2_en:1;
/** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio2_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio3_en:1;
/** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio3_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_ext_etm_task_pn_cfg_reg_t;
/** Group: Interrupt Registers */
/** Type of int_raw register
* GPIOSD interrupt raw register
*/
typedef union {
struct {
/** comp0_neg_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt raw
*/
uint32_t comp0_neg_int_raw:1;
/** comp0_pos_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* analog comparator neg edge interrupt raw
*/
uint32_t comp0_pos_int_raw:1;
/** comp0_all_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* analog comparator neg or pos edge interrupt raw
*/
uint32_t comp0_all_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_ext_int_raw_reg_t;
/** Type of int_st register
* GPIOSD interrupt masked register
*/
typedef union {
struct {
/** comp0_neg_int_st : RO; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt status
*/
uint32_t comp0_neg_int_st:1;
/** comp0_pos_int_st : RO; bitpos: [1]; default: 0;
* analog comparator neg edge interrupt status
*/
uint32_t comp0_pos_int_st:1;
/** comp0_all_int_st : RO; bitpos: [2]; default: 0;
* analog comparator neg or pos edge interrupt status
*/
uint32_t comp0_all_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_ext_int_st_reg_t;
/** Type of int_ena register
* GPIOSD interrupt enable register
*/
typedef union {
struct {
/** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1;
* analog comparator pos edge interrupt enable
*/
uint32_t comp0_neg_int_ena:1;
/** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1;
* analog comparator neg edge interrupt enable
*/
uint32_t comp0_pos_int_ena:1;
/** comp0_all_int_ena : R/W; bitpos: [2]; default: 1;
* analog comparator neg or pos edge interrupt enable
*/
uint32_t comp0_all_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_ext_int_ena_reg_t;
/** Type of int_clr register
* GPIOSD interrupt clear register
*/
typedef union {
struct {
/** comp0_neg_int_clr : WT; bitpos: [0]; default: 0;
* analog comparator pos edge interrupt clear
*/
uint32_t comp0_neg_int_clr:1;
/** comp0_pos_int_clr : WT; bitpos: [1]; default: 0;
* analog comparator neg edge interrupt clear
*/
uint32_t comp0_pos_int_clr:1;
/** comp0_all_int_clr : WT; bitpos: [2]; default: 0;
* analog comparator neg or pos edge interrupt clear
*/
uint32_t comp0_all_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} gpio_ext_int_clr_reg_t;
/** Group: Version Register */
/** Type of version register
* Version Control Register
*/
typedef union {
struct {
/** gpio_sd_date : R/W; bitpos: [27:0]; default: 36704513;
* Version control register.
*/
uint32_t gpio_sd_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_ext_version_reg_t;
typedef struct gpio_sd_dev_t {
volatile gpio_ext_sigmadeltan_reg_t channel[4];
uint32_t reserved_010[5];
volatile gpio_ext_sigmadelta_misc_reg_t misc;
} gpio_sd_dev_t;
typedef struct gpio_ana_cmpr_dev_t {
volatile gpio_ext_pad_comp_config_reg_t pad_comp_config;
volatile gpio_ext_pad_comp_filter_reg_t pad_comp_filter;
} gpio_ana_cmpr_dev_t;
typedef struct {
volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8];
} gpio_glitch_filter_dev_t;
typedef struct gpio_etm_dev_t {
volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[7];
} gpio_etm_dev_t;
typedef struct gpio_ext_dev_t {
volatile gpio_sd_dev_t sigma_delta;
volatile gpio_ana_cmpr_dev_t ana_cmpr;
volatile gpio_glitch_filter_dev_t glitch_filter;
uint32_t reserved_050[4];
volatile gpio_etm_dev_t etm;
uint32_t reserved_0bc[9];
volatile gpio_ext_int_raw_reg_t int_raw;
volatile gpio_ext_int_st_reg_t int_st;
volatile gpio_ext_int_ena_reg_t int_ena;
volatile gpio_ext_int_clr_reg_t int_clr;
uint32_t reserved_0f0[3];
volatile gpio_ext_version_reg_t version;
} gpio_ext_dev_t;
extern gpio_sd_dev_t SDM;
extern gpio_glitch_filter_dev_t GLITCH_FILTER;
extern gpio_etm_dev_t GPIO_ETM;
extern gpio_ext_dev_t GPIO_EXT;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/gpio_num.h
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/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO number
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */
GPIO_NUM_3 = 3, /*!< GPIO3, input and output */
GPIO_NUM_4 = 4, /*!< GPIO4, input and output */
GPIO_NUM_5 = 5, /*!< GPIO5, input and output */
GPIO_NUM_6 = 6, /*!< GPIO6, input and output */
GPIO_NUM_7 = 7, /*!< GPIO7, input and output */
GPIO_NUM_8 = 8, /*!< GPIO8, input and output */
GPIO_NUM_9 = 9, /*!< GPIO9, input and output */
GPIO_NUM_10 = 10, /*!< GPIO10, input and output */
GPIO_NUM_11 = 11, /*!< GPIO11, input and output */
GPIO_NUM_12 = 12, /*!< GPIO12, input and output */
GPIO_NUM_13 = 13, /*!< GPIO13, input and output */
GPIO_NUM_14 = 14, /*!< GPIO14, input and output */
GPIO_NUM_15 = 15, /*!< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
GPIO_NUM_MAX,
} gpio_num_t;
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/gpio_pins.h
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/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/gpio_reg.h
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components/soc/esp32c5/beta3/include/soc/gpio_sig_map.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define EXT_ADC_START_IDX 0
#define LEDC_LS_SIG_OUT0_IDX 0
#define LEDC_LS_SIG_OUT1_IDX 1
#define LEDC_LS_SIG_OUT2_IDX 2
#define LEDC_LS_SIG_OUT3_IDX 3
#define LEDC_LS_SIG_OUT4_IDX 4
#define LEDC_LS_SIG_OUT5_IDX 5
#define U0RXD_IN_IDX 6
#define U0TXD_OUT_IDX 6
#define U0CTS_IN_IDX 7
#define U0RTS_OUT_IDX 7
#define U0DSR_IN_IDX 8
#define U0DTR_OUT_IDX 8
#define U1RXD_IN_IDX 9
#define U1TXD_OUT_IDX 9
#define U1CTS_IN_IDX 10
#define U1RTS_OUT_IDX 10
#define U1DSR_IN_IDX 11
#define U1DTR_OUT_IDX 11
#define I2S_MCLK_IN_IDX 12
#define I2S_MCLK_OUT_IDX 12
#define I2SO_BCK_IN_IDX 13
#define I2SO_BCK_OUT_IDX 13
#define I2SO_WS_IN_IDX 14
#define I2SO_WS_OUT_IDX 14
#define I2SI_SD_IN_IDX 15
#define I2SO_SD_OUT_IDX 15
#define I2SI_BCK_IN_IDX 16
#define I2SI_BCK_OUT_IDX 16
#define I2SI_WS_IN_IDX 17
#define I2SI_WS_OUT_IDX 17
#define I2SO_SD1_OUT_IDX 18
#define USB_JTAG_TDO_BRIDGE_IDX 19
#define USB_JTAG_TRST_IDX 19
#define CPU_TESTBUS0_IDX 20
#define USB_OTG_32K_IN_IDX 21
#define CPU_TESTBUS1_IDX 21
#define USB_OTG_25M_IN_IDX 22
#define CPU_TESTBUS2_IDX 22
#define USB_OTG_PRB_IN_IDX 23
#define CPU_TESTBUS3_IDX 23
#define USB_OTG_SNS_IN_IDX 24
#define CPU_TESTBUS4_IDX 24
#define CPU_TESTBUS5_IDX 25
#define CPU_TESTBUS6_IDX 26
#define CPU_TESTBUS7_IDX 27
#define CPU_GPIO_IN0_IDX 28
#define CPU_GPIO_OUT0_IDX 28
#define CPU_GPIO_IN1_IDX 29
#define CPU_GPIO_OUT1_IDX 29
#define CPU_GPIO_IN2_IDX 30
#define CPU_GPIO_OUT2_IDX 30
#define CPU_GPIO_IN3_IDX 31
#define CPU_GPIO_OUT3_IDX 31
#define CPU_GPIO_IN4_IDX 32
#define CPU_GPIO_OUT4_IDX 32
#define CPU_GPIO_IN5_IDX 33
#define CPU_GPIO_OUT5_IDX 33
#define CPU_GPIO_IN6_IDX 34
#define CPU_GPIO_OUT6_IDX 34
#define CPU_GPIO_IN7_IDX 35
#define CPU_GPIO_OUT7_IDX 35
#define USB_JTAG_TCK_IDX 36
#define USB_JTAG_TMS_IDX 37
#define USB_JTAG_TDI_IDX 38
#define USB_JTAG_TDO_IDX 39
#define USB_EXTPHY_VP_IDX 40
#define USB_EXTPHY_OEN_IDX 40
#define USB_EXTPHY_VM_IDX 41
#define USB_EXTPHY_SPEED_IDX 41
#define USB_EXTPHY_RCV_IDX 42
#define USB_EXTPHY_VPO_IDX 42
#define USB_EXTPHY_VMO_IDX 43
#define USB_EXTPHY_SUSPND_IDX 44
#define I2CEXT0_SCL_IN_IDX 45
#define I2CEXT0_SCL_OUT_IDX 45
#define I2CEXT0_SDA_IN_IDX 46
#define I2CEXT0_SDA_OUT_IDX 46
#define PARL_RX_DATA0_IDX 47
#define PARL_TX_DATA0_IDX 47
#define PARL_RX_DATA1_IDX 48
#define PARL_TX_DATA1_IDX 48
#define PARL_RX_DATA2_IDX 49
#define PARL_TX_DATA2_IDX 49
#define PARL_RX_DATA3_IDX 50
#define PARL_TX_DATA3_IDX 50
#define PARL_RX_DATA4_IDX 51
#define PARL_TX_DATA4_IDX 51
#define PARL_RX_DATA5_IDX 52
#define PARL_TX_DATA5_IDX 52
#define PARL_RX_DATA6_IDX 53
#define PARL_TX_DATA6_IDX 53
#define PARL_RX_DATA7_IDX 54
#define PARL_TX_DATA7_IDX 54
#define ANT_SEL4_IDX 55
#define ANT_SEL5_IDX 56
#define ANT_SEL6_IDX 57
#define ANT_SEL7_IDX 58
#define ANT_SEL8_IDX 59
#define ANT_SEL9_IDX 60
#define ANT_SEL10_IDX 61
#define SDIO_TOHOST_INT_OUT_IDX 62
#define FSPICLK_IN_IDX 63
#define FSPICLK_OUT_MUX_IDX 63
#define FSPIQ_IN_IDX 64
#define FSPIQ_OUT_IDX 64
#define FSPID_IN_IDX 65
#define FSPID_OUT_IDX 65
#define FSPIHD_IN_IDX 66
#define FSPIHD_OUT_IDX 66
#define FSPIWP_IN_IDX 67
#define FSPIWP_OUT_IDX 67
#define FSPICS0_IN_IDX 68
#define FSPICS0_OUT_IDX 68
#define PARL_RX_CLK_IN_IDX 69
#define PARL_RX_CLK_OUT_IDX 69
#define PARL_TX_CLK_IN_IDX 70
#define PARL_TX_CLK_OUT_IDX 70
#define RMT_SIG_IN0_IDX 71
#define RMT_SIG_OUT0_IDX 71
#define RMT_SIG_IN1_IDX 72
#define RMT_SIG_OUT1_IDX 72
#define TWAI0_RX_IDX 73
#define TWAI0_TX_IDX 73
#define TWAI0_BUS_OFF_ON_IDX 74
#define TWAI0_CLKOUT_IDX 75
#define TWAI0_STANDBY_IDX 76
#define TWAI1_RX_IDX 77
#define TWAI1_TX_IDX 77
#define TWAI1_BUS_OFF_ON_IDX 78
#define TWAI1_CLKOUT_IDX 79
#define TWAI1_STANDBY_IDX 80
#define EXTERN_PRIORITY_I_IDX 81
#define EXTERN_PRIORITY_O_IDX 81
#define EXTERN_ACTIVE_I_IDX 82
#define EXTERN_ACTIVE_O_IDX 82
#define PCNT_RST_IN0_IDX 83
#define GPIO_SD0_OUT_IDX 83
#define PCNT_RST_IN1_IDX 84
#define GPIO_SD1_OUT_IDX 84
#define PCNT_RST_IN2_IDX 85
#define GPIO_SD2_OUT_IDX 85
#define PCNT_RST_IN3_IDX 86
#define GPIO_SD3_OUT_IDX 86
#define PWM0_SYNC0_IN_IDX 87
#define PWM0_OUT0A_IDX 87
#define PWM0_SYNC1_IN_IDX 88
#define PWM0_OUT0B_IDX 88
#define PWM0_SYNC2_IN_IDX 89
#define PWM0_OUT1A_IDX 89
#define PWM0_F0_IN_IDX 90
#define PWM0_OUT1B_IDX 90
#define PWM0_F1_IN_IDX 91
#define PWM0_OUT2A_IDX 91
#define PWM0_F2_IN_IDX 92
#define PWM0_OUT2B_IDX 92
#define PWM0_CAP0_IN_IDX 93
#define ANT_SEL0_IDX 93
#define PWM0_CAP1_IN_IDX 94
#define ANT_SEL1_IDX 94
#define PWM0_CAP2_IN_IDX 95
#define ANT_SEL2_IDX 95
#define ANT_SEL3_IDX 96
#define SIG_IN_FUNC_97_IDX 97
#define SIG_IN_FUNC97_IDX 97
#define SIG_IN_FUNC_98_IDX 98
#define SIG_IN_FUNC98_IDX 98
#define SIG_IN_FUNC_99_IDX 99
#define SIG_IN_FUNC99_IDX 99
#define SIG_IN_FUNC_100_IDX 100
#define SIG_IN_FUNC100_IDX 100
#define PCNT_SIG_CH0_IN0_IDX 101
#define FSPICS1_OUT_IDX 101
#define PCNT_SIG_CH1_IN0_IDX 102
#define FSPICS2_OUT_IDX 102
#define PCNT_CTRL_CH0_IN0_IDX 103
#define FSPICS3_OUT_IDX 103
#define PCNT_CTRL_CH1_IN0_IDX 104
#define FSPICS4_OUT_IDX 104
#define PCNT_SIG_CH0_IN1_IDX 105
#define FSPICS5_OUT_IDX 105
#define PCNT_SIG_CH1_IN1_IDX 106
#define USB_OTG_CHRG_OUT_IDX 106
#define PCNT_CTRL_CH0_IN1_IDX 107
#define USB_OTG_DISCHRG_OUT_IDX 107
#define PCNT_CTRL_CH1_IN1_IDX 108
#define USB_OTG_PRB_EN_OUT_IDX 108
#define PCNT_SIG_CH0_IN2_IDX 109
#define USB_OTG_SNS_EN_OUT_IDX 109
#define PCNT_SIG_CH1_IN2_IDX 110
#define ANT_SEL11_IDX 110
#define PCNT_CTRL_CH0_IN2_IDX 111
#define ANT_SEL12_IDX 111
#define PCNT_CTRL_CH1_IN2_IDX 112
#define ANT_SEL13_IDX 112
#define PCNT_SIG_CH0_IN3_IDX 113
#define ANT_SEL14_IDX 113
#define PCNT_SIG_CH1_IN3_IDX 114
#define SPICLK_OUT_MUX_IDX 114
#define PCNT_CTRL_CH0_IN3_IDX 115
#define SPICS0_OUT_IDX 115
#define PCNT_CTRL_CH1_IN3_IDX 116
#define SPICS1_OUT_IDX 116
#define GPIO_EVENT_MATRIX_IN0_IDX 117
#define GPIO_TASK_MATRIX_OUT0_IDX 117
#define GPIO_EVENT_MATRIX_IN1_IDX 118
#define GPIO_TASK_MATRIX_OUT1_IDX 118
#define GPIO_EVENT_MATRIX_IN2_IDX 119
#define GPIO_TASK_MATRIX_OUT2_IDX 119
#define GPIO_EVENT_MATRIX_IN3_IDX 120
#define GPIO_TASK_MATRIX_OUT3_IDX 120
#define SPIQ_IN_IDX 121
#define SPIQ_OUT_IDX 121
#define SPID_IN_IDX 122
#define SPID_OUT_IDX 122
#define SPIHD_IN_IDX 123
#define SPIHD_OUT_IDX 123
#define SPIWP_IN_IDX 124
#define SPIWP_OUT_IDX 124
#define CLK_OUT_OUT1_IDX 125
#define CLK_OUT_OUT2_IDX 126
#define CLK_OUT_OUT3_IDX 127
// version date 2301100
#define SIG_GPIO_OUT_IDX 128

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration register */
/** Type of bt_select register
* GPIO bit select register
*/
typedef union {
struct {
/** bt_sel : R/W; bitpos: [31:0]; default: 0;
* GPIO bit select register
*/
uint32_t bt_sel:32;
};
uint32_t val;
} gpio_bt_select_reg_t;
/** Type of out register
* GPIO output register for GPIO0-30
*/
typedef union {
struct {
/** out_data_orig : R/W/SC/WTC; bitpos: [30:0]; default: 0;
* GPIO output register for GPIO0-30
*/
uint32_t out_data_orig:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_out_reg_t;
/** Type of out_w1ts register
* GPIO output set register for GPIO0-30
*/
typedef union {
struct {
/** out_w1ts : WT; bitpos: [30:0]; default: 0;
* GPIO output set register for GPIO0-30
*/
uint32_t out_w1ts:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_out_w1ts_reg_t;
/** Type of out_w1tc register
* GPIO output clear register for GPIO0-30
*/
typedef union {
struct {
/** out_w1tc : WT; bitpos: [30:0]; default: 0;
* GPIO output clear register for GPIO0-30
*/
uint32_t out_w1tc:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_out_w1tc_reg_t;
/** Type of sdio_select register
* GPIO sdio select register
*/
typedef union {
struct {
/** sdio_sel : R/W; bitpos: [7:0]; default: 0;
* GPIO sdio select register
*/
uint32_t sdio_sel:8;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_sdio_select_reg_t;
/** Type of enable register
* GPIO output enable register for GPIO0-30
*/
typedef union {
struct {
/** enable_data : R/W/WTC; bitpos: [30:0]; default: 0;
* GPIO output enable register for GPIO0-30
*/
uint32_t enable_data:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_enable_reg_t;
/** Type of enable_w1ts register
* GPIO output enable set register for GPIO0-30
*/
typedef union {
struct {
/** enable_w1ts : WT; bitpos: [30:0]; default: 0;
* GPIO output enable set register for GPIO0-30
*/
uint32_t enable_w1ts:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_enable_w1ts_reg_t;
/** Type of enable_w1tc register
* GPIO output enable clear register for GPIO0-30
*/
typedef union {
struct {
/** enable_w1tc : WT; bitpos: [30:0]; default: 0;
* GPIO output enable clear register for GPIO0-30
*/
uint32_t enable_w1tc:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_enable_w1tc_reg_t;
/** Type of strap register
* pad strapping register
*/
typedef union {
struct {
/** strapping : RO; bitpos: [15:0]; default: 0;
* pad strapping register
*/
uint32_t strapping:16;
uint32_t reserved_16:16;
};
uint32_t val;
} gpio_strap_reg_t;
/** Type of in register
* GPIO input register for GPIO0-30
*/
typedef union {
struct {
/** in_data_next : RO; bitpos: [30:0]; default: 0;
* GPIO input register for GPIO0-30
*/
uint32_t in_data_next:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_in_reg_t;
/** Type of status register
* GPIO interrupt status register for GPIO0-30
*/
typedef union {
struct {
/** status_interrupt : R/W/WTC; bitpos: [30:0]; default: 0;
* GPIO interrupt status register for GPIO0-30
*/
uint32_t status_interrupt:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_status_reg_t;
/** Type of status_w1ts register
* GPIO interrupt status set register for GPIO0-30
*/
typedef union {
struct {
/** status_w1ts : WT; bitpos: [30:0]; default: 0;
* GPIO interrupt status set register for GPIO0-30
*/
uint32_t status_w1ts:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_status_w1ts_reg_t;
/** Type of status_w1tc register
* GPIO interrupt status clear register for GPIO0-30
*/
typedef union {
struct {
/** status_w1tc : WT; bitpos: [30:0]; default: 0;
* GPIO interrupt status clear register for GPIO0-30
*/
uint32_t status_w1tc:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_status_w1tc_reg_t;
/** Type of pcpu_int register
* GPIO PRO_CPU interrupt status register for GPIO0-30
*/
typedef union {
struct {
/** procpu_int : RO; bitpos: [30:0]; default: 0;
* GPIO PRO_CPU interrupt status register for GPIO0-30
*/
uint32_t procpu_int:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_pcpu_int_reg_t;
/** Type of pcpu_nmi_int register
* GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30
*/
typedef union {
struct {
/** procpu_nmi_int : RO; bitpos: [30:0]; default: 0;
* GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30
*/
uint32_t procpu_nmi_int:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_pcpu_nmi_int_reg_t;
/** Type of cpusdio_int register
* GPIO CPUSDIO interrupt status register for GPIO0-30
*/
typedef union {
struct {
/** sdio_int : RO; bitpos: [30:0]; default: 0;
* GPIO CPUSDIO interrupt status register for GPIO0-30
*/
uint32_t sdio_int:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_cpusdio_int_reg_t;
/** Type of pinn register
* GPIO pin configuration register
*/
typedef union {
struct {
/** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t sync2_bypass:2;
/** pad_driver : R/W; bitpos: [2]; default: 0;
* set this bit to select pad driver. 1:open-drain. 0:normal.
*/
uint32_t pad_driver:1;
/** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
* posedge.
*/
uint32_t sync1_bypass:2;
uint32_t reserved_5:2;
/** int_type : R/W; bitpos: [9:7]; default: 0;
* set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
* posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
* at high level
*/
uint32_t int_type:3;
/** wakeup_enable : R/W; bitpos: [10]; default: 0;
* set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
*/
uint32_t wakeup_enable:1;
/** config : R/W; bitpos: [12:11]; default: 0;
* reserved
*/
uint32_t config:2;
/** int_ena : R/W; bitpos: [17:13]; default: 0;
* set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
* interrupt.
*/
uint32_t int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pinn_reg_t;
/** Type of status_next register
* GPIO interrupt source register for GPIO0-31
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [30:0]; default: 0;
* GPIO interrupt source register for GPIO0-31
*/
uint32_t status_interrupt_next:31;
uint32_t reserved_31:1;
};
uint32_t val;
} gpio_status_next_reg_t;
/** Type of func_in_sel_cfg register
* GPIO input function configuration register
*/
typedef union {
struct {
/** in_sel : R/W; bitpos: [5:0]; default: 60;
* set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
* high level. s=0x3C: set this port always low level.
*/
uint32_t in_sel:6;
/** in_inv_sel : R/W; bitpos: [6]; default: 0;
* set this bit to invert input signal. 1:invert. 0:not invert.
*/
uint32_t in_inv_sel:1;
/** sig_in_sel : R/W; bitpos: [7]; default: 0;
* set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
*/
uint32_t sig_in_sel:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_func_in_sel_cfg_reg_t;
/** Type of func_out_sel_cfg register
* GPIO output function select register
*/
typedef union {
struct {
/** out_sel : R/W/SC; bitpos: [7:0]; default: 128;
* The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
* output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
* GPIO_OUT_REG[n].
*/
uint32_t out_sel:8;
/** out_inv_sel : R/W/SC; bitpos: [8]; default: 0;
* set this bit to invert output signal.1:invert.0:not invert.
*/
uint32_t out_inv_sel:1;
/** oen_sel : R/W; bitpos: [9]; default: 0;
* set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
* enable signal.0:use peripheral output enable signal.
*/
uint32_t oen_sel:1;
/** oen_inv_sel : R/W; bitpos: [10]; default: 0;
* set this bit to invert output enable signal.1:invert.0:not invert.
*/
uint32_t oen_inv_sel:1;
uint32_t reserved_11:21;
};
uint32_t val;
} gpio_func_out_sel_cfg_reg_t;
/** Type of clock_gate register
* GPIO clock gate register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* set this bit to enable GPIO clock gate
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} gpio_clock_gate_reg_t;
/** Type of date register
* GPIO version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36704512;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpio_date_reg_t;
typedef struct gpio_dev_t {
volatile gpio_bt_select_reg_t bt_select;
volatile gpio_out_reg_t out;
volatile gpio_out_w1ts_reg_t out_w1ts;
volatile gpio_out_w1tc_reg_t out_w1tc;
uint32_t reserved_010[3];
volatile gpio_sdio_select_reg_t sdio_select;
volatile gpio_enable_reg_t enable;
volatile gpio_enable_w1ts_reg_t enable_w1ts;
volatile gpio_enable_w1tc_reg_t enable_w1tc;
uint32_t reserved_02c[3];
volatile gpio_strap_reg_t strap;
volatile gpio_in_reg_t in;
uint32_t reserved_040;
volatile gpio_status_reg_t status;
volatile gpio_status_w1ts_reg_t status_w1ts;
volatile gpio_status_w1tc_reg_t status_w1tc;
uint32_t reserved_050[3];
volatile gpio_pcpu_int_reg_t pcpu_int;
volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int;
volatile gpio_cpusdio_int_reg_t cpusdio_int;
uint32_t reserved_068[3];
volatile gpio_pinn_reg_t pin[31];
uint32_t reserved_0f0[23];
volatile gpio_status_next_reg_t status_next;
uint32_t reserved_150;
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128]; /* Reserved func: 1-5, 18, 20, 25-27, 36-39, 43-44, 55-62, 74-76, 78-80, 96, 125-127 */
uint32_t reserved_34b[128];
volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[31];
uint32_t reserved_5d0[23];
volatile gpio_clock_gate_reg_t clock_gate;
uint32_t reserved_630[51];
volatile gpio_date_reg_t date;
} gpio_dev_t;
extern gpio_dev_t GPIO;
#ifndef __cplusplus
_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ATOMIC_ADDR_LOCK_REG register
* hardware lock regsiter
*/
#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
* read to acquire hardware lock, write to release hardware lock
*/
#define ATOMIC_LOCK 0x00000003U
#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATOMIC_LOCK_S)
#define ATOMIC_LOCK_V 0x00000003U
#define ATOMIC_LOCK_S 0
/** ATOMIC_LR_ADDR_REG register
* gloable lr address regsiter
*/
#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
* backup gloable address
*/
#define ATOMIC_GLOABLE_LR_ADDR 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_ADDR_M (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S)
#define ATOMIC_GLOABLE_LR_ADDR_V 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_ADDR_S 0
/** ATOMIC_LR_VALUE_REG register
* gloable lr value regsiter
*/
#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
* backup gloable value
*/
#define ATOMIC_GLOABLE_LR_VALUE 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_VALUE_M (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S)
#define ATOMIC_GLOABLE_LR_VALUE_V 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_VALUE_S 0
/** ATOMIC_LOCK_STATUS_REG register
* lock status regsiter
*/
#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
* read hareware lock status for debug
*/
#define ATOMIC_LOCK_STATUS 0x00000003U
#define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
#define ATOMIC_LOCK_STATUS_V 0x00000003U
#define ATOMIC_LOCK_STATUS_S 0
/** ATOMIC_COUNTER_REG register
* wait counter register
*/
#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10)
/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0;
* delay counter
*/
#define ATOMIC_WAIT_COUNTER 0x0000FFFFU
#define ATOMIC_WAIT_COUNTER_M (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S)
#define ATOMIC_WAIT_COUNTER_V 0x0000FFFFU
#define ATOMIC_WAIT_COUNTER_S 0
#ifdef __cplusplus
}
#endif

98
components/soc/esp32c5/beta3/include/soc/hardware_lock_struct.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of addr_lock register
* hardware lock regsiter
*/
typedef union {
struct {
/** lock : R/W; bitpos: [1:0]; default: 0;
* read to acquire hardware lock, write to release hardware lock
*/
uint32_t lock:2;
uint32_t reserved_2:30;
};
uint32_t val;
} atomic_addr_lock_reg_t;
/** Type of lr_addr register
* gloable lr address regsiter
*/
typedef union {
struct {
/** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0;
* backup gloable address
*/
uint32_t gloable_lr_addr:32;
};
uint32_t val;
} atomic_lr_addr_reg_t;
/** Type of lr_value register
* gloable lr value regsiter
*/
typedef union {
struct {
/** gloable_lr_value : R/W; bitpos: [31:0]; default: 0;
* backup gloable value
*/
uint32_t gloable_lr_value:32;
};
uint32_t val;
} atomic_lr_value_reg_t;
/** Type of lock_status register
* lock status regsiter
*/
typedef union {
struct {
/** lock_status : RO; bitpos: [1:0]; default: 0;
* read hareware lock status for debug
*/
uint32_t lock_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} atomic_lock_status_reg_t;
/** Type of counter register
* wait counter register
*/
typedef union {
struct {
/** wait_counter : R/W; bitpos: [15:0]; default: 0;
* delay counter
*/
uint32_t wait_counter:16;
uint32_t reserved_16:16;
};
uint32_t val;
} atomic_counter_reg_t;
typedef struct atomic_dev_t {
volatile atomic_addr_lock_reg_t addr_lock;
volatile atomic_lr_addr_reg_t lr_addr;
volatile atomic_lr_value_reg_t lr_value;
volatile atomic_lock_status_reg_t lock_status;
volatile atomic_counter_reg_t counter;
} atomic_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
* Process control register 0.
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S)
#define HMAC_SET_START_V 0x00000001U
#define HMAC_SET_START_S 0
/** HMAC_SET_PARA_PURPOSE_REG register
* Configure purpose.
*/
#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
#define HMAC_PURPOSE_SET 0x0000000FU
#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
#define HMAC_PURPOSE_SET_V 0x0000000FU
#define HMAC_PURPOSE_SET_S 0
/** HMAC_SET_PARA_KEY_REG register
* Configure key.
*/
#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
#define HMAC_KEY_SET 0x00000007U
#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
#define HMAC_KEY_SET_V 0x00000007U
#define HMAC_KEY_SET_S 0
/** HMAC_SET_PARA_FINISH_REG register
* Finish initial configuration.
*/
#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
#define HMAC_SET_PARA_END (BIT(0))
#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
#define HMAC_SET_PARA_END_V 0x00000001U
#define HMAC_SET_PARA_END_S 0
/** HMAC_SET_MESSAGE_ONE_REG register
* Process control register 1.
*/
#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
#define HMAC_SET_TEXT_ONE (BIT(0))
#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
#define HMAC_SET_TEXT_ONE_V 0x00000001U
#define HMAC_SET_TEXT_ONE_S 0
/** HMAC_SET_MESSAGE_ING_REG register
* Process control register 2.
*/
#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
#define HMAC_SET_TEXT_ING (BIT(0))
#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
#define HMAC_SET_TEXT_ING_V 0x00000001U
#define HMAC_SET_TEXT_ING_S 0
/** HMAC_SET_MESSAGE_END_REG register
* Process control register 3.
*/
#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
#define HMAC_SET_TEXT_END (BIT(0))
#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
#define HMAC_SET_TEXT_END_V 0x00000001U
#define HMAC_SET_TEXT_END_S 0
/** HMAC_SET_RESULT_FINISH_REG register
* Process control register 4.
*/
#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
#define HMAC_SET_RESULT_END (BIT(0))
#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
#define HMAC_SET_RESULT_END_V 0x00000001U
#define HMAC_SET_RESULT_END_S 0
/** HMAC_SET_INVALIDATE_JTAG_REG register
* Invalidate register 0.
*/
#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
#define HMAC_SET_INVALIDATE_JTAG (BIT(0))
#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U
#define HMAC_SET_INVALIDATE_JTAG_S 0
/** HMAC_SET_INVALIDATE_DS_REG register
* Invalidate register 1.
*/
#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
#define HMAC_SET_INVALIDATE_DS (BIT(0))
#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
#define HMAC_SET_INVALIDATE_DS_V 0x00000001U
#define HMAC_SET_INVALIDATE_DS_S 0
/** HMAC_QUERY_ERROR_REG register
* Error register.
*/
#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
#define HMAC_QUREY_CHECK (BIT(0))
#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
#define HMAC_QUREY_CHECK_V 0x00000001U
#define HMAC_QUREY_CHECK_S 0
/** HMAC_QUERY_BUSY_REG register
* Busy register.
*/
#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
#define HMAC_BUSY_STATE (BIT(0))
#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
#define HMAC_BUSY_STATE_V 0x00000001U
#define HMAC_BUSY_STATE_S 0
/** HMAC_WR_MESSAGE_MEM register
* Message block memory.
*/
#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
/** HMAC_RD_RESULT_MEM register
* Result from upstream.
*/
#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
/** HMAC_SET_MESSAGE_PAD_REG register
* Process control register 5.
*/
#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
#define HMAC_SET_TEXT_PAD (BIT(0))
#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
#define HMAC_SET_TEXT_PAD_V 0x00000001U
#define HMAC_SET_TEXT_PAD_S 0
/** HMAC_ONE_BLOCK_REG register
* Process control register 6.
*/
#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
#define HMAC_SET_ONE_BLOCK (BIT(0))
#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
#define HMAC_SET_ONE_BLOCK_V 0x00000001U
#define HMAC_SET_ONE_BLOCK_S 0
/** HMAC_SOFT_JTAG_CTRL_REG register
* Jtag register 0.
*/
#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
#define HMAC_SOFT_JTAG_CTRL (BIT(0))
#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U
#define HMAC_SOFT_JTAG_CTRL_S 0
/** HMAC_WR_JTAG_REG register
* Jtag register 1.
*/
#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
#define HMAC_WR_JTAG 0xFFFFFFFFU
#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
#define HMAC_WR_JTAG_V 0xFFFFFFFFU
#define HMAC_WR_JTAG_S 0
/** HMAC_DATE_REG register
* Date register.
*/
#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
#define HMAC_DATE 0x3FFFFFFFU
#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S)
#define HMAC_DATE_V 0x3FFFFFFFU
#define HMAC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of set_start register
* Process control register 0.
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_start_reg_t;
/** Type of set_para_purpose register
* Configure purpose.
*/
typedef union {
struct {
/** purpose_set : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
uint32_t purpose_set:4;
uint32_t reserved_4:28;
};
uint32_t val;
} hmac_set_para_purpose_reg_t;
/** Type of set_para_key register
* Configure key.
*/
typedef union {
struct {
/** key_set : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
uint32_t key_set:3;
uint32_t reserved_3:29;
};
uint32_t val;
} hmac_set_para_key_reg_t;
/** Type of set_para_finish register
* Finish initial configuration.
*/
typedef union {
struct {
/** set_para_end : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
uint32_t set_para_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_para_finish_reg_t;
/** Type of set_message_one register
* Process control register 1.
*/
typedef union {
struct {
/** set_text_one : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
uint32_t set_text_one:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_one_reg_t;
/** Type of set_message_ing register
* Process control register 2.
*/
typedef union {
struct {
/** set_text_ing : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
uint32_t set_text_ing:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_ing_reg_t;
/** Type of set_message_end register
* Process control register 3.
*/
typedef union {
struct {
/** set_text_end : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
uint32_t set_text_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_end_reg_t;
/** Type of set_result_finish register
* Process control register 4.
*/
typedef union {
struct {
/** set_result_end : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
uint32_t set_result_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_result_finish_reg_t;
/** Type of set_invalidate_jtag register
* Invalidate register 0.
*/
typedef union {
struct {
/** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
uint32_t set_invalidate_jtag:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_jtag_reg_t;
/** Type of set_invalidate_ds register
* Invalidate register 1.
*/
typedef union {
struct {
/** set_invalidate_ds : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
uint32_t set_invalidate_ds:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_ds_reg_t;
/** Type of set_message_pad register
* Process control register 5.
*/
typedef union {
struct {
/** set_text_pad : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
uint32_t set_text_pad:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_pad_reg_t;
/** Type of one_block register
* Process control register 6.
*/
typedef union {
struct {
/** set_one_block : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
uint32_t set_one_block:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_one_block_reg_t;
/** Type of soft_jtag_ctrl register
* Jtag register 0.
*/
typedef union {
struct {
/** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
uint32_t soft_jtag_ctrl:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_soft_jtag_ctrl_reg_t;
/** Type of wr_jtag register
* Jtag register 1.
*/
typedef union {
struct {
/** wr_jtag : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
uint32_t wr_jtag:32;
};
uint32_t val;
} hmac_wr_jtag_reg_t;
/** Group: Status Register */
/** Type of query_error register
* Error register.
*/
typedef union {
struct {
/** qurey_check : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
uint32_t qurey_check:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_error_reg_t;
/** Type of query_busy register
* Busy register.
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_busy_reg_t;
/** Group: Memory Type */
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} hmac_date_reg_t;
typedef struct hmac_dev_t {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;
volatile hmac_set_para_key_reg_t set_para_key;
volatile hmac_set_para_finish_reg_t set_para_finish;
volatile hmac_set_message_one_reg_t set_message_one;
volatile hmac_set_message_ing_reg_t set_message_ing;
volatile hmac_set_message_end_reg_t set_message_end;
volatile hmac_set_result_finish_reg_t set_result_finish;
volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
volatile hmac_query_error_reg_t query_error;
volatile hmac_query_busy_reg_t query_busy;
uint32_t reserved_070[4];
volatile uint32_t wr_message[16];
volatile uint32_t rd_result[8];
uint32_t reserved_0e0[4];
volatile hmac_set_message_pad_reg_t set_message_pad;
volatile hmac_one_block_reg_t one_block;
volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
volatile hmac_wr_jtag_reg_t wr_jtag;
uint32_t reserved_100[63];
volatile hmac_date_reg_t date;
} hmac_dev_t;
extern hmac_dev_t HMAC;
#ifndef __cplusplus
_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
* EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
*/
#define HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYS_BASE + 0x0)
/** HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
*/
#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S)
#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S 0
/** HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/** HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
* Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
*/
#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U
#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/** HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
*/
#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
/** HP_SYS_SRAM_USAGE_CONF_REG register
* HP memory usage configuration register
*/
#define HP_SYS_SRAM_USAGE_CONF_REG (DR_REG_HP_SYS_BASE + 0x4)
/** HP_SYS_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_CACHE_USAGE (BIT(0))
#define HP_SYS_CACHE_USAGE_M (HP_SYS_CACHE_USAGE_V << HP_SYS_CACHE_USAGE_S)
#define HP_SYS_CACHE_USAGE_V 0x00000001U
#define HP_SYS_CACHE_USAGE_S 0
/** HP_SYS_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
#define HP_SYS_SRAM_USAGE 0x0000000FU
#define HP_SYS_SRAM_USAGE_M (HP_SYS_SRAM_USAGE_V << HP_SYS_SRAM_USAGE_S)
#define HP_SYS_SRAM_USAGE_V 0x0000000FU
#define HP_SYS_SRAM_USAGE_S 8
/** HP_SYS_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0;
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
*/
#define HP_SYS_MAC_DUMP_ALLOC (BIT(16))
#define HP_SYS_MAC_DUMP_ALLOC_M (HP_SYS_MAC_DUMP_ALLOC_V << HP_SYS_MAC_DUMP_ALLOC_S)
#define HP_SYS_MAC_DUMP_ALLOC_V 0x00000001U
#define HP_SYS_MAC_DUMP_ALLOC_S 16
/** HP_SYS_SEC_DPA_CONF_REG register
* HP anti-DPA security configuration register
*/
#define HP_SYS_SEC_DPA_CONF_REG (DR_REG_HP_SYS_BASE + 0x8)
/** HP_SYS_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
*/
#define HP_SYS_SEC_DPA_LEVEL 0x00000003U
#define HP_SYS_SEC_DPA_LEVEL_M (HP_SYS_SEC_DPA_LEVEL_V << HP_SYS_SEC_DPA_LEVEL_S)
#define HP_SYS_SEC_DPA_LEVEL_V 0x00000003U
#define HP_SYS_SEC_DPA_LEVEL_S 0
/** HP_SYS_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
* This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
* (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
*/
#define HP_SYS_SEC_DPA_CFG_SEL (BIT(2))
#define HP_SYS_SEC_DPA_CFG_SEL_M (HP_SYS_SEC_DPA_CFG_SEL_V << HP_SYS_SEC_DPA_CFG_SEL_S)
#define HP_SYS_SEC_DPA_CFG_SEL_V 0x00000001U
#define HP_SYS_SEC_DPA_CFG_SEL_S 2
/** HP_SYS_CPU_PERI_TIMEOUT_CONF_REG register
* CPU_PERI_TIMEOUT configuration register
*/
#define HP_SYS_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0xc)
/** HP_SYS_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYS_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYS_CPU_PERI_TIMEOUT_THRES_M (HP_SYS_CPU_PERI_TIMEOUT_THRES_V << HP_SYS_CPU_PERI_TIMEOUT_THRES_S)
#define HP_SYS_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYS_CPU_PERI_TIMEOUT_THRES_S 0
/** HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing cpu peripheral
* registers
*/
#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG register
* CPU_PERI_TIMEOUT_ADDR register
*/
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x10)
/** HP_SYS_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_M (HP_SYS_CPU_PERI_TIMEOUT_ADDR_V << HP_SYS_CPU_PERI_TIMEOUT_ADDR_S)
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_S 0
/** HP_SYS_CPU_PERI_TIMEOUT_UID_REG register
* CPU_PERI_TIMEOUT_UID register
*/
#define HP_SYS_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x14)
/** HP_SYS_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYS_CPU_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYS_CPU_PERI_TIMEOUT_UID_M (HP_SYS_CPU_PERI_TIMEOUT_UID_V << HP_SYS_CPU_PERI_TIMEOUT_UID_S)
#define HP_SYS_CPU_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYS_CPU_PERI_TIMEOUT_UID_S 0
/** HP_SYS_HP_PERI_TIMEOUT_CONF_REG register
* HP_PERI_TIMEOUT configuration register
*/
#define HP_SYS_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x18)
/** HP_SYS_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYS_HP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYS_HP_PERI_TIMEOUT_THRES_M (HP_SYS_HP_PERI_TIMEOUT_THRES_V << HP_SYS_HP_PERI_TIMEOUT_THRES_S)
#define HP_SYS_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYS_HP_PERI_TIMEOUT_THRES_S 0
/** HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
*/
#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYS_HP_PERI_TIMEOUT_ADDR_REG register
* HP_PERI_TIMEOUT_ADDR register
*/
#define HP_SYS_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x1c)
/** HP_SYS_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYS_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYS_HP_PERI_TIMEOUT_ADDR_M (HP_SYS_HP_PERI_TIMEOUT_ADDR_V << HP_SYS_HP_PERI_TIMEOUT_ADDR_S)
#define HP_SYS_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYS_HP_PERI_TIMEOUT_ADDR_S 0
/** HP_SYS_HP_PERI_TIMEOUT_UID_REG register
* HP_PERI_TIMEOUT_UID register
*/
#define HP_SYS_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x20)
/** HP_SYS_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYS_HP_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYS_HP_PERI_TIMEOUT_UID_M (HP_SYS_HP_PERI_TIMEOUT_UID_V << HP_SYS_HP_PERI_TIMEOUT_UID_S)
#define HP_SYS_HP_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYS_HP_PERI_TIMEOUT_UID_S 0
/** HP_SYS_MODEM_PERI_TIMEOUT_CONF_REG register
* MODEM_PERI_TIMEOUT configuration register
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x24)
/** HP_SYS_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYS_MODEM_PERI_TIMEOUT_THRES_M (HP_SYS_MODEM_PERI_TIMEOUT_THRES_V << HP_SYS_MODEM_PERI_TIMEOUT_THRES_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYS_MODEM_PERI_TIMEOUT_THRES_S 0
/** HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYS_MODEM_PERI_TIMEOUT_ADDR_REG register
* MODEM_PERI_TIMEOUT_ADDR register
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x28)
/** HP_SYS_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYS_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYS_MODEM_PERI_TIMEOUT_ADDR_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_S 0
/** HP_SYS_MODEM_PERI_TIMEOUT_UID_REG register
* MODEM_PERI_TIMEOUT_UID register
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x2c)
/** HP_SYS_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYS_MODEM_PERI_TIMEOUT_UID_M (HP_SYS_MODEM_PERI_TIMEOUT_UID_V << HP_SYS_MODEM_PERI_TIMEOUT_UID_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYS_MODEM_PERI_TIMEOUT_UID_S 0
/** HP_SYS_SDIO_CTRL_REG register
* SDIO Control configuration register
*/
#define HP_SYS_SDIO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x30)
/** HP_SYS_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
#define HP_SYS_DIS_SDIO_PROB (BIT(0))
#define HP_SYS_DIS_SDIO_PROB_M (HP_SYS_DIS_SDIO_PROB_V << HP_SYS_DIS_SDIO_PROB_S)
#define HP_SYS_DIS_SDIO_PROB_V 0x00000001U
#define HP_SYS_DIS_SDIO_PROB_S 0
/** HP_SYS_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
#define HP_SYS_SDIO_WIN_ACCESS_EN (BIT(1))
#define HP_SYS_SDIO_WIN_ACCESS_EN_M (HP_SYS_SDIO_WIN_ACCESS_EN_V << HP_SYS_SDIO_WIN_ACCESS_EN_S)
#define HP_SYS_SDIO_WIN_ACCESS_EN_V 0x00000001U
#define HP_SYS_SDIO_WIN_ACCESS_EN_S 1
/** HP_SYS_ROM_TABLE_LOCK_REG register
* Rom-Table lock register
*/
#define HP_SYS_ROM_TABLE_LOCK_REG (DR_REG_HP_SYS_BASE + 0x38)
/** HP_SYS_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
* XXXX
*/
#define HP_SYS_ROM_TABLE_LOCK (BIT(0))
#define HP_SYS_ROM_TABLE_LOCK_M (HP_SYS_ROM_TABLE_LOCK_V << HP_SYS_ROM_TABLE_LOCK_S)
#define HP_SYS_ROM_TABLE_LOCK_V 0x00000001U
#define HP_SYS_ROM_TABLE_LOCK_S 0
/** HP_SYS_ROM_TABLE_REG register
* Rom-Table register
*/
#define HP_SYS_ROM_TABLE_REG (DR_REG_HP_SYS_BASE + 0x3c)
/** HP_SYS_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
* XXXX
*/
#define HP_SYS_ROM_TABLE 0xFFFFFFFFU
#define HP_SYS_ROM_TABLE_M (HP_SYS_ROM_TABLE_V << HP_SYS_ROM_TABLE_S)
#define HP_SYS_ROM_TABLE_V 0xFFFFFFFFU
#define HP_SYS_ROM_TABLE_S 0
/** HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG register
* Core Debug runstall configure register
*/
#define HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x40)
/** HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
* Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
*/
#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0))
#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S)
#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V 0x00000001U
#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S 0
/** HP_SYS_CORE_RUNSTALLED : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
* not stalled.
*/
#define HP_SYS_CORE_RUNSTALLED (BIT(1))
#define HP_SYS_CORE_RUNSTALLED_M (HP_SYS_CORE_RUNSTALLED_V << HP_SYS_CORE_RUNSTALLED_S)
#define HP_SYS_CORE_RUNSTALLED_V 0x00000001U
#define HP_SYS_CORE_RUNSTALLED_S 1
/** HP_SYS_MEM_TEST_CONF_REG register
* MEM_TEST configuration register
*/
#define HP_SYS_MEM_TEST_CONF_REG (DR_REG_HP_SYS_BASE + 0x44)
/** HP_SYS_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
*/
#define HP_SYS_HP_MEM_WPULSE 0x00000007U
#define HP_SYS_HP_MEM_WPULSE_M (HP_SYS_HP_MEM_WPULSE_V << HP_SYS_HP_MEM_WPULSE_S)
#define HP_SYS_HP_MEM_WPULSE_V 0x00000007U
#define HP_SYS_HP_MEM_WPULSE_S 0
/** HP_SYS_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
*/
#define HP_SYS_HP_MEM_WA 0x00000007U
#define HP_SYS_HP_MEM_WA_M (HP_SYS_HP_MEM_WA_V << HP_SYS_HP_MEM_WA_S)
#define HP_SYS_HP_MEM_WA_V 0x00000007U
#define HP_SYS_HP_MEM_WA_S 3
/** HP_SYS_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
*/
#define HP_SYS_HP_MEM_RA 0x00000003U
#define HP_SYS_HP_MEM_RA_M (HP_SYS_HP_MEM_RA_V << HP_SYS_HP_MEM_RA_S)
#define HP_SYS_HP_MEM_RA_V 0x00000003U
#define HP_SYS_HP_MEM_RA_S 6
/** HP_SYS_AUDIO_CODEC_SDADC_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_SDADC_CNTL_REG (DR_REG_HP_SYS_BASE + 0x50)
/** HP_SYS_SDADC_PAD_EN_VNCP : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_SDADC_PAD_EN_VNCP (BIT(0))
#define HP_SYS_SDADC_PAD_EN_VNCP_M (HP_SYS_SDADC_PAD_EN_VNCP_V << HP_SYS_SDADC_PAD_EN_VNCP_S)
#define HP_SYS_SDADC_PAD_EN_VNCP_V 0x00000001U
#define HP_SYS_SDADC_PAD_EN_VNCP_S 0
/** HP_SYS_SDADC_PAD_FAST_CHG : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYS_SDADC_PAD_FAST_CHG (BIT(1))
#define HP_SYS_SDADC_PAD_FAST_CHG_M (HP_SYS_SDADC_PAD_FAST_CHG_V << HP_SYS_SDADC_PAD_FAST_CHG_S)
#define HP_SYS_SDADC_PAD_FAST_CHG_V 0x00000001U
#define HP_SYS_SDADC_PAD_FAST_CHG_S 1
/** HP_SYS_SDADC_PAD_EN_0V : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define HP_SYS_SDADC_PAD_EN_0V (BIT(2))
#define HP_SYS_SDADC_PAD_EN_0V_M (HP_SYS_SDADC_PAD_EN_0V_V << HP_SYS_SDADC_PAD_EN_0V_S)
#define HP_SYS_SDADC_PAD_EN_0V_V 0x00000001U
#define HP_SYS_SDADC_PAD_EN_0V_S 2
/** HP_SYS_SDADC_EN_CHOPPER : R/W; bitpos: [3]; default: 1;
* reserved
*/
#define HP_SYS_SDADC_EN_CHOPPER (BIT(3))
#define HP_SYS_SDADC_EN_CHOPPER_M (HP_SYS_SDADC_EN_CHOPPER_V << HP_SYS_SDADC_EN_CHOPPER_S)
#define HP_SYS_SDADC_EN_CHOPPER_V 0x00000001U
#define HP_SYS_SDADC_EN_CHOPPER_S 3
/** HP_SYS_SDADC_EN_DEM : R/W; bitpos: [4]; default: 1;
* reserved
*/
#define HP_SYS_SDADC_EN_DEM (BIT(4))
#define HP_SYS_SDADC_EN_DEM_M (HP_SYS_SDADC_EN_DEM_V << HP_SYS_SDADC_EN_DEM_S)
#define HP_SYS_SDADC_EN_DEM_V 0x00000001U
#define HP_SYS_SDADC_EN_DEM_S 4
/** HP_SYS_SDADC_DREG_OA : R/W; bitpos: [7:5]; default: 3;
* reserved
*/
#define HP_SYS_SDADC_DREG_OA 0x00000007U
#define HP_SYS_SDADC_DREG_OA_M (HP_SYS_SDADC_DREG_OA_V << HP_SYS_SDADC_DREG_OA_S)
#define HP_SYS_SDADC_DREG_OA_V 0x00000007U
#define HP_SYS_SDADC_DREG_OA_S 5
/** HP_SYS_SDADC_DGAIN_INPUT : R/W; bitpos: [9:8]; default: 3;
* reserved
*/
#define HP_SYS_SDADC_DGAIN_INPUT 0x00000003U
#define HP_SYS_SDADC_DGAIN_INPUT_M (HP_SYS_SDADC_DGAIN_INPUT_V << HP_SYS_SDADC_DGAIN_INPUT_S)
#define HP_SYS_SDADC_DGAIN_INPUT_V 0x00000003U
#define HP_SYS_SDADC_DGAIN_INPUT_S 8
/** HP_SYS_SDADC_DCAP : R/W; bitpos: [14:10]; default: 12;
* reserved
*/
#define HP_SYS_SDADC_DCAP 0x0000001FU
#define HP_SYS_SDADC_DCAP_M (HP_SYS_SDADC_DCAP_V << HP_SYS_SDADC_DCAP_S)
#define HP_SYS_SDADC_DCAP_V 0x0000001FU
#define HP_SYS_SDADC_DCAP_S 10
/** HP_SYS_AUDIO_CODEC_DAC_L_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DAC_L_CNTL_REG (DR_REG_HP_SYS_BASE + 0x54)
/** HP_SYS_ENHANCE_L_AUDIO_DAC : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_ENHANCE_L_AUDIO_DAC (BIT(0))
#define HP_SYS_ENHANCE_L_AUDIO_DAC_M (HP_SYS_ENHANCE_L_AUDIO_DAC_V << HP_SYS_ENHANCE_L_AUDIO_DAC_S)
#define HP_SYS_ENHANCE_L_AUDIO_DAC_V 0x00000001U
#define HP_SYS_ENHANCE_L_AUDIO_DAC_S 0
/** HP_SYS_GAIN_L_AUDIO_DAC : R/W; bitpos: [5:1]; default: 19;
* reserved
*/
#define HP_SYS_GAIN_L_AUDIO_DAC 0x0000001FU
#define HP_SYS_GAIN_L_AUDIO_DAC_M (HP_SYS_GAIN_L_AUDIO_DAC_V << HP_SYS_GAIN_L_AUDIO_DAC_S)
#define HP_SYS_GAIN_L_AUDIO_DAC_V 0x0000001FU
#define HP_SYS_GAIN_L_AUDIO_DAC_S 1
/** HP_SYS_MUTE_L_AUDIO_DAC : R/W; bitpos: [6]; default: 0;
* reserved
*/
#define HP_SYS_MUTE_L_AUDIO_DAC (BIT(6))
#define HP_SYS_MUTE_L_AUDIO_DAC_M (HP_SYS_MUTE_L_AUDIO_DAC_V << HP_SYS_MUTE_L_AUDIO_DAC_S)
#define HP_SYS_MUTE_L_AUDIO_DAC_V 0x00000001U
#define HP_SYS_MUTE_L_AUDIO_DAC_S 6
/** HP_SYS_XPD_L_AUDIO_DAC : R/W; bitpos: [7]; default: 0;
* reserved
*/
#define HP_SYS_XPD_L_AUDIO_DAC (BIT(7))
#define HP_SYS_XPD_L_AUDIO_DAC_M (HP_SYS_XPD_L_AUDIO_DAC_V << HP_SYS_XPD_L_AUDIO_DAC_S)
#define HP_SYS_XPD_L_AUDIO_DAC_V 0x00000001U
#define HP_SYS_XPD_L_AUDIO_DAC_S 7
/** HP_SYS_AUDIO_CODEC_DAC_L_DIN_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DAC_L_DIN_REG (DR_REG_HP_SYS_BASE + 0x58)
/** HP_SYS_DAC_DIN_L : R/W; bitpos: [21:0]; default: 0;
* reserved
*/
#define HP_SYS_DAC_DIN_L 0x003FFFFFU
#define HP_SYS_DAC_DIN_L_M (HP_SYS_DAC_DIN_L_V << HP_SYS_DAC_DIN_L_S)
#define HP_SYS_DAC_DIN_L_V 0x003FFFFFU
#define HP_SYS_DAC_DIN_L_S 0
/** HP_SYS_AUDIO_CODEC_DAC_R_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DAC_R_CNTL_REG (DR_REG_HP_SYS_BASE + 0x5c)
/** HP_SYS_ENHANCE_R_AUDIO_DAC : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_ENHANCE_R_AUDIO_DAC (BIT(0))
#define HP_SYS_ENHANCE_R_AUDIO_DAC_M (HP_SYS_ENHANCE_R_AUDIO_DAC_V << HP_SYS_ENHANCE_R_AUDIO_DAC_S)
#define HP_SYS_ENHANCE_R_AUDIO_DAC_V 0x00000001U
#define HP_SYS_ENHANCE_R_AUDIO_DAC_S 0
/** HP_SYS_GAIN_R_AUDIO_DAC : R/W; bitpos: [5:1]; default: 19;
* reserved
*/
#define HP_SYS_GAIN_R_AUDIO_DAC 0x0000001FU
#define HP_SYS_GAIN_R_AUDIO_DAC_M (HP_SYS_GAIN_R_AUDIO_DAC_V << HP_SYS_GAIN_R_AUDIO_DAC_S)
#define HP_SYS_GAIN_R_AUDIO_DAC_V 0x0000001FU
#define HP_SYS_GAIN_R_AUDIO_DAC_S 1
/** HP_SYS_MUTE_R_AUDIO_DAC : R/W; bitpos: [6]; default: 0;
* reserved
*/
#define HP_SYS_MUTE_R_AUDIO_DAC (BIT(6))
#define HP_SYS_MUTE_R_AUDIO_DAC_M (HP_SYS_MUTE_R_AUDIO_DAC_V << HP_SYS_MUTE_R_AUDIO_DAC_S)
#define HP_SYS_MUTE_R_AUDIO_DAC_V 0x00000001U
#define HP_SYS_MUTE_R_AUDIO_DAC_S 6
/** HP_SYS_XPD_R_AUDIO_DAC : R/W; bitpos: [7]; default: 0;
* reserved
*/
#define HP_SYS_XPD_R_AUDIO_DAC (BIT(7))
#define HP_SYS_XPD_R_AUDIO_DAC_M (HP_SYS_XPD_R_AUDIO_DAC_V << HP_SYS_XPD_R_AUDIO_DAC_S)
#define HP_SYS_XPD_R_AUDIO_DAC_V 0x00000001U
#define HP_SYS_XPD_R_AUDIO_DAC_S 7
/** HP_SYS_AUDIO_CODEC_DAC_R_DIN_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DAC_R_DIN_REG (DR_REG_HP_SYS_BASE + 0x60)
/** HP_SYS_DAC_DIN_R : R/W; bitpos: [21:0]; default: 0;
* reserved
*/
#define HP_SYS_DAC_DIN_R 0x003FFFFFU
#define HP_SYS_DAC_DIN_R_M (HP_SYS_DAC_DIN_R_V << HP_SYS_DAC_DIN_R_S)
#define HP_SYS_DAC_DIN_R_V 0x003FFFFFU
#define HP_SYS_DAC_DIN_R_S 0
/** HP_SYS_AUDIO_CODEC_PLL_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_PLL_CNTL_REG (DR_REG_HP_SYS_BASE + 0x64)
/** HP_SYS_CAL_STOP_PLLA : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_CAL_STOP_PLLA (BIT(0))
#define HP_SYS_CAL_STOP_PLLA_M (HP_SYS_CAL_STOP_PLLA_V << HP_SYS_CAL_STOP_PLLA_S)
#define HP_SYS_CAL_STOP_PLLA_V 0x00000001U
#define HP_SYS_CAL_STOP_PLLA_S 0
/** HP_SYS_CAL_END_PLLA : RO; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYS_CAL_END_PLLA (BIT(1))
#define HP_SYS_CAL_END_PLLA_M (HP_SYS_CAL_END_PLLA_V << HP_SYS_CAL_END_PLLA_S)
#define HP_SYS_CAL_END_PLLA_V 0x00000001U
#define HP_SYS_CAL_END_PLLA_S 1
/** HP_SYS_AUDIO_CODEC_DATA_MODE_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DATA_MODE_CNTL_REG (DR_REG_HP_SYS_BASE + 0x68)
/** HP_SYS_AUDIO_ADC_MODE : R/W; bitpos: [1:0]; default: 0;
* reserved
*/
#define HP_SYS_AUDIO_ADC_MODE 0x00000003U
#define HP_SYS_AUDIO_ADC_MODE_M (HP_SYS_AUDIO_ADC_MODE_V << HP_SYS_AUDIO_ADC_MODE_S)
#define HP_SYS_AUDIO_ADC_MODE_V 0x00000003U
#define HP_SYS_AUDIO_ADC_MODE_S 0
/** HP_SYS_AUDIO_DAC_DSM_MODE_R : R/W; bitpos: [3:2]; default: 0;
* reserved
*/
#define HP_SYS_AUDIO_DAC_DSM_MODE_R 0x00000003U
#define HP_SYS_AUDIO_DAC_DSM_MODE_R_M (HP_SYS_AUDIO_DAC_DSM_MODE_R_V << HP_SYS_AUDIO_DAC_DSM_MODE_R_S)
#define HP_SYS_AUDIO_DAC_DSM_MODE_R_V 0x00000003U
#define HP_SYS_AUDIO_DAC_DSM_MODE_R_S 2
/** HP_SYS_AUDIO_DAC_DSM_MODE_L : R/W; bitpos: [5:4]; default: 0;
* reserved
*/
#define HP_SYS_AUDIO_DAC_DSM_MODE_L 0x00000003U
#define HP_SYS_AUDIO_DAC_DSM_MODE_L_M (HP_SYS_AUDIO_DAC_DSM_MODE_L_V << HP_SYS_AUDIO_DAC_DSM_MODE_L_S)
#define HP_SYS_AUDIO_DAC_DSM_MODE_L_V 0x00000003U
#define HP_SYS_AUDIO_DAC_DSM_MODE_L_S 4
/** HP_SYS_SPROM_CTRL_REG register
* reserved
*/
#define HP_SYS_SPROM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70)
/** HP_SYS_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
* reserved
*/
#define HP_SYS_SPROM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYS_SPROM_MEM_AUX_CTRL_M (HP_SYS_SPROM_MEM_AUX_CTRL_V << HP_SYS_SPROM_MEM_AUX_CTRL_S)
#define HP_SYS_SPROM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYS_SPROM_MEM_AUX_CTRL_S 0
/** HP_SYS_SPRAM_CTRL_REG register
* reserved
*/
#define HP_SYS_SPRAM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x74)
/** HP_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
#define HP_SYS_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYS_SPRAM_MEM_AUX_CTRL_M (HP_SYS_SPRAM_MEM_AUX_CTRL_V << HP_SYS_SPRAM_MEM_AUX_CTRL_S)
#define HP_SYS_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYS_SPRAM_MEM_AUX_CTRL_S 0
/** HP_SYS_SPRF_CTRL_REG register
* reserved
*/
#define HP_SYS_SPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x78)
/** HP_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
#define HP_SYS_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYS_SPRF_MEM_AUX_CTRL_M (HP_SYS_SPRF_MEM_AUX_CTRL_V << HP_SYS_SPRF_MEM_AUX_CTRL_S)
#define HP_SYS_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYS_SPRF_MEM_AUX_CTRL_S 0
/** HP_SYS_SDPRF_CTRL_REG register
* reserved
*/
#define HP_SYS_SDPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x7c)
/** HP_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
#define HP_SYS_SDPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYS_SDPRF_MEM_AUX_CTRL_M (HP_SYS_SDPRF_MEM_AUX_CTRL_V << HP_SYS_SDPRF_MEM_AUX_CTRL_S)
#define HP_SYS_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYS_SDPRF_MEM_AUX_CTRL_S 0
/** HP_SYS_AUDIO_CODEX_CTRL0_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEX_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x80)
/** HP_SYS_DAC_IN_R1_IE : R/W; bitpos: [0]; default: 1;
* reserved
*/
#define HP_SYS_DAC_IN_R1_IE (BIT(0))
#define HP_SYS_DAC_IN_R1_IE_M (HP_SYS_DAC_IN_R1_IE_V << HP_SYS_DAC_IN_R1_IE_S)
#define HP_SYS_DAC_IN_R1_IE_V 0x00000001U
#define HP_SYS_DAC_IN_R1_IE_S 0
/** HP_SYS_DAC_IN_R1_OE : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYS_DAC_IN_R1_OE (BIT(1))
#define HP_SYS_DAC_IN_R1_OE_M (HP_SYS_DAC_IN_R1_OE_V << HP_SYS_DAC_IN_R1_OE_S)
#define HP_SYS_DAC_IN_R1_OE_V 0x00000001U
#define HP_SYS_DAC_IN_R1_OE_S 1
/** HP_SYS_DAC_IN_R0_IE : R/W; bitpos: [2]; default: 1;
* reserved
*/
#define HP_SYS_DAC_IN_R0_IE (BIT(2))
#define HP_SYS_DAC_IN_R0_IE_M (HP_SYS_DAC_IN_R0_IE_V << HP_SYS_DAC_IN_R0_IE_S)
#define HP_SYS_DAC_IN_R0_IE_V 0x00000001U
#define HP_SYS_DAC_IN_R0_IE_S 2
/** HP_SYS_DAC_IN_R0_OE : R/W; bitpos: [3]; default: 0;
* reserved
*/
#define HP_SYS_DAC_IN_R0_OE (BIT(3))
#define HP_SYS_DAC_IN_R0_OE_M (HP_SYS_DAC_IN_R0_OE_V << HP_SYS_DAC_IN_R0_OE_S)
#define HP_SYS_DAC_IN_R0_OE_V 0x00000001U
#define HP_SYS_DAC_IN_R0_OE_S 3
/** HP_SYS_ADC_DATA_4_IE : R/W; bitpos: [4]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_4_IE (BIT(4))
#define HP_SYS_ADC_DATA_4_IE_M (HP_SYS_ADC_DATA_4_IE_V << HP_SYS_ADC_DATA_4_IE_S)
#define HP_SYS_ADC_DATA_4_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_4_IE_S 4
/** HP_SYS_ADC_DATA_4_OE : R/W; bitpos: [5]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_4_OE (BIT(5))
#define HP_SYS_ADC_DATA_4_OE_M (HP_SYS_ADC_DATA_4_OE_V << HP_SYS_ADC_DATA_4_OE_S)
#define HP_SYS_ADC_DATA_4_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_4_OE_S 5
/** HP_SYS_ADC_DATA_3_IE : R/W; bitpos: [6]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_3_IE (BIT(6))
#define HP_SYS_ADC_DATA_3_IE_M (HP_SYS_ADC_DATA_3_IE_V << HP_SYS_ADC_DATA_3_IE_S)
#define HP_SYS_ADC_DATA_3_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_3_IE_S 6
/** HP_SYS_ADC_DATA_3_OE : R/W; bitpos: [7]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_3_OE (BIT(7))
#define HP_SYS_ADC_DATA_3_OE_M (HP_SYS_ADC_DATA_3_OE_V << HP_SYS_ADC_DATA_3_OE_S)
#define HP_SYS_ADC_DATA_3_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_3_OE_S 7
/** HP_SYS_ADC_DATA_2_IE : R/W; bitpos: [8]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_2_IE (BIT(8))
#define HP_SYS_ADC_DATA_2_IE_M (HP_SYS_ADC_DATA_2_IE_V << HP_SYS_ADC_DATA_2_IE_S)
#define HP_SYS_ADC_DATA_2_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_2_IE_S 8
/** HP_SYS_ADC_DATA_2_OE : R/W; bitpos: [9]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_2_OE (BIT(9))
#define HP_SYS_ADC_DATA_2_OE_M (HP_SYS_ADC_DATA_2_OE_V << HP_SYS_ADC_DATA_2_OE_S)
#define HP_SYS_ADC_DATA_2_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_2_OE_S 9
/** HP_SYS_ADC_DATA_1_IE : R/W; bitpos: [10]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_1_IE (BIT(10))
#define HP_SYS_ADC_DATA_1_IE_M (HP_SYS_ADC_DATA_1_IE_V << HP_SYS_ADC_DATA_1_IE_S)
#define HP_SYS_ADC_DATA_1_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_1_IE_S 10
/** HP_SYS_ADC_DATA_1_OE : R/W; bitpos: [11]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_1_OE (BIT(11))
#define HP_SYS_ADC_DATA_1_OE_M (HP_SYS_ADC_DATA_1_OE_V << HP_SYS_ADC_DATA_1_OE_S)
#define HP_SYS_ADC_DATA_1_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_1_OE_S 11
/** HP_SYS_ADC_DATA_0_IE : R/W; bitpos: [12]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_0_IE (BIT(12))
#define HP_SYS_ADC_DATA_0_IE_M (HP_SYS_ADC_DATA_0_IE_V << HP_SYS_ADC_DATA_0_IE_S)
#define HP_SYS_ADC_DATA_0_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_0_IE_S 12
/** HP_SYS_ADC_DATA_0_OE : R/W; bitpos: [13]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_0_OE (BIT(13))
#define HP_SYS_ADC_DATA_0_OE_M (HP_SYS_ADC_DATA_0_OE_V << HP_SYS_ADC_DATA_0_OE_S)
#define HP_SYS_ADC_DATA_0_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_0_OE_S 13
/** HP_SYS_ADC_CK_DATA_IE : R/W; bitpos: [14]; default: 0;
* reserved
*/
#define HP_SYS_ADC_CK_DATA_IE (BIT(14))
#define HP_SYS_ADC_CK_DATA_IE_M (HP_SYS_ADC_CK_DATA_IE_V << HP_SYS_ADC_CK_DATA_IE_S)
#define HP_SYS_ADC_CK_DATA_IE_V 0x00000001U
#define HP_SYS_ADC_CK_DATA_IE_S 14
/** HP_SYS_ADC_CK_DATA_OE : R/W; bitpos: [15]; default: 1;
* reserved
*/
#define HP_SYS_ADC_CK_DATA_OE (BIT(15))
#define HP_SYS_ADC_CK_DATA_OE_M (HP_SYS_ADC_CK_DATA_OE_V << HP_SYS_ADC_CK_DATA_OE_S)
#define HP_SYS_ADC_CK_DATA_OE_V 0x00000001U
#define HP_SYS_ADC_CK_DATA_OE_S 15
/** HP_SYS_RND_ECO_REG register
* redcy eco register.
*/
#define HP_SYS_RND_ECO_REG (DR_REG_HP_SYS_BASE + 0x3e0)
/** HP_SYS_REDCY_ENA : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYS_REDCY_ENA (BIT(0))
#define HP_SYS_REDCY_ENA_M (HP_SYS_REDCY_ENA_V << HP_SYS_REDCY_ENA_S)
#define HP_SYS_REDCY_ENA_V 0x00000001U
#define HP_SYS_REDCY_ENA_S 0
/** HP_SYS_REDCY_RESULT : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYS_REDCY_RESULT (BIT(1))
#define HP_SYS_REDCY_RESULT_M (HP_SYS_REDCY_RESULT_V << HP_SYS_REDCY_RESULT_S)
#define HP_SYS_REDCY_RESULT_V 0x00000001U
#define HP_SYS_REDCY_RESULT_S 1
/** HP_SYS_RND_ECO_LOW_REG register
* redcy eco low register.
*/
#define HP_SYS_RND_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0x3e4)
/** HP_SYS_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYS_REDCY_LOW 0xFFFFFFFFU
#define HP_SYS_REDCY_LOW_M (HP_SYS_REDCY_LOW_V << HP_SYS_REDCY_LOW_S)
#define HP_SYS_REDCY_LOW_V 0xFFFFFFFFU
#define HP_SYS_REDCY_LOW_S 0
/** HP_SYS_RND_ECO_HIGH_REG register
* redcy eco high register.
*/
#define HP_SYS_RND_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0x3e8)
/** HP_SYS_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
#define HP_SYS_REDCY_HIGH 0xFFFFFFFFU
#define HP_SYS_REDCY_HIGH_M (HP_SYS_REDCY_HIGH_V << HP_SYS_REDCY_HIGH_S)
#define HP_SYS_REDCY_HIGH_V 0xFFFFFFFFU
#define HP_SYS_REDCY_HIGH_S 0
/** HP_SYS_DEBUG_REG register
* HP-SYSTEM debug register
*/
#define HP_SYS_DEBUG_REG (DR_REG_HP_SYS_BASE + 0x3f4)
/** HP_SYS_FPGA_DEBUG : R/W; bitpos: [0]; default: 1;
* Reserved
*/
#define HP_SYS_FPGA_DEBUG (BIT(0))
#define HP_SYS_FPGA_DEBUG_M (HP_SYS_FPGA_DEBUG_V << HP_SYS_FPGA_DEBUG_S)
#define HP_SYS_FPGA_DEBUG_V 0x00000001U
#define HP_SYS_FPGA_DEBUG_S 0
/** HP_SYS_CLOCK_GATE_REG register
* HP-SYSTEM clock gating configure register
*/
#define HP_SYS_CLOCK_GATE_REG (DR_REG_HP_SYS_BASE + 0x3f8)
/** HP_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
*/
#define HP_SYS_CLK_EN (BIT(0))
#define HP_SYS_CLK_EN_M (HP_SYS_CLK_EN_V << HP_SYS_CLK_EN_S)
#define HP_SYS_CLK_EN_V 0x00000001U
#define HP_SYS_CLK_EN_S 0
/** HP_SYS_DATE_REG register
* Date register.
*/
#define HP_SYS_DATE_REG (DR_REG_HP_SYS_BASE + 0x3fc)
/** HP_SYS_DATE : R/W; bitpos: [27:0]; default: 36720768;
* HP-SYSTEM date information/ HP-SYSTEM version information.
*/
#define HP_SYS_DATE 0x0FFFFFFFU
#define HP_SYS_DATE_M (HP_SYS_DATE_V << HP_SYS_DATE_S)
#define HP_SYS_DATE_V 0x0FFFFFFFU
#define HP_SYS_DATE_S 0
#ifdef __cplusplus
}
#endif

760
components/soc/esp32c5/beta3/include/soc/hp_system_struct.h
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@ -1,760 +0,0 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of external_device_encrypt_decrypt_control register
* EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
*/
typedef union {
struct {
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
*/
uint32_t enable_spi_manual_encrypt:1;
/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t enable_download_db_encrypt:1;
/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
*/
uint32_t enable_download_g0cb_decrypt:1;
/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
*/
uint32_t enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_sys_external_device_encrypt_decrypt_control_reg_t;
/** Type of sram_usage_conf register
* HP memory usage configuration register
*/
typedef union {
struct {
/** cache_usage : HRO; bitpos: [0]; default: 0;
* reserved
*/
uint32_t cache_usage:1;
uint32_t reserved_1:7;
/** sram_usage : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
uint32_t sram_usage:4;
uint32_t reserved_12:4;
/** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
*/
uint32_t mac_dump_alloc:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hp_sys_sram_usage_conf_reg_t;
/** Type of sec_dpa_conf register
* HP anti-DPA security configuration register
*/
typedef union {
struct {
/** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
*/
uint32_t sec_dpa_level:2;
/** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
* This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
* (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
*/
uint32_t sec_dpa_cfg_sel:1;
uint32_t reserved_3:29;
};
uint32_t val;
} hp_sys_sec_dpa_conf_reg_t;
/** Type of sdio_ctrl register
* SDIO Control configuration register
*/
typedef union {
struct {
/** dis_sdio_prob : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
uint32_t dis_sdio_prob:1;
/** sdio_win_access_en : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
uint32_t sdio_win_access_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_sys_sdio_ctrl_reg_t;
/** Type of rom_table_lock register
* Rom-Table lock register
*/
typedef union {
struct {
/** rom_table_lock : R/W; bitpos: [0]; default: 0;
* XXXX
*/
uint32_t rom_table_lock:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_sys_rom_table_lock_reg_t;
/** Type of rom_table register
* Rom-Table register
*/
typedef union {
struct {
/** rom_table : R/W; bitpos: [31:0]; default: 0;
* XXXX
*/
uint32_t rom_table:32;
};
uint32_t val;
} hp_sys_rom_table_reg_t;
/** Type of core_debug_runstall_conf register
* Core Debug runstall configure register
*/
typedef union {
struct {
/** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
* Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
*/
uint32_t core_debug_runstall_enable:1;
/** core_runstalled : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
* not stalled.
*/
uint32_t core_runstalled:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_sys_core_debug_runstall_conf_reg_t;
/** Type of mem_test_conf register
* MEM_TEST configuration register
*/
typedef union {
struct {
/** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
*/
uint32_t hp_mem_wpulse:3;
/** hp_mem_wa : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
*/
uint32_t hp_mem_wa:3;
/** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
*/
uint32_t hp_mem_ra:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_sys_mem_test_conf_reg_t;
/** Type of audio_codec_sdadc_cntl register
* reserved
*/
typedef union {
struct {
/** sdadc_pad_en_vncp : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t sdadc_pad_en_vncp:1;
/** sdadc_pad_fast_chg : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t sdadc_pad_fast_chg:1;
/** sdadc_pad_en_0v : R/W; bitpos: [2]; default: 0;
* reserved
*/
uint32_t sdadc_pad_en_0v:1;
/** sdadc_en_chopper : R/W; bitpos: [3]; default: 1;
* reserved
*/
uint32_t sdadc_en_chopper:1;
/** sdadc_en_dem : R/W; bitpos: [4]; default: 1;
* reserved
*/
uint32_t sdadc_en_dem:1;
/** sdadc_dreg_oa : R/W; bitpos: [7:5]; default: 3;
* reserved
*/
uint32_t sdadc_dreg_oa:3;
/** sdadc_dgain_input : R/W; bitpos: [9:8]; default: 3;
* reserved
*/
uint32_t sdadc_dgain_input:2;
/** sdadc_dcap : R/W; bitpos: [14:10]; default: 12;
* reserved
*/
uint32_t sdadc_dcap:5;
uint32_t reserved_15:17;
};
uint32_t val;
} hp_sys_audio_codec_sdadc_cntl_reg_t;
/** Type of audio_codec_dac_l_cntl register
* reserved
*/
typedef union {
struct {
/** enhance_l_audio_dac : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t enhance_l_audio_dac:1;
/** gain_l_audio_dac : R/W; bitpos: [5:1]; default: 19;
* reserved
*/
uint32_t gain_l_audio_dac:5;
/** mute_l_audio_dac : R/W; bitpos: [6]; default: 0;
* reserved
*/
uint32_t mute_l_audio_dac:1;
/** xpd_l_audio_dac : R/W; bitpos: [7]; default: 0;
* reserved
*/
uint32_t xpd_l_audio_dac:1;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_sys_audio_codec_dac_l_cntl_reg_t;
/** Type of audio_codec_dac_l_din register
* reserved
*/
typedef union {
struct {
/** dac_din_l : R/W; bitpos: [21:0]; default: 0;
* reserved
*/
uint32_t dac_din_l:22;
uint32_t reserved_22:10;
};
uint32_t val;
} hp_sys_audio_codec_dac_l_din_reg_t;
/** Type of audio_codec_dac_r_cntl register
* reserved
*/
typedef union {
struct {
/** enhance_r_audio_dac : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t enhance_r_audio_dac:1;
/** gain_r_audio_dac : R/W; bitpos: [5:1]; default: 19;
* reserved
*/
uint32_t gain_r_audio_dac:5;
/** mute_r_audio_dac : R/W; bitpos: [6]; default: 0;
* reserved
*/
uint32_t mute_r_audio_dac:1;
/** xpd_r_audio_dac : R/W; bitpos: [7]; default: 0;
* reserved
*/
uint32_t xpd_r_audio_dac:1;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_sys_audio_codec_dac_r_cntl_reg_t;
/** Type of audio_codec_dac_r_din register
* reserved
*/
typedef union {
struct {
/** dac_din_r : R/W; bitpos: [21:0]; default: 0;
* reserved
*/
uint32_t dac_din_r:22;
uint32_t reserved_22:10;
};
uint32_t val;
} hp_sys_audio_codec_dac_r_din_reg_t;
/** Type of audio_codec_pll_cntl register
* reserved
*/
typedef union {
struct {
/** cal_stop_plla : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t cal_stop_plla:1;
/** cal_end_plla : RO; bitpos: [1]; default: 0;
* reserved
*/
uint32_t cal_end_plla:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_sys_audio_codec_pll_cntl_reg_t;
/** Type of audio_codec_data_mode_cntl register
* reserved
*/
typedef union {
struct {
/** audio_adc_mode : R/W; bitpos: [1:0]; default: 0;
* reserved
*/
uint32_t audio_adc_mode:2;
/** audio_dac_dsm_mode_r : R/W; bitpos: [3:2]; default: 0;
* reserved
*/
uint32_t audio_dac_dsm_mode_r:2;
/** audio_dac_dsm_mode_l : R/W; bitpos: [5:4]; default: 0;
* reserved
*/
uint32_t audio_dac_dsm_mode_l:2;
uint32_t reserved_6:26;
};
uint32_t val;
} hp_sys_audio_codec_data_mode_cntl_reg_t;
/** Type of sprom_ctrl register
* reserved
*/
typedef union {
struct {
/** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
* reserved
*/
uint32_t sprom_mem_aux_ctrl:32;
};
uint32_t val;
} hp_sys_sprom_ctrl_reg_t;
/** Type of spram_ctrl register
* reserved
*/
typedef union {
struct {
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
uint32_t spram_mem_aux_ctrl:32;
};
uint32_t val;
} hp_sys_spram_ctrl_reg_t;
/** Type of sprf_ctrl register
* reserved
*/
typedef union {
struct {
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
uint32_t sprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_sys_sprf_ctrl_reg_t;
/** Type of sdprf_ctrl register
* reserved
*/
typedef union {
struct {
/** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t sdprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_sys_sdprf_ctrl_reg_t;
/** Type of audio_codex_ctrl0 register
* reserved
*/
typedef union {
struct {
/** dac_in_r1_ie : R/W; bitpos: [0]; default: 1;
* reserved
*/
uint32_t dac_in_r1_ie:1;
/** dac_in_r1_oe : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t dac_in_r1_oe:1;
/** dac_in_r0_ie : R/W; bitpos: [2]; default: 1;
* reserved
*/
uint32_t dac_in_r0_ie:1;
/** dac_in_r0_oe : R/W; bitpos: [3]; default: 0;
* reserved
*/
uint32_t dac_in_r0_oe:1;
/** adc_data_4_ie : R/W; bitpos: [4]; default: 0;
* reserved
*/
uint32_t adc_data_4_ie:1;
/** adc_data_4_oe : R/W; bitpos: [5]; default: 1;
* reserved
*/
uint32_t adc_data_4_oe:1;
/** adc_data_3_ie : R/W; bitpos: [6]; default: 0;
* reserved
*/
uint32_t adc_data_3_ie:1;
/** adc_data_3_oe : R/W; bitpos: [7]; default: 1;
* reserved
*/
uint32_t adc_data_3_oe:1;
/** adc_data_2_ie : R/W; bitpos: [8]; default: 0;
* reserved
*/
uint32_t adc_data_2_ie:1;
/** adc_data_2_oe : R/W; bitpos: [9]; default: 1;
* reserved
*/
uint32_t adc_data_2_oe:1;
/** adc_data_1_ie : R/W; bitpos: [10]; default: 0;
* reserved
*/
uint32_t adc_data_1_ie:1;
/** adc_data_1_oe : R/W; bitpos: [11]; default: 1;
* reserved
*/
uint32_t adc_data_1_oe:1;
/** adc_data_0_ie : R/W; bitpos: [12]; default: 0;
* reserved
*/
uint32_t adc_data_0_ie:1;
/** adc_data_0_oe : R/W; bitpos: [13]; default: 1;
* reserved
*/
uint32_t adc_data_0_oe:1;
/** adc_ck_data_ie : R/W; bitpos: [14]; default: 0;
* reserved
*/
uint32_t adc_ck_data_ie:1;
/** adc_ck_data_oe : R/W; bitpos: [15]; default: 1;
* reserved
*/
uint32_t adc_ck_data_oe:1;
uint32_t reserved_16:16;
};
uint32_t val;
} hp_sys_audio_codex_ctrl0_reg_t;
/** Type of clock_gate register
* HP-SYSTEM clock gating configure register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_sys_clock_gate_reg_t;
/** Group: Timeout Register */
/** Type of cpu_peri_timeout_conf register
* CPU_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t cpu_peri_timeout_thres:16;
/** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t cpu_peri_timeout_int_clear:1;
/** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing cpu peripheral
* registers
*/
uint32_t cpu_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_sys_cpu_peri_timeout_conf_reg_t;
/** Type of cpu_peri_timeout_addr register
* CPU_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t cpu_peri_timeout_addr:32;
};
uint32_t val;
} hp_sys_cpu_peri_timeout_addr_reg_t;
/** Type of cpu_peri_timeout_uid register
* CPU_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t cpu_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_sys_cpu_peri_timeout_uid_reg_t;
/** Type of hp_peri_timeout_conf register
* HP_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t hp_peri_timeout_thres:16;
/** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t hp_peri_timeout_int_clear:1;
/** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
*/
uint32_t hp_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_sys_hp_peri_timeout_conf_reg_t;
/** Type of hp_peri_timeout_addr register
* HP_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t hp_peri_timeout_addr:32;
};
uint32_t val;
} hp_sys_hp_peri_timeout_addr_reg_t;
/** Type of hp_peri_timeout_uid register
* HP_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t hp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_sys_hp_peri_timeout_uid_reg_t;
/** Type of modem_peri_timeout_conf register
* MODEM_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t modem_peri_timeout_thres:16;
/** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t modem_peri_timeout_int_clear:1;
/** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
uint32_t modem_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_sys_modem_peri_timeout_conf_reg_t;
/** Type of modem_peri_timeout_addr register
* MODEM_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t modem_peri_timeout_addr:32;
};
uint32_t val;
} hp_sys_modem_peri_timeout_addr_reg_t;
/** Type of modem_peri_timeout_uid register
* MODEM_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t modem_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_sys_modem_peri_timeout_uid_reg_t;
/** Group: Redcy ECO Registers */
/** Type of rnd_eco register
* redcy eco register.
*/
typedef union {
struct {
/** redcy_ena : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_ena:1;
/** redcy_result : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_sys_rnd_eco_reg_t;
/** Type of rnd_eco_low register
* redcy eco low register.
*/
typedef union {
struct {
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_low:32;
};
uint32_t val;
} hp_sys_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* redcy eco high register.
*/
typedef union {
struct {
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
uint32_t redcy_high:32;
};
uint32_t val;
} hp_sys_rnd_eco_high_reg_t;
/** Group: Debug Register */
/** Type of debug register
* HP-SYSTEM debug register
*/
typedef union {
struct {
/** fpga_debug : R/W; bitpos: [0]; default: 1;
* Reserved
*/
uint32_t fpga_debug:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_sys_debug_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720768;
* HP-SYSTEM date information/ HP-SYSTEM version information.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_sys_date_reg_t;
typedef struct {
volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf;
volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf;
volatile hp_sys_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
volatile hp_sys_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
volatile hp_sys_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
volatile hp_sys_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
volatile hp_sys_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
volatile hp_sys_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
volatile hp_sys_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
volatile hp_sys_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
volatile hp_sys_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
volatile hp_sys_sdio_ctrl_reg_t sdio_ctrl;
uint32_t reserved_034;
volatile hp_sys_rom_table_lock_reg_t rom_table_lock;
volatile hp_sys_rom_table_reg_t rom_table;
volatile hp_sys_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
volatile hp_sys_mem_test_conf_reg_t mem_test_conf;
uint32_t reserved_048[2];
volatile hp_sys_audio_codec_sdadc_cntl_reg_t audio_codec_sdadc_cntl;
volatile hp_sys_audio_codec_dac_l_cntl_reg_t audio_codec_dac_l_cntl;
volatile hp_sys_audio_codec_dac_l_din_reg_t audio_codec_dac_l_din;
volatile hp_sys_audio_codec_dac_r_cntl_reg_t audio_codec_dac_r_cntl;
volatile hp_sys_audio_codec_dac_r_din_reg_t audio_codec_dac_r_din;
volatile hp_sys_audio_codec_pll_cntl_reg_t audio_codec_pll_cntl;
volatile hp_sys_audio_codec_data_mode_cntl_reg_t audio_codec_data_mode_cntl;
uint32_t reserved_06c;
volatile hp_sys_sprom_ctrl_reg_t sprom_ctrl;
volatile hp_sys_spram_ctrl_reg_t spram_ctrl;
volatile hp_sys_sprf_ctrl_reg_t sprf_ctrl;
volatile hp_sys_sdprf_ctrl_reg_t sdprf_ctrl;
volatile hp_sys_audio_codex_ctrl0_reg_t audio_codex_ctrl0;
uint32_t reserved_084[215];
volatile hp_sys_rnd_eco_reg_t rnd_eco;
volatile hp_sys_rnd_eco_low_reg_t rnd_eco_low;
volatile hp_sys_rnd_eco_high_reg_t rnd_eco_high;
uint32_t reserved_3ec[2];
volatile hp_sys_debug_reg_t debug;
volatile hp_sys_clock_gate_reg_t clock_gate;
volatile hp_sys_date_reg_t date;
} hp_sys_dev_t;
extern hp_sys_dev_t HP_SYSTEM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_sys_dev_t) == 0x400, "Invalid size of hp_sys_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/huk_reg.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HUK_CLK_REG register
* HUK Generator clock gate control register
*/
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define HUK_CLK_EN (BIT(0))
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
#define HUK_CLK_EN_V 0x00000001U
#define HUK_CLK_EN_S 0
/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define HUK_MEM_CG_FORCE_ON (BIT(1))
#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
#define HUK_MEM_CG_FORCE_ON_V 0x00000001U
#define HUK_MEM_CG_FORCE_ON_S 1
/** HUK_INT_RAW_REG register
* HUK Generator interrupt raw register, valid in level.
*/
#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_RAW (BIT(0))
#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
#define HUK_PREP_DONE_INT_RAW_V 0x00000001U
#define HUK_PREP_DONE_INT_RAW_S 0
/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_RAW (BIT(1))
#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
#define HUK_PROC_DONE_INT_RAW_V 0x00000001U
#define HUK_PROC_DONE_INT_RAW_S 1
/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_RAW (BIT(2))
#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
#define HUK_POST_DONE_INT_RAW_V 0x00000001U
#define HUK_POST_DONE_INT_RAW_S 2
/** HUK_INT_ST_REG register
* HUK Generator interrupt status register.
*/
#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ST (BIT(0))
#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
#define HUK_PREP_DONE_INT_ST_V 0x00000001U
#define HUK_PREP_DONE_INT_ST_S 0
/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ST (BIT(1))
#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
#define HUK_PROC_DONE_INT_ST_V 0x00000001U
#define HUK_PROC_DONE_INT_ST_S 1
/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ST (BIT(2))
#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
#define HUK_POST_DONE_INT_ST_V 0x00000001U
#define HUK_POST_DONE_INT_ST_S 2
/** HUK_INT_ENA_REG register
* HUK Generator interrupt enable register.
*/
#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ENA (BIT(0))
#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
#define HUK_PREP_DONE_INT_ENA_V 0x00000001U
#define HUK_PREP_DONE_INT_ENA_S 0
/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ENA (BIT(1))
#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
#define HUK_PROC_DONE_INT_ENA_V 0x00000001U
#define HUK_PROC_DONE_INT_ENA_S 1
/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ENA (BIT(2))
#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
#define HUK_POST_DONE_INT_ENA_V 0x00000001U
#define HUK_POST_DONE_INT_ENA_S 2
/** HUK_INT_CLR_REG register
* HUK Generator interrupt clear register.
*/
#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_CLR (BIT(0))
#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
#define HUK_PREP_DONE_INT_CLR_V 0x00000001U
#define HUK_PREP_DONE_INT_CLR_S 0
/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_CLR (BIT(1))
#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
#define HUK_PROC_DONE_INT_CLR_V 0x00000001U
#define HUK_PROC_DONE_INT_CLR_S 1
/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_CLR (BIT(2))
#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
#define HUK_POST_DONE_INT_CLR_V 0x00000001U
#define HUK_POST_DONE_INT_CLR_S 2
/** HUK_CONF_REG register
* HUK Generator configuration register
*/
#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
/** HUK_MODE : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
#define HUK_MODE (BIT(0))
#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S)
#define HUK_MODE_V 0x00000001U
#define HUK_MODE_S 0
/** HUK_START_REG register
* HUK Generator control register
*/
#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
/** HUK_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
#define HUK_START (BIT(0))
#define HUK_START_M (HUK_START_V << HUK_START_S)
#define HUK_START_V 0x00000001U
#define HUK_START_S 0
/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
#define HUK_CONTINUE (BIT(1))
#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S)
#define HUK_CONTINUE_V 0x00000001U
#define HUK_CONTINUE_S 1
/** HUK_STATE_REG register
* HUK Generator state register
*/
#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define HUK_STATE 0x00000003U
#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S)
#define HUK_STATE_V 0x00000003U
#define HUK_STATE_S 0
/** HUK_STATUS_REG register
* HUK Generator HUK status register
*/
#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
#define HUK_STATUS 0x00000003U
#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S)
#define HUK_STATUS_V 0x00000003U
#define HUK_STATUS_S 0
/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
#define HUK_RISK_LEVEL 0x00000007U
#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
#define HUK_RISK_LEVEL_V 0x00000007U
#define HUK_RISK_LEVEL_S 2
/** HUK_DATE_REG register
* Version control register
*/
#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704;
* HUK Generator version control register.
*/
#define HUK_DATE 0x0FFFFFFFU
#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S)
#define HUK_DATE_V 0x0FFFFFFFU
#define HUK_DATE_S 0
/** HUK_INFO_MEM register
* The memory that stores HUK info.
*/
#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
#define HUK_INFO_MEM_SIZE_BYTES 384
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* HUK Generator clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* HUK Generator interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_raw_reg_t;
/** Type of int_st register
* HUK Generator interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_st_reg_t;
/** Type of int_ena register
* HUK Generator interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_ena_reg_t;
/** Type of int_clr register
* HUK Generator interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_clr_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* HUK Generator configuration register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
uint32_t mode:1;
uint32_t reserved_1:31;
};
uint32_t val;
} huk_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* HUK Generator control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
uint32_t start:1;
/** conti : WT; bitpos: [1]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_start_reg_t;
/** Group: State registers */
/** Type of state register
* HUK Generator state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_state_reg_t;
/** Group: Result registers */
/** Type of status register
* HUK Generator HUK status register
*/
typedef union {
struct {
/** status : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
uint32_t status:2;
/** risk_level : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
uint32_t risk_level:3;
uint32_t reserved_5:27;
};
uint32_t val;
} huk_status_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
* HUK Generator version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} huk_date_reg_t;
typedef struct huk_dev_t {
uint32_t reserved_000;
volatile huk_clk_reg_t clk;
volatile huk_int_raw_reg_t int_raw;
volatile huk_int_st_reg_t int_st;
volatile huk_int_ena_reg_t int_ena;
volatile huk_int_clr_reg_t int_clr;
uint32_t reserved_018[2];
volatile huk_conf_reg_t conf;
volatile huk_start_reg_t start;
volatile huk_state_reg_t state;
uint32_t reserved_02c[2];
volatile huk_status_reg_t status;
uint32_t reserved_038[49];
volatile huk_date_reg_t date;
volatile uint32_t info[96];
} huk_dev_t;
extern huk_dev_t HUK;
#ifndef __cplusplus
_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// TODO: ZB-93, rewrite this file using regdesc tools when IEEE802154.csv is ready.
#define IEEE802154_REG_BASE 0x600A3000
#define IEEE802154_COMMAND_REG (IEEE802154_REG_BASE + 0x0000)
#define IEEE802154_OPCODE 0x000000FF
#define IEEE802154_OPCODE_S 0
#define IEEE802154_CTRL_CFG_REG (IEEE802154_REG_BASE + 0x0004)
#define IEEE802154_MAC_INF3_ENABLE (BIT(31))
#define IEEE802154_MAC_INF3_ENABLE_S 31
#define IEEE802154_MAC_INF2_ENABLE (BIT(30))
#define IEEE802154_MAC_INF2_ENABLE_S 30
#define IEEE802154_MAC_INF1_ENABLE (BIT(29))
#define IEEE802154_MAC_INF1_ENABLE_S 29
#define IEEE802154_MAC_INF0_ENABLE (BIT(28))
#define IEEE802154_MAC_INF0_ENABLE_S 28
#define IEEE802154_RX_DONE_TRIGGER_IDLE (BIT(27))
#define IEEE802154_RX_DONE_TRIGGER_IDLE_S 27
#define IEEE802154_FORCE_RX_ENB (BIT(26))
#define IEEE802154_FORCE_RX_ENB_S 26
#define IEEE802154_NO_RSS_TRK_ENB (BIT(25))
#define IEEE802154_NO_RSS_TRK_ENB_S 25
#define IEEE802154_BIT_ORDER (BIT(24))
#define IEEE802154_BIT_ORDER_S 24
#define IEEE802154_COEX_ARB_DELAY 0x000000FF
#define IEEE802154_COEX_ARB_DELAY_S 16
#define IEEE802154_FILTER_ENHANCE (BIT(14))
#define IEEE802154_FILTER_ENHANCE_S 14
#define IEEE802154_AUTOPEND_ENHANCE (BIT(12))
#define IEEE802154_AUTOPEND_ENHANCE_S 12
#define IEEE802154_DIS_FRAME_VERSION_RSV_FILTER (BIT(11))
#define IEEE802154_DIS_FRAME_VERSION_RSV_FILTER_S 11
#define IEEE802154_PROMISCUOUS_MODE (BIT(7))
#define IEEE802154_PROMISCUOUS_MODE_S 7
#define IEEE802154_PAN_COORDINATOR (BIT(6))
#define IEEE802154_PAN_COORDINATOR_S 6
#define IEEE802154_DIS_IFS_CONTROL (BIT(5))
#define IEEE802154_DIS_IFS_CONTROL_S 5
#define IEEE802154_HW_AUTO_ACK_RX_EN (BIT(3))
#define IEEE802154_HW_AUTO_ACK_RX_EN_S 3
#define HW_ENHANCE_ACK_TX_EN (BIT(1))
#define HW_ENHANCE_ACK_TX_EN_S 1
#define IEEE802154_HW_AUTO_ACK_TX_EN (BIT(0))
#define IEEE802154_HW_AUTO_ACK_TX_EN_S 0
#define IEEE802154_INF0_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0008)
#define IEEE802154_MAC_INF0_SHORT_ADDR 0x0000FFFF
#define IEEE802154_MAC_INF0_SHORT_ADDR_S 0
#define IEEE802154_INF0_PAN_ID_REG (IEEE802154_REG_BASE + 0x000C)
#define IEEE802154_MAC_INF0_PAN_ID 0x0000FFFF
#define IEEE802154_MAC_INF0_PAN_ID_S 0
#define IEEE802154_INF0_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0010)
#define IEEE802154_MAC_INF0_EXTEND_ADDR0 0xFFFFFFFF
#define IEEE802154_MAC_INF0_EXTEND_ADDR0_S 0
#define IEEE802154_INF0_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0014)
#define IEEE802154_MAC_INF0_EXTEND_ADDR1 0xFFFFFFFF
#define IEEE802154_MAC_INF0_EXTEND_ADDR1_S 0
#define IEEE802154_INF1_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0018)
#define IEEE802154_MAC_INF1_SHORT_ADDR 0x0000FFFF
#define IEEE802154_MAC_INF1_SHORT_ADDR_S 0
#define IEEE802154_INF1_PAN_ID_REG (IEEE802154_REG_BASE + 0x001C)
#define IEEE802154_MAC_INF1_PAN_ID 0x0000FFFF
#define IEEE802154_MAC_INF1_PAN_ID_S 0
#define IEEE802154_INF1_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0020)
#define IEEE802154_MAC_INF1_EXTEND_ADDR0 0xFFFFFFFF
#define IEEE802154_MAC_INF1_EXTEND_ADDR0_S 0
#define IEEE802154_INF1_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0024)
#define IEEE802154_MAC_INF1_EXTEND_ADDR1 0xFFFFFFFF
#define IEEE802154_MAC_INF1_EXTEND_ADDR1_S 0
#define IEEE802154_INF2_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0028)
#define IEEE802154_MAC_INF2_SHORT_ADDR 0x0000FFFF
#define IEEE802154_MAC_INF2_SHORT_ADDR_S 0
#define IEEE802154_INF2_PAN_ID_REG (IEEE802154_REG_BASE + 0x002C)
#define IEEE802154_MAC_INF2_PAN_ID 0x0000FFFF
#define IEEE802154_MAC_INF2_PAN_ID_S 0
#define IEEE802154_INF2_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0030)
#define IEEE802154_MAC_INF2_EXTEND_ADDR0 0xFFFFFFFF
#define IEEE802154_MAC_INF2_EXTEND_ADDR0_S 0
#define IEEE802154_INF2_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0034)
#define IEEE802154_MAC_INF2_EXTEND_ADDR1 0xFFFFFFFF
#define IEEE802154_MAC_INF2_EXTEND_ADDR1_S 0
#define IEEE802154_INF3_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0038)
#define IEEE802154_MAC_INF3_SHORT_ADDR 0x0000FFFF
#define IEEE802154_MAC_INF3_SHORT_ADDR_S 0
#define IEEE802154_INF3_PAN_ID_REG (IEEE802154_REG_BASE + 0x003C)
#define IEEE802154_MAC_INF3_PAN_ID 0x0000FFFF
#define IEEE802154_MAC_INF3_PAN_ID_S 0
#define IEEE802154_INF3_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0040)
#define IEEE802154_MAC_INF3_EXTEND_ADDR0 0xFFFFFFFF
#define IEEE802154_MAC_INF3_EXTEND_ADDR0_S 0
#define IEEE802154_INF3_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0044)
#define IEEE802154_MAC_INF3_EXTEND_ADDR1 0xFFFFFFFF
#define IEEE802154_MAC_INF3_EXTEND_ADDR1_S 0
#define IEEE802154_CHANNEL_REG (IEEE802154_REG_BASE + 0x0048)
#define IEEE802154_HOP 0x0000007F
#define IEEE802154_HOP_S 0
#define IEEE802154_TX_POWER_REG (IEEE802154_REG_BASE + 0x004C)
#define IEEE802154_TX_POWER 0x0000001F
#define IEEE802154_TX_POWER_S 0
#define IEEE802154_ED_SCAN_DURATION_REG (IEEE802154_REG_BASE + 0x0050)
#define IEEE802154_ED_SCAN_WAIT_DLY 0x0000000F
#define IEEE802154_ED_SCAN_WAIT_DLY_S 24
#define IEEE802154_ED_SCAN_DURATION 0x00FFFFFF
#define IEEE802154_ED_SCAN_DURATION_S 0
#define IEEE802154_ED_SCAN_CFG_REG (IEEE802154_REG_BASE + 0x0054)
#define IEEE802154_CCA_BUSY (BIT(24))
#define IEEE802154_CCA_BUSY_S 24
#define IEEE802154_ED_RSS 0x000000FF
#define IEEE802154_ED_RSS_S 16
#define IEEE802154_CCA_MODE 0x00000003
#define IEEE802154_CCA_MODE_S 14
#define IEEE802154_DIS_ED_POWER_SEL (BIT(13))
#define IEEE802154_DIS_ED_POWER_SEL_S 13
#define IEEE802154_ED_SAMPLE_MODE 0x00000003
#define IEEE802154_ED_SAMPLE_MODE_S 11
#define IEEE802154_CCA_ED_THRESHOLD 0x000000FF
#define IEEE802154_CCA_ED_THRESHOLD_S 0
#define IEEE802154_IFS_REG (IEEE802154_REG_BASE + 0x0058)
#define IEEE802154_LIFS 0x000003FF
#define IEEE802154_LIFS_S 16
#define IEEE802154_SIFS 0x000000FF
#define IEEE802154_SIFS_S 0
#define IEEE802154_ACK_TIMEOUT_REG (IEEE802154_REG_BASE + 0x005C)
#define IEEE802154_ACK_TIMEOUT 0x0000FFFF
#define IEEE802154_ACK_TIMEOUT_S 0
#define IEEE802154_EVENT_EN_REG (IEEE802154_REG_BASE + 0x0060)
#define IEEE802154_EVENT_EN 0x00001FFF
#define IEEE802154_EVENT_EN_S 0
#define IEEE802154_EVENT_STATUS_REG (IEEE802154_REG_BASE + 0x0064)
#define IEEE802154_EVENT_STATUS 0x00001FFF
#define IEEE802154_EVENT_STATUS_S 0
#define IEEE802154_RX_ABORT_INTR_CTRL_REG (IEEE802154_REG_BASE + 0x0068)
#define IEEE802154_RX_ABORT_INTR_CTRL 0x7FFFFFFF
#define IEEE802154_RX_ABORT_INTR_CTRL_S 0
#define IEEE802154_ACK_FRAME_PENDING_EN_REG (IEEE802154_REG_BASE + 0x006c)
#define IEEE802154_ACK_TX_ACK_TIMEOUT 0x0000FFFF
#define IEEE802154_ACK_TX_ACK_TIMEOUT_S 16
#define IEEE802154_ACK_FRAME_PENDING_EN (BIT(0))
#define IEEE802154_ACK_FRAME_PENDING_EN_S 0
#define IEEE802154_COEX_PTI_REG (IEEE802154_REG_BASE + 0x0070)
#define IEEE802154_CLOSE_RF_SEL (BIT(8))
#define IEEE802154_CLOSE_RF_SEL_S 8
#define IEEE802154_COEX_ACK_PTI 0x0000000F
#define IEEE802154_COEX_ACK_PTI_S 4
#define IEEE802154_COEX_PTI 0x0000000F
#define IEEE802154_COEX_PTI_S 0
#define IEEE802154_TX_ABORT_INTERRUPT_CONTROL_REG (IEEE802154_REG_BASE + 0x0078)
#define IEEE802154_TX_ABORT_INTERRUPT_CONTROL 0x7FFFFFFF
#define IEEE802154_TX_ABORT_INTERRUPT_CONTROL_S 0
#define IEEE802154_ENHANCE_ACK_CFG_REG (IEEE802154_REG_BASE + 0x7C)
#define IEEE802154_TX_ENH_ACK_GENERATE_DONE_NOTIFY 0xFFFFFFFF
#define IEEE802154_TX_ENH_ACK_GENERATE_DONE_NOTIFY_S 0
#define IEEE802154_RX_STATUS_REG (IEEE802154_REG_BASE + 0x0080)
#define IEEE802154_SFD_MATCH (BIT(21))
#define IEEE802154_SFD_MATCH_S 21
#define IEEE802154_PREAMBLE_MATCH (BIT(20))
#define IEEE802154_PREAMBLE_MATCH_S 20
#define IEEE802154_RX_STATE 0x00000007
#define IEEE802154_RX_STATE_S 16
#define IEEE802154_RX_ABORT_STATUS 0x0000001F
#define IEEE802154_RX_ABORT_STATUS_S 4
#define IEEE802154_FILTER_FAIL_STATUS 0x0000000F
#define IEEE802154_FILTER_FAIL_STATUS_S 0
#define IEEE802154_TX_STATUS_REG (IEEE802154_REG_BASE + 0x0084)
#define IEEE802154_TX_SEC_ERROR_CODE 0x0000000F
#define IEEE802154_TX_SEC_ERROR_CODE_S 16
#define IEEE802154_TX_ABORT_STATUS 0x0000001F
#define IEEE802154_TX_ABORT_STATUS_S 4
#define IEEE802154_TX_STATE 0x0000000F
#define IEEE802154_TX_STATE_S 0
#define IEEE802154_TXRX_STATUS_REG (IEEE802154_REG_BASE + 0x0088)
#define IEEE802154_RF_CTRL_STATE 0x0000000F
#define IEEE802154_RF_CTRL_STATE_S 16
#define IEEE802154_ED_TRIGGER_TX_PROC (BIT(11))
#define IEEE802154_ED_TRIGGER_TX_PROC_S 11
#define IEEE802154_ED_PROC (BIT(10))
#define IEEE802154_ED_PROC_S 10
#define IEEE802154_RX_PROC (BIT(9))
#define IEEE802154_RX_PROC_S 9
#define IEEE802154_TX_PROC (BIT(8))
#define IEEE802154_TX_PROC_S 8
#define IEEE802154_TXRX_STATE 0x0000000F
#define IEEE802154_TXRX_STATE_S 0
#define IEEE802154_TX_CCM_SCHEDULE_STATUS_REG (IEEE802154_REG_BASE + 0x008c)
#define IEEE802154_TX_CCM_SCHEDULE_STATUS 0x7FFFFFFF
#define IEEE802154_TX_CCM_SCHEDULE_STATUS_S 0
#define IEEE802154_RX_LENGTH_REG (IEEE802154_REG_BASE + 0x00a4)
#define IEEE802154_RX_LENGTH 0x0000007F
#define IEEE802154_RX_LENGTH_S 0
#define IEEE802154_TIME0_THRESHOLD_REG (IEEE802154_REG_BASE + 0x00a8)
#define IEEE802154_TIMER0_THRESHOLD 0xFFFFFFFF
#define IEEE802154_TIMER0_THRESHOLD_S 0
#define IEEE802154_TIME0_VALUE_REG (IEEE802154_REG_BASE + 0x00ac)
#define IEEE802154_TIMER0_VALUE 0xFFFFFFFF
#define IEEE802154_TIMER0_VALUE_S 0
#define IEEE802154_TIME1_THRESHOLD_REG (IEEE802154_REG_BASE + 0x00b0)
#define IEEE802154_TIMER1_THRESHOLD 0xFFFFFFFF
#define IEEE802154_TIMER1_THRESHOLD_S 0
#define IEEE802154_TIME1_VALUE_REG (IEEE802154_REG_BASE + 0x00b4)
#define IEEE802154_TIMER1_VALUE 0xFFFFFFFF
#define IEEE802154_TIMER1_VALUE_S 0
#define IEEE802154_CLK_COUNTER_MATCH_VAL_REG (IEEE802154_REG_BASE + 0x00b8)
#define IEEE802154_CLK_COUNT_MATCH_VAL 0x0000FFFF
#define IEEE802154_CLK_COUNT_MATCH_VAL_S 0
#define IEEE802154_CLK_COUNTER_REG (IEEE802154_REG_BASE + 0x00bc)
#define IEEE802154_CLK_625US_CNT 0x0000FFFF
#define IEEE802154_CLK_625US_CNT_S 0
#define IEEE802154_IFS_COUNTER_REG (IEEE802154_REG_BASE + 0x00c0)
#define IEEE802154_IFS_COUNTER_EN (BIT(16))
#define IEEE802154_IFS_COUNTER_EN_S 16
#define IEEE802154_IFS_COUNTER 0x000003FF
#define IEEE802154_IFS_COUNTER_S 0
#define IEEE802154_SFD_WAIT_SYMBOL_REG (IEEE802154_REG_BASE + 0x00c4)
#define IEEE802154_SFD_WAIT_SYMBOL_NUM 0x0000000F
#define IEEE802154_SFD_WAIT_SYMBOL_NUM_S 0
#define IEEE802154_TXRX_PATH_DELAY_REG (IEEE802154_REG_BASE + 0x00c8)
#define IEEE802154_RX_PATH_DELAY 0x0000003F
#define IEEE802154_RX_PATH_DELAY_S 16
#define IEEE802154_TX_PATH_DELAY 0x0000003F
#define IEEE802154_TX_PATH_DELAY_S 0
#define IEEE802154_BB_CLK_REG (IEEE802154_REG_BASE + 0x00cc)
#define IEEE802154_BB_CLK_FREQ_MINUS_1 0x0000001F
#define IEEE802154_BB_CLK_FREQ_MINUS_1_S 0
#define IEEE802154_TXDMA_ADDR_REG (IEEE802154_REG_BASE + 0x00D0)
#define IEEE802154_TXDMA_ADDR 0xFFFFFFFF
#define IEEE802154_TXDMA_ADDR_S 0
#define IEEE802154_TXDMA_CTRL_STATE_REG (IEEE802154_REG_BASE + 0x00D4)
#define IEEE802154_TXDMA_FETCH_BYTE_CNT 0x0000007F
#define IEEE802154_TXDMA_FETCH_BYTE_CNT_S 24
#define IEEE802154_TXDMA_STATE 0x0000001F
#define IEEE802154_TXDMA_STATE_S 16
#define IEEE802154_TXDMA_FILL_ENTRY 0x00000007
#define IEEE802154_TXDMA_FILL_ENTRY_S 4
#define IEEE802154_TXDMA_WATER_LEVEL 0x00000007
#define IEEE802154_TXDMA_WATER_LEVEL_S 0
#define IEEE802154_TXDMA_ERR_REG (IEEE802154_REG_BASE + 0x00D8)
#define IEEE802154_TXDMA_ERR 0x0000000F
#define IEEE802154_TXDMA_ERR_S 0
#define IEEE802154_RXDMA_ADDR_REG (IEEE802154_REG_BASE + 0x00E0)
#define IEEE802154_RXDMA_ADDR 0xFFFFFFFF
#define IEEE802154_RXDMA_ADDR_S 0
#define IEEE802154_RXDMA_CTRL_STATE_REG (IEEE802154_REG_BASE + 0x00E4)
#define IEEE802154_RXDMA_APPEND_FREQ_OFFSET (BIT(25))
#define IEEE802154_RXDMA_APPEND_FREQ_OFFSET_S 25
#define IEEE802154_RXDMA_APPEND_LQI_OFFSET (BIT(24))
#define IEEE802154_RXDMA_APPEND_LQI_OFFSET_S 24
#define IEEE802154_RXDMA_STATE 0x0000001F
#define IEEE802154_RXDMA_STATE_S 16
#define IEEE802154_RXDMA_WATER_LEVEL 0x00000007
#define IEEE802154_RXDMA_WATER_LEVEL_S 0
#define IEEE802154_RXDMA_ERR_REG (IEEE802154_REG_BASE + 0x00E8)
#define IEEE802154_RXDMA_ERR 0x0000000F
#define IEEE802154_RXDMA_ERR_S 0
#define IEEE802154_DMA_GCK_CFG_REG (IEEE802154_REG_BASE + 0x00F0)
#define IEEE802154_DMA_GCK_CFG (BIT(0))
#define IEEE802154_DMA_GCK_CFG_S 0
#define IEEE802154_DMA_DUMMY_REG (IEEE802154_REG_BASE + 0x00F4)
#define IEEE802154_DMA_DUMMY_DATA 0xFFFFFFFF
#define IEEE802154_DMA_DUMMY_DATA_S
#define IEEE802154_PAON_DELAY_REG (IEEE802154_REG_BASE + 0x0100)
#define IEEE802154_PAON_DELAY 0x000003FF
#define IEEE802154_PAON_DELAY_S 0
#define IEEE802154_TXON_DELAY_REG (IEEE802154_REG_BASE + 0x0104)
#define IEEE802154_TXON_DELAY 0x000003FF
#define IEEE802154_TXON_DELAY_S 0
#define IEEE802154_TXEN_STOP_DELAY_REG (IEEE802154_REG_BASE + 0x0108)
#define IEEE802154_TXEN_STOP_DLY 0x0000003F
#define IEEE802154_TXEN_STOP_DLY_S 0
#define IEEE802154_TXOFF_DELAY_REG (IEEE802154_REG_BASE + 0x010c)
#define IEEE802154_TXOFF_DELAY 0x0000003F
#define IEEE802154_TXOFF_DELAY_S 0
#define IEEE802154_RXON_DELAY_REG (IEEE802154_REG_BASE + 0x0110)
#define IEEE802154_RXON_DELAY 0x000007FF
#define IEEE802154_RXON_DELAY_S 0
#define IEEE802154_TXRX_SWITCH_DELAY_REG (IEEE802154_REG_BASE + 0x0114)
#define IEEE802154_TXRX_SWITCH_DELAY 0x000003FF
#define IEEE802154_TXRX_SWITCH_DELAY_S 0
#define IEEE802154_CONT_RX_DELAY_REG (IEEE802154_REG_BASE + 0x0118)
#define IEEE802154_CONT_RX_DELAY 0x0000003F
#define IEEE802154_CONT_RX_DELAY_S 0
#define IEEE802154_DCDC_CTRL_REG (IEEE802154_REG_BASE + 0x011c)
#define IEEE802154_TX_DCDC_UP (BIT(31))
#define IEEE802154_TX_DCDC_UP_S 31
#define IEEE802154_DCDC_CTRL_EN (BIT(16))
#define IEEE802154_DCDC_CTRL_EN_S 16
#define IEEE802154_DCDC_DOWN_DELAY 0x000000FF
#define IEEE802154_DCDC_DOWN_DELAY_S 8
#define IEEE802154_DCDC_PRE_UP_DELAY 0x000000FF
#define IEEE802154_DCDC_PRE_UP_DELAY_S 0
#define IEEE802154_DEBUG_CTRL_REG (IEEE802154_REG_BASE + 0x0120)
#define IEEE802154_DEBUG_TRIGGER_DUMP_EN (BIT(31))
#define IEEE802154_DEBUG_TRIGGER_DUMP_EN_S 31
#define IEEE802154_DEBUG_STATE_MATCH_DUMP_EN (BIT(30))
#define IEEE802154_DEBUG_STATE_MATCH_DUMP_EN_S 30
#define IEEE802154_DEBUG_TRIGGER_PULSE_SELECT 0x00000007
#define IEEE802154_DEBUG_TRIGGER_PULSE_SELECT_S 24
#define IEEE802154_DEBUG_TRIGGER_STATE_MATCH_VALUE 0x0000001F
#define IEEE802154_DEBUG_TRIGGER_STATE_MATCH_VALUE_S 16
#define IEEE802154_DEBUG_SER_DEBUG_SEL 0x0000000F
#define IEEE802154_DEBUG_SER_DEBUG_SEL_S 12
#define IEEE802154_DEBUG_TRIGGER_STATE_SELECT 0x0000000F
#define IEEE802154_DEBUG_TRIGGER_STATE_SELECT_S 8
#define IEEE802154_DEBUG_SIGNAL_SEL 0x00000007
#define IEEE802154_DEBUG_SIGNAL_SEL_S 0
#define IEEE802154_SEC_CTRL_REG (IEEE802154_REG_BASE + 0x0128)
#define IEEE802154_SEC_PAYLOAD_OFFSET 0x0000007F
#define IEEE802154_SEC_PAYLOAD_OFFSET_S 8
#define IEEE802154_SEC_EN (BIT(0))
#define IEEE802154_SEC_EN_S 0
#define IEEE802154_SEC_EXTEND_ADDRESS0_REG (IEEE802154_REG_BASE + 0x012c)
#define IEEE802154_SEC_EXTEND_ADDRESS0 0xFFFFFFFF
#define IEEE802154_SEC_EXTEND_ADDRESS0_S 0
#define IEEE802154_SEC_EXTEND_ADDRESS1_REG (IEEE802154_REG_BASE + 0x0130)
#define IEEE802154_SEC_EXTEND_ADDRESS1 0xFFFFFFFF
#define IEEE802154_SEC_EXTEND_ADDRESS1_S 0
#define IEEE802154_SEC_KEY0_REG (IEEE802154_REG_BASE + 0x0134)
#define IEEE802154_SEC_KEY0 0xFFFFFFFF
#define IEEE802154_SEC_KEY0_S 0
#define IEEE802154_SEC_KEY1_REG (IEEE802154_REG_BASE + 0x0138)
#define IEEE802154_SEC_KEY1 0xFFFFFFFF
#define IEEE802154_SEC_KEY1_S 0
#define IEEE802154_SEC_KEY2_REG (IEEE802154_REG_BASE + 0x013c)
#define IEEE802154_SEC_KEY2 0xFFFFFFFF
#define IEEE802154_SEC_KEY2_S 0
#define IEEE802154_SEC_KEY3_REG (IEEE802154_REG_BASE + 0x0140)
#define IEEE802154_SEC_KEY3 0xFFFFFFFF
#define IEEE802154_SEC_KEY3_S 0
#define IEEE802154_SFD_TIMEOUT_CNT_REG (IEEE802154_REG_BASE + 0x0144)
#define IEEE802154_SFD_TIMEOUT_CNT 0x0000FFFF
#define IEEE802154_SFD_TIMEOUT_CNT_S 0
#define IEEE802154_CRC_ERROR_CNT_REG (IEEE802154_REG_BASE + 0x0148)
#define IEEE802154_CRC_ERROR_CNT 0x0000FFFF
#define IEEE802154_CRC_ERROR_CNT_S 0
#define IEEE802154_ED_ABORT_CNT_REG (IEEE802154_REG_BASE + 0x014c)
#define IEEE802154_ED_ABORT_CNT 0x0000FFFF
#define IEEE802154_ED_ABORT_CNT_S 0
#define IEEE802154_CCA_FAIL_CNT_REG (IEEE802154_REG_BASE + 0x0150)
#define IEEE802154_CCA_FAIL_CNT 0x0000FFFF
#define IEEE802154_CCA_FAIL_CNT_S 0
#define IEEE802154_RX_FILTER_FAIL_CNT_REG (IEEE802154_REG_BASE + 0x0154)
#define IEEE802154_RX_FILTER_FAIL_CNT 0x0000FFFF
#define IEEE802154_RX_FILTER_FAIL_CNT_S 0
#define IEEE802154_NO_RSS_DETECT_CNT_REG (IEEE802154_REG_BASE + 0x0158)
#define IEEE802154_NO_RSS_DETECT_CNT 0x0000FFFF
#define IEEE802154_NO_RSS_DETECT_CNT_S 0
#define IEEE802154_RX_ABORT_COEX_CNT_REG (IEEE802154_REG_BASE + 0x015c)
#define IEEE802154_RX_ABORT_COEX_CNT 0x0000FFFF
#define IEEE802154_RX_ABORT_COEX_CNT_S 0
#define IEEE802154_RX_RESTART_CNT_REG (IEEE802154_REG_BASE + 0x0160)
#define IEEE802154_RX_RESTART_CNT 0x0000FFFF
#define IEEE802154_RX_RESTART_CNT_S 0
#define IEEE802154_TX_ACK_ABORT_COEX_CNT_REG (IEEE802154_REG_BASE + 0x0164)
#define IEEE802154_TX_ACK_ABORT_COEX_CNT 0x0000FFFF
#define IEEE802154_TX_ACK_ABORT_COEX_CNT_S 0
#define IEEE802154_ED_SCAN_COEX_CNT_REG (IEEE802154_REG_BASE + 0x0168)
#define IEEE802154_ED_SCAN_COEX_CNT 0x0000FFFF
#define IEEE802154_ED_SCAN_COEX_CNT_S 0
#define IEEE802154_RX_ACK_ABORT_COEX_CNT_REG (IEEE802154_REG_BASE + 0x016c)
#define IEEE802154_RX_ACK_ABORT_COEX_CNT 0x0000FFFF
#define IEEE802154_RX_ACK_ABORT_COEX_CNT_S 0
#define IEEE802154_RX_ACK_TIMEOUT_CNT_REG (IEEE802154_REG_BASE + 0x0170)
#define IEEE802154_RX_ACK_TIMEOUT_CNT 0x0000FFFF
#define IEEE802154_RX_ACK_TIMEOUT_CNT_S 0
#define IEEE802154_TX_BREAK_COEX_CNT_REG (IEEE802154_REG_BASE + 0x0174)
#define IEEE802154_TX_BREAK_COEX_CNT 0x0000FFFF
#define IEEE802154_TX_BREAK_COEX_CNT_S 0
#define IEEE802154_TX_SECURITY_ERROR_CNT_REG (IEEE802154_REG_BASE + 0x0178)
#define IEEE802154_TX_SECURITY_ERROR_CNT 0x0000FFFF
#define IEEE802154_TX_SECURITY_ERROR_CNT_S 0
#define IEEE802154_CCA_BUSY_CNT_REG (IEEE802154_REG_BASE + 0x017c)
#define IEEE802154_CCA_BUSY_CNT 0x0000FFFF
#define IEEE802154_CCA_BUSY_CNT_S 0
#define IEEE802154_ERROR_CNT_CLEAR_REG (IEEE802154_REG_BASE + 0x0180)
#define IEEE802154_SFD_TIMEOUT_CNT_CLEAR (BIT(14))
#define IEEE802154_SFD_TIMEOUT_CNT_CLEAR_S 14
#define IEEE802154_CRC_ERROR_CNT_CLEAR (BIT(13))
#define IEEE802154_CRC_ERROR_CNT_CLEAR_S 13
#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR (BIT(12))
#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR_S 12
#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR (BIT(11))
#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR_S 11
#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR (BIT(10))
#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR_S 10
#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR (BIT(9))
#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR_S 9
#define IEEE802154_RX_RESTART_CNT_CLEAR (BIT(8))
#define IEEE802154_RX_RESTART_CNT_CLEAR_S 8
#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR (BIT(7))
#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR_S 7
#define IEEE802154_TX_ACK_ABORT_COEX_CNT_CLEAR (BIT(6))
#define IEEE802154_TX_ACK_ABORT_COEX_CNT_CLEAR_S 6
#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR (BIT(5))
#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR_S 5
#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR (BIT(4))
#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR_S 4
#define IEEE802154_ED_ABORT_CNT_CLEAR (BIT(3))
#define IEEE802154_ED_ABORT_CNT_CLEAR_S 3
#define IEEE802154_CCA_FAIL_CNT_CLEAR (BIT(2))
#define IEEE802154_CCA_FAIL_CNT_CLEAR_S 2
#define IEEE802154_CCA_BUSY_CNT_CLEAR (BIT(1))
#define IEEE802154_CCA_BUSY_CNT_CLEAR_S 1
#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR (BIT(0))
#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR_S 0
#define DEBUG_SEL_CFG0_REG (IEEE802154_REG_BASE + 0x184)
#define DEBUG_FIELD3_SEL 0x0000001F
#define DEBUG_FIELD3_SEL_S 24
#define DEBUG_FIELD2_SEL 0x0000001F
#define DEBUG_FIELD2_SEL_S 16
#define DEBUG_FIELD1_SEL 0x0000001F
#define DEBUG_FIELD1_SEL_S 8
#define DEBUG_FIELD0_SEL 0x0000001F
#define DEBUG_FIELD0_SEL_S 0
#define DEBUG_SEL_CFG1_REG (IEEE802154_REG_BASE + 0x188)
#define DEBUG_FIELD7_SEL 0x0000001F
#define DEBUG_FIELD7_SEL_S 24
#define DEBUG_FIELD6_SEL 0x0000001F
#define DEBUG_FIELD6_SEL_S 16
#define DEBUG_FIELD5_SEL 0x0000001F
#define DEBUG_FIELD5_SEL_S 8
#define DEBUG_FIELD4_SEL 0x0000001F
#define DEBUG_FIELD4_SEL_S 0
#define IEEE802154_MAC_DATE_REG (IEEE802154_REG_BASE + 0x18c)
#define IEEE802154_MAC_DATE 0xFFFFFFFF
#define IEEE802154_MAC_DATE_S 0
#define IEEE802154_MAC_DATE_VERSION 0x220907
// For ETM feature.
#define ETM_REG_BASE 0x600A8800
#define ETM_CHEN_AD0_REG (ETM_REG_BASE + 0x0000)
#define ETM_CHENSET_AD0_REG (ETM_REG_BASE + 0x0004)
#define ETM_CHENCLR_AD0_REG (ETM_REG_BASE + 0x0008)
#define ETM_CH0_EVT_ID_REG (ETM_REG_BASE + 0x0018)
#define ETM_CH0_TASK_ID_REG (ETM_REG_BASE + 0x001C)
#define ETM_CH_OFFSET 0x08
#define ETM_EVENT_TIMER1_OVERFLOW 58
#define ETM_EVENT_TIMER0_OVERFLOW 59
#define ETM_TASK_ED_TRIG_TX 64
#define ETM_TASK_RX_START 65
#define ETM_TASK_TX_START 68
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/ieee802154_struct.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
// TODO: ZB-93, rewrite this file using regdesc tools when IEEE802154.csv is ready.
typedef volatile struct esp_ieee802154_s {
union {
struct {
uint32_t cmd: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} cmd; // 0x00
union {
struct {
uint32_t auto_ack_tx: 1;
uint32_t auto_enhack: 1;
uint32_t reserved2: 1;
uint32_t auto_ack_rx: 1;
uint32_t reserved4: 1;
uint32_t ifs_dis: 1;
uint32_t coordinator: 1;
uint32_t promiscuous: 1;
uint32_t reserved8: 3;
uint32_t version_filter_dis: 1;
uint32_t pending_enhance: 1;
uint32_t reserved13: 1;
uint32_t filter_enhance_dis: 1;
uint32_t reserved15: 1;
uint32_t coex_arb_delay: 8;
uint32_t bit_order: 1;
uint32_t no_rssi_trigger_break_en: 1;
uint32_t coex_force_rx: 1;
uint32_t rx_done_trig_idle: 1;
uint32_t multipan_mask: 4;
};
uint32_t val;
} conf; // 0x04
struct {
union {
struct {
uint32_t addr: 16;
uint32_t reserved16: 16;
};
uint32_t val;
} short_addr; // 0x08
union {
struct {
uint32_t id: 16;
uint32_t reserved16: 16;
};
uint32_t val;
} panid; // 0x0c
uint32_t ext_addr0; // 0x10
uint32_t ext_addr1; // 0x14
} multipan[4];
union {
struct {
uint32_t freq: 7;
uint32_t reserved7: 25;
};
uint32_t val;
} channel; //0x48
union {
struct {
uint32_t power: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} txpower; //0x4c
union {
struct {
uint32_t duration: 24;
uint32_t delay: 4;
uint32_t reserved28: 4;
};
uint32_t val;
} ed_duration; //0x50
union {
struct {
uint32_t cca_threshold: 8;
uint32_t reserved8: 3;
uint32_t ed_sample_rate: 2;
uint32_t ed_sample_mode: 1;
uint32_t cca_mode: 2;
uint32_t ed_rss: 8;
uint32_t cca_busy: 1;
uint32_t reserved25: 7;
};
uint32_t val;
} ed_cfg; //0x54
union {
struct {
uint32_t sifs: 8;
uint32_t reserved8: 8;
uint32_t lifs: 10;
uint32_t reserved26: 6;
};
uint32_t val;
} ifs_cfg; //0x58
union {
struct {
uint32_t timeout: 16;
uint32_t reserved16: 16;
};
uint32_t val;
} ack_timeout; //0x5c
union {
struct {
uint32_t events: 13;
uint32_t reserved13: 19;
};
uint32_t val;
} event_en; //0x60
union {
struct {
uint32_t events: 13;
uint32_t reserved13: 19;
};
uint32_t val;
} event_status; //0x64
union {
struct {
uint32_t rx_abort_en: 31;
uint32_t reserved31: 1;
};
uint32_t val;
} rx_abort_event_en; //0x68
union {
struct {
uint32_t pending: 1;
uint32_t reserved1: 15;
uint32_t pending_timeout: 16;
};
uint32_t val;
} pending_cfg; //0x6c
union {
struct {
uint32_t pti: 4;
uint32_t hw_ack_pti: 4;
uint32_t close_rf_sel: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} pti; //0x70
uint32_t reserved_74; //0x74
union {
struct {
uint32_t tx_abort_en: 31;
uint32_t reserved31: 1;
};
uint32_t val;
} tx_abort_event_en; //0x78
uint32_t enhack_generate_done_notify; //0x7c
union {
struct {
uint32_t filter_fail_reason: 4;
uint32_t rx_abort_reason: 5;
uint32_t reserved9: 7;
uint32_t rx_state: 3;
uint32_t reserved19: 1;
uint32_t preamble_match: 1;
uint32_t sfd_match: 1;
uint32_t reserved22: 10;
};
uint32_t val;
} rx_status; // 0x80
union {
struct {
uint32_t tx_state: 4;
uint32_t tx_abort_reason: 5;
uint32_t reserved9: 7;
uint32_t tx_security_error: 4;
uint32_t reserved20: 12;
};
uint32_t val;
} tx_status; //0x84
union {
struct {
uint32_t txrx_status: 4;
uint32_t reserved4: 4;
uint32_t tx_proc: 1;
uint32_t rx_proc: 1;
uint32_t ed_proc: 1;
uint32_t ed_trig_tx_proc: 1;
uint32_t reserved12: 4;
uint32_t rf_ctrl_state: 4;
uint32_t reserved20: 12;
};
uint32_t val;
} txrx_status; //0x88
uint32_t tx_sec_schedule_state; //0x8c
union {
struct {
uint32_t pkt_gck: 1;
uint32_t ctrl_gck: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} core_gck_cfg; //0x90
uint32_t reserved_94; //0x94
uint32_t reserved_98; //0x98
uint32_t reserved_9c; //0x9c
uint32_t reserved_a0; //0xa0
uint32_t rx_length; //0xa4
uint32_t timer0_threshold; //0xa8
uint32_t timer0_value; //0xac
uint32_t timer1_threshold; //0xb0
uint32_t timer1_value; //0xb4
uint32_t clk_counter_threshold; //0xb8
uint32_t clk_counter_value; //0xbc
union {
struct {
uint32_t ifs_counter: 10;
uint32_t reserved10: 6;
uint32_t ifs_counter_en: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} ifs_counter_cfg; //0xc0
union {
struct {
uint32_t sfd_wait_symbol_num: 4;
uint32_t reserved4: 28;
};
uint32_t val;
} sfd_wait; //0xc4
union {
struct {
uint32_t tx_path_delay: 6;
uint32_t reserved6: 10;
uint32_t rx_path_delay: 6;
uint32_t reserved624: 10;
};
uint32_t val;
} txrx_path_delay; //0xc8
uint32_t bb_clk; //0xcc
uint32_t dma_tx_addr; //0xd0
union {
struct {
uint32_t txdma_water_level: 3;
uint32_t reserved3: 1;
uint32_t txdma_fill_entry: 3;
uint32_t reserved7: 9;
uint32_t txdma_ctrl_state: 5;
uint32_t reserved21: 3;
uint32_t txdma_fetch_byte_cnt: 7;
uint32_t reserved31: 1;
};
uint32_t val;
} dma_tx_cfg; //0xd4
uint32_t dma_tx_err; //0xd8
uint32_t reserved_dc; //0xdc
uint32_t dma_rx_addr; //0xe0
union {
struct {
uint32_t rxdma_water_level: 3;
uint32_t reserved3: 13;
uint32_t rxdma_ctrl_state: 5;
uint32_t reserved21: 3;
uint32_t rxdma_append_lqi: 1;
uint32_t rxdma_append_freq_offset: 1;
uint32_t reserved26: 6;
};
uint32_t val;
} dma_rx_cfg; //0xe4
uint32_t dma_rx_err; //0xe8
uint32_t reserved_ec; //x0ec
uint32_t dma_gck; //0xf0
uint32_t dma_dummy_data; //0xf4
uint32_t reserved_f8; //0xf8
uint32_t reserved_fc; //0xfc
union {
struct {
uint32_t delay: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} pa_on_delay; //0x100
union {
struct {
uint32_t delay: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} tx_on_delay; //0x104
union {
struct {
uint32_t delay: 6;
uint32_t reserved6: 26;
};
uint32_t val;
} txen_stop_delay; //0x108
union {
struct {
uint32_t delay: 6;
uint32_t reserved6: 26;
};
uint32_t val;
} tx_off_delay; //0x10c
union {
struct {
uint32_t delay: 11;
uint32_t reserved11: 21;
};
uint32_t val;
} rx_on_delay; //0x110
union {
struct {
uint32_t delay: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} txrx_switch_delay; //0x114
uint32_t cont_rx_delay; //0x118
union {
struct {
uint32_t dcdc_pre_up_delay: 8;
uint32_t dcdc_down_delay: 8;
uint32_t dcdc_ctrl_en: 1;
uint32_t reserved17: 14;
uint32_t tx_dcdc_up: 1;
};
uint32_t val;
} dcdc_ctrl; //0x11c
union {
struct {
uint32_t debug_sel: 3;
uint32_t reserved3: 5;
uint32_t trig_st_sel: 4;
uint32_t ser_debug_sel: 4;
uint32_t trig_st_match_val: 5;
uint32_t reserved21: 3;
uint32_t trig_pulse_sel: 3;
uint32_t reserved27: 3;
uint32_t trig_st_match_dump_en: 1;
uint32_t trig_pulse_dump_en: 1;
};
uint32_t val;
} debug_ctrl; //0x120
uint32_t tx_dma_err_sts_reg; //0x124
union {
struct {
uint32_t tx_security_en: 1;
uint32_t reserved1: 7;
uint32_t security_offset: 7;
uint32_t reserved15: 17;
};
uint32_t val;
} security_ctrl; //0x128
uint32_t security_addr0; //0x12c
uint32_t security_addr1; //0x130
uint32_t security_key0; //0x134
uint32_t security_key1; //0x138
uint32_t security_key2; //0x13c
uint32_t security_key3; //0x140
uint32_t debug_sfd_timeout_cnt; //0x144
uint32_t debug_crc_error_cnt; //0x148
uint32_t debug_ed_abort_cnt; //0x14c
uint32_t debug_cca_fail_cnt; //0x150
uint32_t debug_rx_filter_fail_cnt; //0x154
uint32_t debug_no_rss_detect_cnt; //0x158
uint32_t debug_rx_abort_coex_cnt; //0x15c
uint32_t debug_rx_restart_cnt; //0x160
uint32_t debug_tx_ack_abort_coex_cnt; //0x164
uint32_t debug_ed_scan_break_coex_cnt; //0x168
uint32_t debug_rx_ack_abort_coex_cnt; //0x16c
uint32_t debug_rx_ack_timeout_cnt; //0x170
uint32_t debug_tx_break_coex_cnt; //0x174
uint32_t debug_tx_security_error_cnt; //0x178
uint32_t debug_cca_busy_cnt; //0x17c
union {
struct {
uint32_t debug_ed_scan_break_coex_cnt: 1;
uint32_t debug_cca_busy_cnt: 1;
uint32_t debug_cca_fail_cnt: 1;
uint32_t debug_ed_abort_cnt: 1;
uint32_t debug_tx_security_error_cnt: 1;
uint32_t debug_tx_break_coex_cnt: 1;
uint32_t debug_tx_ack_abort_coex_cnt: 1;
uint32_t debug_rx_ack_timeout_cnt: 1;
uint32_t debug_rx_restart_cnt: 1;
uint32_t debug_rx_ack_abort_coex_cnt: 1;
uint32_t debug_rx_abort_coex_cnt: 1;
uint32_t debug_no_rss_detect_cnt: 1;
uint32_t debug_rx_filter_fail_cnt: 1;
uint32_t debug_crc_error_cnt: 1;
uint32_t debug_sfd_timeout_cnt: 1;
uint32_t reserved15: 17;
};
uint32_t val;
} debug_cnt_clr; //0x180
union {
struct {
uint32_t debug_field0_sel: 8;
uint32_t debug_field1_sel: 8;
uint32_t debug_field2_sel: 8;
uint32_t debug_field3_sel: 8;
};
uint32_t val;
} debug_sel_cfg0; //0x184
union {
struct {
uint32_t debug_field4_sel: 8;
uint32_t debug_field5_sel: 8;
uint32_t debug_field6_sel: 8;
uint32_t debug_field7_sel: 8;
};
uint32_t val;
} debug_sel_cfg1; //0x188
uint32_t i154_version; //0x18c
} esp_ieee802154_t;
extern esp_ieee802154_t IEEE802154;
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/interrupt_matrix_reg.h
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components/soc/esp32c5/beta3/include/soc/interrupt_matrix_struct.h
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components/soc/esp32c5/beta3/include/soc/interrupts.h
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/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibration*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
ETS_LP_TIMER_INTR_SOURCE,
ETS_COEX_INTR_SOURCE,
ETS_BLE_TIMER_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
ETS_ZB_MAC_INTR_SOURCE,
ETS_PMU_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_LP_RTC_TIMER_INTR_SOURCE,
ETS_LP_UART_INTR_SOURCE,
ETS_LP_I2C_INTR_SOURCE,
ETS_LP_WDT_INTR_SOURCE,
ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
ETS_LP_APM_M0_INTR_SOURCE,
ETS_LP_APM_M1_INTR_SOURCE,
ETS_HUK_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_TRACE_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_GPIO_SD_INTR_SOURCE,
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
ETS_HP_APM_M0_INTR_SOURCE,
ETS_HP_APM_M1_INTR_SOURCE,
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_TWAI0_INTR_SOURCE, /**< interrupt of twai0, level*/
ETS_TWAI1_INTR_SOURCE, /**< interrupt of twai1, level*/
ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/
ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
ETS_PARL_IO_RX_INTR_SOURCE,
ETS_SLC0_INTR_SOURCE,
ETS_SLC1_INTR_SOURCE,
ETS_USB_OTG20_INTR_SOURCE,
ETS_USB_OTG20_MULTI_PROC_INTR_SOURCE,
ETS_USB_OTG20_MISC_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/
ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/
ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/
ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/
ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/
ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/
ETS_GPSPI2_INTR_SOURCE,
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/
ETS_ECDSA_INTR_SOURCE,
ETS_KM_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrupt_t;
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/intpri_reg.h
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@ -1,88 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_0_S 0
/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_1_S 0
/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_2_S 0
/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_3_S 0
/** INTPRI_DATE_REG register
* register description
*/
#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784;
* Need add description
*/
#define INTPRI_DATE 0x0FFFFFFFU
#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S)
#define INTPRI_DATE_V 0x0FFFFFFFU
#define INTPRI_DATE_S 0
/** INTPRI_CLOCK_GATE_REG register
* register description
*/
#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define INTPRI_CLK_EN (BIT(0))
#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
#define INTPRI_CLK_EN_V 0x00000001U
#define INTPRI_CLK_EN_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/intpri_struct.h
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@ -1,121 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Interrupt Registers */
/** Type of cpu_intr_from_cpu_0 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_0:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_0_reg_t;
/** Type of cpu_intr_from_cpu_1 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_1:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_1_reg_t;
/** Type of cpu_intr_from_cpu_2 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_2:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_2_reg_t;
/** Type of cpu_intr_from_cpu_3 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_3:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_3_reg_t;
/** Group: Version Registers */
/** Type of date register
* register description
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36712784;
* Need add description
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} intpri_date_reg_t;
/** Group: Configuration Registers */
/** Type of clock_gate register
* register description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_clock_gate_reg_t;
typedef struct intpri_dev_t {
uint32_t reserved_000[36];
volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
volatile intpri_date_reg_t date;
volatile intpri_clock_gate_reg_t clock_gate;
} intpri_dev_t;
extern intpri_dev_t INTPRI;
#ifndef __cplusplus
_Static_assert(sizeof(intpri_dev_t) == 0xa8, "Invalid size of intpri_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/io_mux_reg.h
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@ -1,344 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Used to enable sleep mode pin functions */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
#define FILTER_EN (BIT(15))
#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
#define FILTER_EN_V 1
#define FILTER_EN_S 15
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_MTMS
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTDI
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_MTCK
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_MTDO
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_GPIO6
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_U0TXD
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_U0RXD
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_SDIO_DATA1
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_SDIO_DATA0
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_SDIO_CLK
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_SDIO_CMD
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_SDIO_DATA3
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_SDIO_DATA2
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_SPICS0
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIQ
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPIWP
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_SPIHD
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_SPICLK
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_SPID
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_PAD_GPIO25
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_U_PAD_GPIO26
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define SPI_HD_GPIO_NUM 22
#define SPI_WP_GPIO_NUM 20
#define SPI_CS0_GPIO_NUM 18
#define SPI_CLK_GPIO_NUM 23
#define SPI_D_GPIO_NUM 24
#define SPI_Q_GPIO_NUM 19
#define SD_CLK_GPIO_NUM 14
#define SD_CMD_GPIO_NUM 15
#define SD_DATA0_GPIO_NUM 13
#define SD_DATA1_GPIO_NUM 12
#define SD_DATA2_GPIO_NUM 17
#define SD_DATA3_GPIO_NUM 16
#define USB_INT_PHY0_DM_GPIO_NUM 25
#define USB_INT_PHY0_DP_GPIO_NUM 26
#define EXT_OSC_SLOW_GPIO_NUM 0
#define MAX_RTC_GPIO_NUM 8
#define MAX_PAD_GPIO_NUM 26
#define MAX_GPIO_NUM 30
#define DIG_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define CLK_OUT3 0x1f
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 10
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0x1f
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 5
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0x1f
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x4)
#define FUNC_XTAL_32K_P_GPIO0 1
#define FUNC_XTAL_32K_P_GPIO0_0 0
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x8)
#define FUNC_XTAL_32K_N_GPIO1 1
#define FUNC_XTAL_32K_N_GPIO1_0 0
#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0xC)
#define FUNC_MTMS_FSPIQ 2
#define FUNC_MTMS_GPIO2 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0x10)
#define FUNC_MTDI_GPIO3 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x14)
#define FUNC_MTCK_FSPIHD 2
#define FUNC_MTCK_GPIO4 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x18)
#define FUNC_MTDO_FSPIWP 2
#define FUNC_MTDO_GPIO5 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_U_PAD_GPIO6 (REG_IO_MUX_BASE + 0x1C)
#define FUNC_GPIO6_FSPICLK 2
#define FUNC_GPIO6_GPIO6 1
#define FUNC_GPIO6_GPIO6_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x20)
#define FUNC_GPIO7_FSPID 2
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x24)
#define FUNC_GPIO8_DAC_DSM_IN_R2 3
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x28)
#define FUNC_GPIO9_DAC_DSM_IN_R3 3
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x2C)
#define FUNC_U0TXD_GPIO10 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x30)
#define FUNC_U0RXD_GPIO11 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_U_PAD_SDIO_DATA1 (REG_IO_MUX_BASE + 0x34)
#define FUNC_SDIO_DATA1_DAC_DSM_IN_L1 3
#define FUNC_SDIO_DATA1_FSPICS0 2
#define FUNC_SDIO_DATA1_GPIO12 1
#define FUNC_SDIO_DATA1_SDIO_DATA1 0
#define PERIPHS_IO_MUX_U_PAD_SDIO_DATA0 (REG_IO_MUX_BASE + 0x38)
#define FUNC_SDIO_DATA0_DAC_DSM_IN_L0 3
#define FUNC_SDIO_DATA0_FSPICS1 2
#define FUNC_SDIO_DATA0_GPIO13 1
#define FUNC_SDIO_DATA0_SDIO_DATA0 0
#define PERIPHS_IO_MUX_U_PAD_SDIO_CLK (REG_IO_MUX_BASE + 0x3C)
#define FUNC_SDIO_CLK_CKO_AUDIO_DAC 3
#define FUNC_SDIO_CLK_FSPICS2 2
#define FUNC_SDIO_CLK_GPIO14 1
#define FUNC_SDIO_CLK_SDIO_CLK 0
#define PERIPHS_IO_MUX_U_PAD_SDIO_CMD (REG_IO_MUX_BASE + 0x40)
#define FUNC_SDIO_CMD_CKO_PLLA 3
#define FUNC_SDIO_CMD_FSPICS3 2
#define FUNC_SDIO_CMD_GPIO15 1
#define FUNC_SDIO_CMD_SDIO_CMD 0
#define PERIPHS_IO_MUX_U_PAD_SDIO_DATA3 (REG_IO_MUX_BASE + 0x44)
#define FUNC_SDIO_DATA3_DAC_DSM_IN_L3 3
#define FUNC_SDIO_DATA3_FSPICS4 2
#define FUNC_SDIO_DATA3_GPIO16 1
#define FUNC_SDIO_DATA3_SDIO_DATA3 0
#define PERIPHS_IO_MUX_U_PAD_SDIO_DATA2 (REG_IO_MUX_BASE + 0x48)
#define FUNC_SDIO_DATA2_DAC_DSM_IN_L2 3
#define FUNC_SDIO_DATA2_FSPICS5 2
#define FUNC_SDIO_DATA2_GPIO17 1
#define FUNC_SDIO_DATA2_SDIO_DATA2 0
#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x4C)
#define FUNC_SPICS0_GPIO18 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x50)
#define FUNC_SPIQ_GPIO19 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x54)
#define FUNC_SPIWP_GPIO20 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x58)
#define FUNC_VDD_SPI_GPIO21 1
#define FUNC_VDD_SPI_GPIO21_0 0
#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x5C)
#define FUNC_SPIHD_GPIO22 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x60)
#define FUNC_SPICLK_GPIO23 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x64)
#define FUNC_SPID_GPIO24 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x68)
#define FUNC_GPIO25_GPIO25 1
#define FUNC_GPIO25_GPIO25_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x6C)
#define FUNC_GPIO26_GPIO26 1
#define FUNC_GPIO26_GPIO26_0 0
/** IO_MUX_PIN_CTRL_REG register
* Clock Output Configuration Register
*/
#define IO_MUX_PIN_CTRL_REG (DR_REG_IO_MUX_BASE + 0x0)
/** IO_MUX_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
* CLK_OUT_out1 can be found in peripheral output signals.
*/
#define IO_MUX_CLK_OUT1 0x0000001FU
#define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
#define IO_MUX_CLK_OUT1_V 0x0000001FU
#define IO_MUX_CLK_OUT1_S 0
/** IO_MUX_CLK_OUT2 : R/W; bitpos: [9:5]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
* CLK_OUT_out2 can be found in peripheral output signals.
*/
#define IO_MUX_CLK_OUT2 0x0000001FU
#define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
#define IO_MUX_CLK_OUT2_V 0x0000001FU
#define IO_MUX_CLK_OUT2_S 5
/** IO_MUX_CLK_OUT3 : R/W; bitpos: [14:10]; default: 7;
* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
* CLK_OUT_out3 can be found in peripheral output signals.
*/
#define IO_MUX_CLK_OUT3 0x0000001FU
#define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
#define IO_MUX_CLK_OUT3_V 0x0000001FU
#define IO_MUX_CLK_OUT3_S 10
/** IO_MUX_DATE_REG register
* IO MUX Version Control Register
*/
#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0xfc)
/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36708704;
* Version control register
*/
#define IO_MUX_REG_DATE 0x0FFFFFFFU
#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
#define IO_MUX_REG_DATE_V 0x0FFFFFFFU
#define IO_MUX_REG_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
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/**
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Registers */
/** Type of pin_ctrl register
* Clock Output Configuration Register
*/
typedef union {
struct {
/** clk_out1 : R/W; bitpos: [4:0]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
* CLK_OUT_out1 can be found in peripheral output signals.
*/
uint32_t clk_out1:5;
/** clk_out2 : R/W; bitpos: [9:5]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
* CLK_OUT_out2 can be found in peripheral output signals.
*/
uint32_t clk_out2:5;
/** clk_out3 : R/W; bitpos: [14:10]; default: 7;
* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
* CLK_OUT_out3 can be found in peripheral output signals.
*/
uint32_t clk_out3:5;
uint32_t reserved_15:17;
};
uint32_t val;
} io_mux_pin_ctrl_reg_t;
/** Type of gpio register
* IO MUX Configure Register for pad XTAL_32K_P
*/
typedef union {
struct {
/** mcu_oe : R/W; bitpos: [0]; default: 0;
* Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled.
*/
uint32_t mcu_oe:1;
/** slp_sel : R/W; bitpos: [1]; default: 0;
* Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
*/
uint32_t slp_sel:1;
/** mcu_wpd : R/W; bitpos: [2]; default: 0;
* Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0:
* internal pull-down disabled.
*/
uint32_t mcu_wpd:1;
/** mcu_wpu : R/W; bitpos: [3]; default: 0;
* Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0:
* internal pull-up disabled.
*/
uint32_t mcu_wpu:1;
/** mcu_ie : R/W; bitpos: [4]; default: 0;
* Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled.
*/
uint32_t mcu_ie:1;
/** mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2:
* ~20mA. 3: ~40mA.
*/
uint32_t mcu_drv:2;
/** fun_wpd : R/W; bitpos: [7]; default: 0;
* Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down
* disabled.
*/
uint32_t fun_wpd:1;
/** fun_wpu : R/W; bitpos: [8]; default: 0;
* Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up
* disabled.
*/
uint32_t fun_wpu:1;
/** fun_ie : R/W; bitpos: [9]; default: 0;
* Input enable of the pad. 1: input enabled. 0: input disabled.
*/
uint32_t fun_ie:1;
/** fun_drv : R/W; bitpos: [11:10]; default: 2;
* Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA.
*/
uint32_t fun_drv:2;
/** mcu_sel : R/W; bitpos: [14:12]; default: 0;
* Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2.
* etc.
*/
uint32_t mcu_sel:3;
/** filter_en : R/W; bitpos: [15]; default: 0;
* Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled.
*/
uint32_t filter_en:1;
/** hys_en : R/W; bitpos: [16]; default: 0;
* Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0:
* Hysteresis disabled.
*/
uint32_t hys_en:1;
/** hys_sel : R/W; bitpos: [17]; default: 0;
* Select enabling signals of the pad from software and efuse hardware. 1: Select
* enabling signal from slftware. 0: Select enabling signal from efuse hardware.
*/
uint32_t hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} io_mux_gpio_reg_t;
/** Type of date register
* IO MUX Version Control Register
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [27:0]; default: 36708704;
* Version control register
*/
uint32_t reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} io_mux_date_reg_t;
typedef struct io_mux_dev_t {
volatile io_mux_pin_ctrl_reg_t pin_ctrl;
volatile io_mux_gpio_reg_t gpio[27];
uint32_t reserved_070[35];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** KEYMNG_CLK_REG register
* Key Manager clock gate control register
*/
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define KEYMNG_CLK_EN (BIT(0))
#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S)
#define KEYMNG_CLK_EN_V 0x00000001U
#define KEYMNG_CLK_EN_S 0
/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_MEM_CG_FORCE_ON_S 1
/** KEYMNG_INT_RAW_REG register
* Key Manager interrupt raw register, valid in level.
*/
#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_RAW_S 0
/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_RAW_S 1
/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_POST_DONE_INT_RAW_S 2
/** KEYMNG_INT_ST_REG register
* Key Manager interrupt status register.
*/
#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ST_S 0
/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ST_S 1
/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ST (BIT(2))
#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ST_S 2
/** KEYMNG_INT_ENA_REG register
* Key Manager interrupt enable register.
*/
#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ENA_S 0
/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ENA_S 1
/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ENA_S 2
/** KEYMNG_INT_CLR_REG register
* Key Manager interrupt clear register.
*/
#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_CLR_S 0
/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_CLR_S 1
/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_POST_DONE_INT_CLR_S 2
/** KEYMNG_STATIC_REG register
* Key Manager static configuration register
*/
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [1:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key
*/
#define KEYMNG_USE_EFUSE_KEY 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
#define KEYMNG_USE_EFUSE_KEY_V 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_S 0
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_S 4
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY (BIT(9))
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_S 9
/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0;
* Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
* xts-aes-128.
*/
#define KEYMNG_XTS_AES_KEY_LEN (BIT(10))
#define KEYMNG_XTS_AES_KEY_LEN_M (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S)
#define KEYMNG_XTS_AES_KEY_LEN_V 0x00000001U
#define KEYMNG_XTS_AES_KEY_LEN_S 10
/** KEYMNG_LOCK_REG register
* Key Manager static configuration locker register
*/
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [1:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(4))
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 4
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(5))
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 5
/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_xts_aes_key_len.
*/
#define KEYMNG_XTS_AES_KEY_LEN_LOCK (BIT(6))
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S)
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S 6
/** KEYMNG_CONF_REG register
* Key Manager configuration register
*/
#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
#define KEYMNG_KGEN_MODE 0x00000007U
#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
#define KEYMNG_KGEN_MODE_V 0x00000007U
#define KEYMNG_KGEN_MODE_S 0
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
* xts_256_2_key. 4. xts_128_key. others: reserved.
*/
#define KEYMNG_KEY_PURPOSE 0x0000000FU
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
#define KEYMNG_KEY_PURPOSE_S 3
/** KEYMNG_START_REG register
* Key Manager control register
*/
#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
/** KEYMNG_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
#define KEYMNG_START (BIT(0))
#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
#define KEYMNG_START_V 0x00000001U
#define KEYMNG_START_S 0
/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
#define KEYMNG_CONTINUE (BIT(1))
#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
#define KEYMNG_CONTINUE_V 0x00000001U
#define KEYMNG_CONTINUE_S 1
/** KEYMNG_STATE_REG register
* Key Manager state register
*/
#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define KEYMNG_STATE 0x00000003U
#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
#define KEYMNG_STATE_V 0x00000003U
#define KEYMNG_STATE_S 0
/** KEYMNG_RESULT_REG register
* Key Manager operation result register
*/
#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
#define KEYMNG_PROC_RESULT (BIT(0))
#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
#define KEYMNG_PROC_RESULT_V 0x00000001U
#define KEYMNG_PROC_RESULT_S 0
/** KEYMNG_KEY_VLD_REG register
* Key Manager key status register
*/
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_VLD (BIT(0))
#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_VLD_S 0
/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0;
* The status bit for key_xts. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_XTS_VLD (BIT(1))
#define KEYMNG_KEY_XTS_VLD_M (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S)
#define KEYMNG_KEY_XTS_VLD_V 0x00000001U
#define KEYMNG_KEY_XTS_VLD_S 1
/** KEYMNG_HUK_VLD_REG register
* Key Manager HUK status register
*/
#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
#define KEYMNG_HUK_VALID (BIT(0))
#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
#define KEYMNG_HUK_VALID_V 0x00000001U
#define KEYMNG_HUK_VALID_S 0
/** KEYMNG_DATE_REG register
* Version control register
*/
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704;
* Key Manager version control register.
*/
#define KEYMNG_DATE 0x0FFFFFFFU
#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
#define KEYMNG_DATE_V 0x0FFFFFFFU
#define KEYMNG_DATE_S 0
/** KEYMNG_ASSIST_INFO_MEM register
* The memory that stores assist key info.
*/
#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_PUBLIC_INFO_MEM register
* The memory that stores public key info.
*/
#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_SW_INIT_KEY_MEM register
* The memory that stores software written init key.
*/
#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* Key Manager clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Key Manager interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_raw_reg_t;
/** Type of int_st register
* Key Manager interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_st_reg_t;
/** Type of int_ena register
* Key Manager interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_ena_reg_t;
/** Type of int_clr register
* Key Manager interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_clr_reg_t;
/** Group: Static configuration registers */
/** Type of static register
* Key Manager static configuration register
*/
typedef union {
struct {
/** use_efuse_key : R/W; bitpos: [1:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key
*/
uint32_t use_efuse_key:2;
uint32_t reserved_2:2;
/** rnd_switch_cycle : R/W; bitpos: [8:4]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
uint32_t rnd_switch_cycle:5;
/** use_sw_init_key : R/W; bitpos: [9]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
uint32_t use_sw_init_key:1;
/** xts_aes_key_len : R/W; bitpos: [10]; default: 0;
* Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
* xts-aes-128.
*/
uint32_t xts_aes_key_len:1;
uint32_t reserved_11:21;
};
uint32_t val;
} keymng_static_reg_t;
/** Type of lock register
* Key Manager static configuration locker register
*/
typedef union {
struct {
/** use_efuse_key_lock : R/W1; bitpos: [1:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
uint32_t use_efuse_key_lock:2;
uint32_t reserved_2:2;
/** rnd_switch_cycle_lock : R/W1; bitpos: [4]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
uint32_t rnd_switch_cycle_lock:1;
/** use_sw_init_key_lock : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
uint32_t use_sw_init_key_lock:1;
/** xts_aes_key_len_lock : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_xts_aes_key_len.
*/
uint32_t xts_aes_key_len_lock:1;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_lock_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* Key Manager configuration register
*/
typedef union {
struct {
/** kgen_mode : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
uint32_t kgen_mode:3;
/** key_purpose : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
* xts_256_2_key. 4. xts_128_key. others: reserved.
*/
uint32_t key_purpose:4;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* Key Manager control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
uint32_t start:1;
/** conti : WT; bitpos: [1]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_start_reg_t;
/** Group: State registers */
/** Type of state register
* Key Manager state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_state_reg_t;
/** Group: Result registers */
/** Type of result register
* Key Manager operation result register
*/
typedef union {
struct {
/** proc_result : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
uint32_t proc_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_result_reg_t;
/** Type of key_vld register
* Key Manager key status register
*/
typedef union {
struct {
/** key_ecdsa_vld : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_ecdsa_vld:1;
/** key_xts_vld : RO; bitpos: [1]; default: 0;
* The status bit for key_xts. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_xts_vld:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_key_vld_reg_t;
/** Type of huk_vld register
* Key Manager HUK status register
*/
typedef union {
struct {
/** huk_valid : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
uint32_t huk_valid:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_huk_vld_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
* Key Manager version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} keymng_date_reg_t;
typedef struct keymng_dev_t {
uint32_t reserved_000;
volatile keymng_clk_reg_t clk;
volatile keymng_int_raw_reg_t int_raw;
volatile keymng_int_st_reg_t int_st;
volatile keymng_int_ena_reg_t int_ena;
volatile keymng_int_clr_reg_t int_clr;
volatile keymng_static_reg_t static_cfg;
volatile keymng_lock_reg_t lock;
volatile keymng_conf_reg_t conf;
volatile keymng_start_reg_t start;
volatile keymng_state_reg_t state;
volatile keymng_result_reg_t result;
volatile keymng_key_vld_reg_t key_vld;
volatile keymng_huk_vld_reg_t huk_vld;
uint32_t reserved_038[49];
volatile keymng_date_reg_t date;
volatile uint32_t assist_info[16];
volatile uint32_t public_info[16];
volatile uint32_t sw_init_key[8];
} keymng_dev_t;
extern keymng_dev_t KEYMNG;
#ifndef __cplusplus
_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_ANA_BOD_MODE0_CNTL_REG register
* need_des
*/
#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6))
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6
/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7))
#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7
/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
* need_des
*/
#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8
/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
* need_des
*/
#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18
/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28))
#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_CNT_CLR_S 28
/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29))
#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INTR_ENA_S 29
/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30))
#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_SEL_S 30
/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_ENA_S 31
/** LP_ANA_BOD_MODE1_CNTL_REG register
* need_des
*/
#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE1_RESET_ENA_S 31
/** LP_ANA_CK_GLITCH_CNTL_REG register
* need_des
*/
#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANA_CK_GLITCH_RESET_ENA_S 31
/** LP_ANA_FIB_ENABLE_REG register
* need_des
*/
#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
*/
#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_S 0
/** LP_ANA_INT_RAW_REG register
* need_des
*/
#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_RAW_S 31
/** LP_ANA_INT_ST_REG register
* need_des
*/
#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ST_S 31
/** LP_ANA_INT_ENA_REG register
* need_des
*/
#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ENA_S 31
/** LP_ANA_INT_CLR_REG register
* need_des
*/
#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_CLR_S 31
/** LP_ANA_LP_INT_RAW_REG register
* need_des
*/
#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31
/** LP_ANA_LP_INT_ST_REG register
* need_des
*/
#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31
/** LP_ANA_LP_INT_ENA_REG register
* need_des
*/
#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31
/** LP_ANA_LP_INT_CLR_REG register
* need_des
*/
#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31
/** LP_ANA_DATE_REG register
* need_des
*/
#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 35660384;
* need_des
*/
#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_S 0
/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_CLK_EN (BIT(31))
#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
#define LP_ANA_CLK_EN_V 0x00000001U
#define LP_ANA_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of bod_mode0_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
* need_des
*/
uint32_t bod_mode0_close_flash_ena:1;
/** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
* need_des
*/
uint32_t bod_mode0_pd_rf_ena:1;
/** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
* need_des
*/
uint32_t bod_mode0_intr_wait:10;
/** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
* need_des
*/
uint32_t bod_mode0_reset_wait:10;
/** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t bod_mode0_cnt_clr:1;
/** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t bod_mode0_intr_ena:1;
/** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t bod_mode0_reset_sel:1;
/** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode0_cntl_reg_t;
/** Type of bod_mode1_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode1_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode1_cntl_reg_t;
/** Type of ck_glitch_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_ana_ck_glitch_cntl_reg_t;
/** Type of fib_enable register
* need_des
*/
typedef union {
struct {
/** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
*/
uint32_t ana_fib_ena:32;
};
uint32_t val;
} lp_ana_fib_enable_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_int_raw:1;
};
uint32_t val;
} lp_ana_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_int_st:1;
};
uint32_t val;
} lp_ana_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_int_ena:1;
};
uint32_t val;
} lp_ana_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_int_clr:1;
};
uint32_t val;
} lp_ana_int_clr_reg_t;
/** Type of lp_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_lp_int_raw:1;
};
uint32_t val;
} lp_ana_lp_int_raw_reg_t;
/** Type of lp_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_lp_int_st:1;
};
uint32_t val;
} lp_ana_lp_int_st_reg_t;
/** Type of lp_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_lp_int_ena:1;
};
uint32_t val;
} lp_ana_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_lp_int_clr:1;
};
uint32_t val;
} lp_ana_lp_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lp_ana_date : R/W; bitpos: [30:0]; default: 35660384;
* need_des
*/
uint32_t lp_ana_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_ana_date_reg_t;
typedef struct lp_ana_dev_t {
volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
volatile lp_ana_fib_enable_reg_t fib_enable;
volatile lp_ana_int_raw_reg_t int_raw;
volatile lp_ana_int_st_reg_t int_st;
volatile lp_ana_int_ena_reg_t int_ena;
volatile lp_ana_int_clr_reg_t int_clr;
volatile lp_ana_lp_int_raw_reg_t lp_int_raw;
volatile lp_ana_lp_int_st_reg_t lp_int_st;
volatile lp_ana_lp_int_ena_reg_t lp_int_ena;
volatile lp_ana_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_030[243];
volatile lp_ana_date_reg_t date;
} lp_ana_dev_t;
extern lp_ana_dev_t LP_ANA_PERI;
#ifndef __cplusplus
_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

466
components/soc/esp32c5/beta3/include/soc/lp_aon_reg.h
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@ -1,466 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_AON_STORE0_REG register
* need_des
*/
#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S)
#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE0_S 0
/** LP_AON_STORE1_REG register
* need_des
*/
#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S)
#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE1_S 0
/** LP_AON_STORE2_REG register
* need_des
*/
#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S)
#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE2_S 0
/** LP_AON_STORE3_REG register
* need_des
*/
#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S)
#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE3_S 0
/** LP_AON_STORE4_REG register
* need_des
*/
#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S)
#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE4_S 0
/** LP_AON_STORE5_REG register
* need_des
*/
#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S)
#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE5_S 0
/** LP_AON_STORE6_REG register
* need_des
*/
#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S)
#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE6_S 0
/** LP_AON_STORE7_REG register
* need_des
*/
#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S)
#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE7_S 0
/** LP_AON_STORE8_REG register
* need_des
*/
#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S)
#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE8_S 0
/** LP_AON_STORE9_REG register
* need_des
*/
#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S)
#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE9_S 0
/** LP_AON_GPIO_MUX_REG register
* need_des
*/
#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_MUX_SEL 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_S 0
/** LP_AON_GPIO_HOLD0_REG register
* need_des
*/
#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_S 0
/** LP_AON_GPIO_HOLD1_REG register
* need_des
*/
#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_S 0
/** LP_AON_SYS_CFG_REG register
* need_des
*/
#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30))
#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U
#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30
/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_HPSYS_SW_RESET (BIT(31))
#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
#define LP_AON_HPSYS_SW_RESET_V 0x00000001U
#define LP_AON_HPSYS_SW_RESET_S 31
/** LP_AON_CPUCORE0_CFG_REG register
* need_des
*/
#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_S 0
/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_SW_RESET (BIT(28))
#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_SW_RESET_S 28
/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29))
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29
/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30))
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30
/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31))
#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U
#define LP_AON_CPU_CORE0_DRESET_MASK_S 31
/** LP_AON_IO_MUX_REG register
* need_des
*/
#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31))
#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U
#define LP_AON_IO_MUX_RESET_DISABLE_S 31
/** LP_AON_EXT_WAKEUP_CNTL_REG register
* need_des
*/
#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_S 0
/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14))
#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U
#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14
/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_S 15
/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_LV 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_S 23
/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_FILTER (BIT(31))
#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U
#define LP_AON_EXT_WAKEUP_FILTER_S 31
/** LP_AON_USB_REG register
* need_des
*/
#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44)
/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_USB_RESET_DISABLE (BIT(31))
#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
#define LP_AON_USB_RESET_DISABLE_V 0x00000001U
#define LP_AON_USB_RESET_DISABLE_S 31
/** LP_AON_LPBUS_REG register
* need_des
*/
#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28))
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28
/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29))
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29
/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30))
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30
/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL (BIT(31))
#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_S 31
/** LP_AON_SDIO_ACTIVE_REG register
* need_des
*/
#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
#define LP_AON_SDIO_ACT_DNUM 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_S 22
/** LP_AON_LPCORE_REG register
* need_des
*/
#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50)
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1
/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_DISABLE (BIT(31))
#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S)
#define LP_AON_LPCORE_DISABLE_V 0x00000001U
#define LP_AON_LPCORE_DISABLE_S 31
/** LP_AON_SAR_CCT_REG register
* need_des
*/
#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
#define LP_AON_SAR2_PWDET_CCT 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_S 29
/** LP_AON_MODEM_BUS_REG register
* need_des
*/
#define LP_AON_MODEM_BUS_REG (DR_REG_LP_AON_BASE + 0x58)
/** LP_AON_MODEM_SYNC_BRIDGE_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_MODEM_SYNC_BRIDGE_EN (BIT(31))
#define LP_AON_MODEM_SYNC_BRIDGE_EN_M (LP_AON_MODEM_SYNC_BRIDGE_EN_V << LP_AON_MODEM_SYNC_BRIDGE_EN_S)
#define LP_AON_MODEM_SYNC_BRIDGE_EN_V 0x00000001U
#define LP_AON_MODEM_SYNC_BRIDGE_EN_S 31
/** LP_AON_AUDIO_CODEC_CTRL_REG register
* need_des
*/
#define LP_AON_AUDIO_CODEC_CTRL_REG (DR_REG_LP_AON_BASE + 0x5c)
/** LP_AON_RTC_XPD_SDADC : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define LP_AON_RTC_XPD_SDADC (BIT(0))
#define LP_AON_RTC_XPD_SDADC_M (LP_AON_RTC_XPD_SDADC_V << LP_AON_RTC_XPD_SDADC_S)
#define LP_AON_RTC_XPD_SDADC_V 0x00000001U
#define LP_AON_RTC_XPD_SDADC_S 0
/** LP_AON_RTC_EN_CLK_AUDIO_DAC : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define LP_AON_RTC_EN_CLK_AUDIO_DAC (BIT(1))
#define LP_AON_RTC_EN_CLK_AUDIO_DAC_M (LP_AON_RTC_EN_CLK_AUDIO_DAC_V << LP_AON_RTC_EN_CLK_AUDIO_DAC_S)
#define LP_AON_RTC_EN_CLK_AUDIO_DAC_V 0x00000001U
#define LP_AON_RTC_EN_CLK_AUDIO_DAC_S 1
/** LP_AON_RTC_XPD_BIAS_AUDIO_DAC : R/W; bitpos: [2]; default: 0;
* need_des
*/
#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC (BIT(2))
#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_M (LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V << LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S)
#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V 0x00000001U
#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S 2
/** LP_AON_RTC_XPD_PLLA : R/W; bitpos: [3]; default: 1;
* need_des
*/
#define LP_AON_RTC_XPD_PLLA (BIT(3))
#define LP_AON_RTC_XPD_PLLA_M (LP_AON_RTC_XPD_PLLA_V << LP_AON_RTC_XPD_PLLA_S)
#define LP_AON_RTC_XPD_PLLA_V 0x00000001U
#define LP_AON_RTC_XPD_PLLA_S 3
/** LP_AON_SPRAM_CTRL_REG register
* need_des
*/
#define LP_AON_SPRAM_CTRL_REG (DR_REG_LP_AON_BASE + 0x60)
/** LP_AON_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
#define LP_AON_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define LP_AON_SPRAM_MEM_AUX_CTRL_M (LP_AON_SPRAM_MEM_AUX_CTRL_V << LP_AON_SPRAM_MEM_AUX_CTRL_S)
#define LP_AON_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define LP_AON_SPRAM_MEM_AUX_CTRL_S 0
/** LP_AON_SPRF_CTRL_REG register
* need_des
*/
#define LP_AON_SPRF_CTRL_REG (DR_REG_LP_AON_BASE + 0x64)
/** LP_AON_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
#define LP_AON_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define LP_AON_SPRF_MEM_AUX_CTRL_M (LP_AON_SPRF_MEM_AUX_CTRL_V << LP_AON_SPRF_MEM_AUX_CTRL_S)
#define LP_AON_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define LP_AON_SPRF_MEM_AUX_CTRL_S 0
/** LP_AON_DATE_REG register
* need_des
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36720768;
* need_des
*/
#define LP_AON_DATE 0x7FFFFFFFU
#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S)
#define LP_AON_DATE_V 0x7FFFFFFFU
#define LP_AON_DATE_S 0
/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_CLK_EN (BIT(31))
#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
#define LP_AON_CLK_EN_V 0x00000001U
#define LP_AON_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

365
components/soc/esp32c5/beta3/include/soc/lp_aon_struct.h
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@ -1,365 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of store n register
* need_des
*/
typedef union {
struct {
/** lp_aon_store : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store:32;
};
uint32_t val;
} lp_aon_store_reg_t;
/** Type of gpio_mux register
* need_des
*/
typedef union {
struct {
/** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t gpio_mux_sel:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_aon_gpio_mux_reg_t;
/** Type of gpio_hold0 register
* need_des
*/
typedef union {
struct {
/** gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t gpio_hold0:32;
};
uint32_t val;
} lp_aon_gpio_hold0_reg_t;
/** Type of gpio_hold1 register
* need_des
*/
typedef union {
struct {
/** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t gpio_hold1:32;
};
uint32_t val;
} lp_aon_gpio_hold1_reg_t;
/** Type of sys_cfg register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** force_download_boot : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t force_download_boot:1;
/** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t hpsys_sw_reset:1;
};
uint32_t val;
} lp_aon_sys_cfg_reg_t;
/** Type of cpucore0_cfg register
* need_des
*/
typedef union {
struct {
/** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t cpu_core0_sw_stall:8;
uint32_t reserved_8:20;
/** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t cpu_core0_sw_reset:1;
/** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t cpu_core0_ocd_halt_on_reset:1;
/** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t cpu_core0_stat_vector_sel:1;
/** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t cpu_core0_dreset_mask:1;
};
uint32_t val;
} lp_aon_cpucore0_cfg_reg_t;
/** Type of io_mux register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t io_mux_reset_disable:1;
};
uint32_t val;
} lp_aon_io_mux_reg_t;
/** Type of ext_wakeup_cntl register
* need_des
*/
typedef union {
struct {
/** ext_wakeup_status : RO; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t ext_wakeup_status:8;
uint32_t reserved_8:6;
/** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0;
* need_des
*/
uint32_t ext_wakeup_status_clr:1;
/** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0;
* need_des
*/
uint32_t ext_wakeup_sel:8;
/** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
uint32_t ext_wakeup_lv:8;
/** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ext_wakeup_filter:1;
};
uint32_t val;
} lp_aon_ext_wakeup_cntl_reg_t;
/** Type of usb register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** usb_reset_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t usb_reset_disable:1;
};
uint32_t val;
} lp_aon_usb_reg_t;
/** Type of lpbus register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_fsm_idle:1;
/** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_sel_status:1;
/** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t fast_mem_mux_sel_update:1;
/** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_sel:1;
};
uint32_t val;
} lp_aon_lpbus_reg_t;
/** Type of sdio_active register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
uint32_t sdio_act_dnum:10;
};
uint32_t val;
} lp_aon_sdio_active_reg_t;
/** Type of lpcore register
* need_des
*/
typedef union {
struct {
/** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t lpcore_etm_wakeup_flag_clr:1;
/** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t lpcore_etm_wakeup_flag:1;
uint32_t reserved_2:29;
/** lpcore_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lpcore_disable:1;
};
uint32_t val;
} lp_aon_lpcore_reg_t;
/** Type of sar_cct register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
uint32_t sar2_pwdet_cct:3;
};
uint32_t val;
} lp_aon_sar_cct_reg_t;
/** Type of modem_bus register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** modem_sync_bridge_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t modem_sync_bridge_en:1;
};
uint32_t val;
} lp_aon_modem_bus_reg_t;
/** Type of audio_codec_ctrl register
* need_des
*/
typedef union {
struct {
/** rtc_xpd_sdadc : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t rtc_xpd_sdadc:1;
/** rtc_en_clk_audio_dac : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t rtc_en_clk_audio_dac:1;
/** rtc_xpd_bias_audio_dac : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t rtc_xpd_bias_audio_dac:1;
/** rtc_xpd_plla : R/W; bitpos: [3]; default: 1;
* need_des
*/
uint32_t rtc_xpd_plla:1;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_aon_audio_codec_ctrl_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 36720768;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_aon_date_reg_t;
/** Group: Configuration Register */
/** Type of spram_ctrl register
* need_des
*/
typedef union {
struct {
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
uint32_t spram_mem_aux_ctrl:32;
};
uint32_t val;
} lp_aon_spram_ctrl_reg_t;
/** Type of sprf_ctrl register
* need_des
*/
typedef union {
struct {
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
uint32_t sprf_mem_aux_ctrl:32;
};
uint32_t val;
} lp_aon_sprf_ctrl_reg_t;
typedef struct lp_aon_dev_t {
volatile lp_aon_store_reg_t store[10];
volatile lp_aon_gpio_mux_reg_t gpio_mux;
volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
volatile lp_aon_sys_cfg_reg_t sys_cfg;
volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg;
volatile lp_aon_io_mux_reg_t io_mux;
volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
volatile lp_aon_usb_reg_t usb;
volatile lp_aon_lpbus_reg_t lpbus;
volatile lp_aon_sdio_active_reg_t sdio_active;
volatile lp_aon_lpcore_reg_t lpcore;
volatile lp_aon_sar_cct_reg_t sar_cct;
volatile lp_aon_modem_bus_reg_t modem_bus;
volatile lp_aon_audio_codec_ctrl_reg_t audio_codec_ctrl;
volatile lp_aon_spram_ctrl_reg_t spram_ctrl;
volatile lp_aon_sprf_ctrl_reg_t sprf_ctrl;
uint32_t reserved_068[229];
volatile lp_aon_date_reg_t date;
} lp_aon_dev_t;
extern lp_aon_dev_t LP_AON;
#ifndef __cplusplus
_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

534
components/soc/esp32c5/beta3/include/soc/lp_apm0_reg.h
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@ -1,534 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM0_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
#define LP_APM0_REGION_FILTER_EN 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_S 0
/** LP_APM0_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S)
#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_S 0
/** LP_APM0_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S)
#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_S 0
/** LP_APM0_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_X (BIT(0))
#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S)
#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_X_S 0
/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_W (BIT(1))
#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S)
#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_W_S 1
/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_R (BIT(2))
#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S)
#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_R_S 2
/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_X (BIT(4))
#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S)
#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_X_S 4
/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_W (BIT(5))
#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S)
#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_W_S 5
/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_R (BIT(6))
#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S)
#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_R_S 6
/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_X (BIT(8))
#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S)
#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_X_S 8
/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_W (BIT(9))
#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S)
#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_W_S 9
/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_R (BIT(10))
#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S)
#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_R_S 10
/** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION0_LOCK (BIT(11))
#define LP_APM0_REGION0_LOCK_M (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S)
#define LP_APM0_REGION0_LOCK_V 0x00000001U
#define LP_APM0_REGION0_LOCK_S 11
/** LP_APM0_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S)
#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_S 0
/** LP_APM0_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S)
#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_S 0
/** LP_APM0_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_X (BIT(0))
#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S)
#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_X_S 0
/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_W (BIT(1))
#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S)
#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_W_S 1
/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_R (BIT(2))
#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S)
#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_R_S 2
/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_X (BIT(4))
#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S)
#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_X_S 4
/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_W (BIT(5))
#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S)
#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_W_S 5
/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_R (BIT(6))
#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S)
#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_R_S 6
/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_X (BIT(8))
#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S)
#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_X_S 8
/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_W (BIT(9))
#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S)
#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_W_S 9
/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_R (BIT(10))
#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S)
#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_R_S 10
/** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region1 configuration
*/
#define LP_APM0_REGION1_LOCK (BIT(11))
#define LP_APM0_REGION1_LOCK_M (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S)
#define LP_APM0_REGION1_LOCK_V 0x00000001U
#define LP_APM0_REGION1_LOCK_S 11
/** LP_APM0_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S)
#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_S 0
/** LP_APM0_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S)
#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_S 0
/** LP_APM0_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_X (BIT(0))
#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S)
#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_X_S 0
/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_W (BIT(1))
#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S)
#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_W_S 1
/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_R (BIT(2))
#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S)
#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_R_S 2
/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_X (BIT(4))
#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S)
#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_X_S 4
/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_W (BIT(5))
#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S)
#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_W_S 5
/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_R (BIT(6))
#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S)
#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_R_S 6
/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_X (BIT(8))
#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S)
#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_X_S 8
/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_W (BIT(9))
#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S)
#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_W_S 9
/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_R (BIT(10))
#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S)
#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_R_S 10
/** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region2 configuration
*/
#define LP_APM0_REGION2_LOCK (BIT(11))
#define LP_APM0_REGION2_LOCK_M (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S)
#define LP_APM0_REGION2_LOCK_V 0x00000001U
#define LP_APM0_REGION2_LOCK_S 11
/** LP_APM0_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S)
#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_S 0
/** LP_APM0_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S)
#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_S 0
/** LP_APM0_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_X (BIT(0))
#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S)
#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_X_S 0
/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_W (BIT(1))
#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S)
#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_W_S 1
/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_R (BIT(2))
#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S)
#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_R_S 2
/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_X (BIT(4))
#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S)
#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_X_S 4
/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_W (BIT(5))
#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S)
#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_W_S 5
/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_R (BIT(6))
#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S)
#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_R_S 6
/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_X (BIT(8))
#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S)
#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_X_S 8
/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_W (BIT(9))
#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S)
#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_W_S 9
/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_R (BIT(10))
#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S)
#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_R_S 10
/** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region3 configuration
*/
#define LP_APM0_REGION3_LOCK (BIT(11))
#define LP_APM0_REGION3_LOCK_M (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S)
#define LP_APM0_REGION3_LOCK_V 0x00000001U
#define LP_APM0_REGION3_LOCK_S 11
/** LP_APM0_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM0_M0_PMS_FUNC_EN (BIT(0))
#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S)
#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U
#define LP_APM0_M0_PMS_FUNC_EN_S 0
/** LP_APM0_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_S 0
/** LP_APM0_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0))
#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S)
#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM0_M0_REGION_STATUS_CLR_S 0
/** LP_APM0_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_S 0
/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S)
#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_S 16
/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S)
#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_S 18
/** LP_APM0_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S)
#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_S 0
/** LP_APM0_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
#define LP_APM0_M0_APM_INT_EN (BIT(0))
#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
#define LP_APM0_M0_APM_INT_EN_V 0x00000001U
#define LP_APM0_M0_APM_INT_EN_S 0
/** LP_APM0_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_APM0_CLK_EN (BIT(0))
#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)
#define LP_APM0_CLK_EN_V 0x00000001U
#define LP_APM0_CLK_EN_S 0
/** LP_APM0_DATE_REG register
* Version register
*/
#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664;
* reg_date
*/
#define LP_APM0_DATE 0x0FFFFFFFU
#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S)
#define LP_APM0_DATE_V 0x0FFFFFFFU
#define LP_APM0_DATE_S 0
#ifdef __cplusplus
}
#endif

515
components/soc/esp32c5/beta3/include/soc/lp_apm0_struct.h
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@ -1,515 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm0_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of region0_addr_start register
* Region address register
*/
typedef union {
struct {
/** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
uint32_t region0_addr_start:32;
};
uint32_t val;
} lp_apm0_region0_addr_start_reg_t;
/** Type of region0_addr_end register
* Region address register
*/
typedef union {
struct {
/** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
uint32_t region0_addr_end:32;
};
uint32_t val;
} lp_apm0_region0_addr_end_reg_t;
/** Type of region1_addr_start register
* Region address register
*/
typedef union {
struct {
/** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
uint32_t region1_addr_start:32;
};
uint32_t val;
} lp_apm0_region1_addr_start_reg_t;
/** Type of region1_addr_end register
* Region address register
*/
typedef union {
struct {
/** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
uint32_t region1_addr_end:32;
};
uint32_t val;
} lp_apm0_region1_addr_end_reg_t;
/** Type of region2_addr_start register
* Region address register
*/
typedef union {
struct {
/** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
uint32_t region2_addr_start:32;
};
uint32_t val;
} lp_apm0_region2_addr_start_reg_t;
/** Type of region2_addr_end register
* Region address register
*/
typedef union {
struct {
/** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
uint32_t region2_addr_end:32;
};
uint32_t val;
} lp_apm0_region2_addr_end_reg_t;
/** Type of region3_addr_start register
* Region address register
*/
typedef union {
struct {
/** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
uint32_t region3_addr_start:32;
};
uint32_t val;
} lp_apm0_region3_addr_start_reg_t;
/** Type of region3_addr_end register
* Region address register
*/
typedef union {
struct {
/** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
uint32_t region3_addr_end:32;
};
uint32_t val;
} lp_apm0_region3_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of region0_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region0_r0_pms_x:1;
/** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region0_r0_pms_w:1;
/** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region0_r0_pms_r:1;
uint32_t reserved_3:1;
/** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region0_r1_pms_x:1;
/** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region0_r1_pms_w:1;
/** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region0_r1_pms_r:1;
uint32_t reserved_7:1;
/** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region0_r2_pms_x:1;
/** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region0_r2_pms_w:1;
/** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region0_r2_pms_r:1;
/** region0_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t region0_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm0_region0_pms_attr_reg_t;
/** Type of region1_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region1_r0_pms_x:1;
/** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region1_r0_pms_w:1;
/** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region1_r0_pms_r:1;
uint32_t reserved_3:1;
/** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region1_r1_pms_x:1;
/** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region1_r1_pms_w:1;
/** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region1_r1_pms_r:1;
uint32_t reserved_7:1;
/** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region1_r2_pms_x:1;
/** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region1_r2_pms_w:1;
/** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region1_r2_pms_r:1;
/** region1_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region1 configuration
*/
uint32_t region1_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm0_region1_pms_attr_reg_t;
/** Type of region2_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region2_r0_pms_x:1;
/** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region2_r0_pms_w:1;
/** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region2_r0_pms_r:1;
uint32_t reserved_3:1;
/** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region2_r1_pms_x:1;
/** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region2_r1_pms_w:1;
/** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region2_r1_pms_r:1;
uint32_t reserved_7:1;
/** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region2_r2_pms_x:1;
/** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region2_r2_pms_w:1;
/** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region2_r2_pms_r:1;
/** region2_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region2 configuration
*/
uint32_t region2_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm0_region2_pms_attr_reg_t;
/** Type of region3_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region3_r0_pms_x:1;
/** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region3_r0_pms_w:1;
/** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region3_r0_pms_r:1;
uint32_t reserved_3:1;
/** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region3_r1_pms_x:1;
/** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region3_r1_pms_w:1;
/** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region3_r1_pms_r:1;
uint32_t reserved_7:1;
/** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region3_r2_pms_x:1;
/** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region3_r2_pms_w:1;
/** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region3_r2_pms_r:1;
/** region3_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region3 configuration
*/
uint32_t region3_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm0_region3_pms_attr_reg_t;
/** Group: PMS function control register */
/** Type of func_ctrl register
* PMS function control register
*/
typedef union {
struct {
/** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_pms_func_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm0_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m0_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm0_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm0_m0_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
uint32_t m0_apm_int_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725664;
* reg_date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm0_date_reg_t;
typedef struct lp_apm0_dev_t {
volatile lp_apm0_region_filter_en_reg_t region_filter_en;
volatile lp_apm0_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm0_region0_addr_end_reg_t region0_addr_end;
volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr;
volatile lp_apm0_region1_addr_start_reg_t region1_addr_start;
volatile lp_apm0_region1_addr_end_reg_t region1_addr_end;
volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr;
volatile lp_apm0_region2_addr_start_reg_t region2_addr_start;
volatile lp_apm0_region2_addr_end_reg_t region2_addr_end;
volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr;
volatile lp_apm0_region3_addr_start_reg_t region3_addr_start;
volatile lp_apm0_region3_addr_end_reg_t region3_addr_end;
volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr;
uint32_t reserved_034[36];
volatile lp_apm0_func_ctrl_reg_t func_ctrl;
volatile lp_apm0_m0_status_reg_t m0_status;
volatile lp_apm0_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm0_int_en_reg_t int_en;
volatile lp_apm0_clock_gate_reg_t clock_gate;
uint32_t reserved_0e0[455];
volatile lp_apm0_date_reg_t date;
} lp_apm0_dev_t;
extern lp_apm0_dev_t LP_APM0;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/lp_apm_reg.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
#define LP_APM_REGION_FILTER_EN 0x0000000FU
#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
#define LP_APM_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM_REGION_FILTER_EN_S 0
/** LP_APM_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S)
#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_S 0
/** LP_APM_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S)
#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_S 0
/** LP_APM_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_X (BIT(0))
#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S)
#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_X_S 0
/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_W (BIT(1))
#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S)
#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_W_S 1
/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_R (BIT(2))
#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S)
#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_R_S 2
/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_X (BIT(4))
#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S)
#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_X_S 4
/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_W (BIT(5))
#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S)
#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_W_S 5
/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_R (BIT(6))
#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S)
#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_R_S 6
/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_X (BIT(8))
#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S)
#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_X_S 8
/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_W (BIT(9))
#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S)
#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_W_S 9
/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_R (BIT(10))
#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S)
#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_R_S 10
/** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION0_LOCK (BIT(11))
#define LP_APM_REGION0_LOCK_M (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S)
#define LP_APM_REGION0_LOCK_V 0x00000001U
#define LP_APM_REGION0_LOCK_S 11
/** LP_APM_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S)
#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_S 0
/** LP_APM_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S)
#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_S 0
/** LP_APM_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_X (BIT(0))
#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S)
#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_X_S 0
/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_W (BIT(1))
#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S)
#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_W_S 1
/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_R (BIT(2))
#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S)
#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_R_S 2
/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_X (BIT(4))
#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S)
#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_X_S 4
/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_W (BIT(5))
#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S)
#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_W_S 5
/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_R (BIT(6))
#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S)
#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_R_S 6
/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_X (BIT(8))
#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S)
#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_X_S 8
/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_W (BIT(9))
#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S)
#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_W_S 9
/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_R (BIT(10))
#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S)
#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_R_S 10
/** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region1 configuration
*/
#define LP_APM_REGION1_LOCK (BIT(11))
#define LP_APM_REGION1_LOCK_M (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S)
#define LP_APM_REGION1_LOCK_V 0x00000001U
#define LP_APM_REGION1_LOCK_S 11
/** LP_APM_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c)
/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S)
#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_S 0
/** LP_APM_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20)
/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S)
#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_S 0
/** LP_APM_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24)
/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_X (BIT(0))
#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S)
#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_X_S 0
/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_W (BIT(1))
#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S)
#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_W_S 1
/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_R (BIT(2))
#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S)
#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_R_S 2
/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_X (BIT(4))
#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S)
#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_X_S 4
/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_W (BIT(5))
#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S)
#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_W_S 5
/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_R (BIT(6))
#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S)
#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_R_S 6
/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_X (BIT(8))
#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S)
#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_X_S 8
/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_W (BIT(9))
#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S)
#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_W_S 9
/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_R (BIT(10))
#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S)
#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_R_S 10
/** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region2 configuration
*/
#define LP_APM_REGION2_LOCK (BIT(11))
#define LP_APM_REGION2_LOCK_M (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S)
#define LP_APM_REGION2_LOCK_V 0x00000001U
#define LP_APM_REGION2_LOCK_S 11
/** LP_APM_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28)
/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S)
#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_S 0
/** LP_APM_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c)
/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S)
#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_S 0
/** LP_APM_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30)
/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_X (BIT(0))
#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S)
#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_X_S 0
/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_W (BIT(1))
#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S)
#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_W_S 1
/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_R (BIT(2))
#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S)
#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_R_S 2
/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_X (BIT(4))
#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S)
#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_X_S 4
/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_W (BIT(5))
#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S)
#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_W_S 5
/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_R (BIT(6))
#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S)
#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_R_S 6
/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_X (BIT(8))
#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S)
#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_X_S 8
/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_W (BIT(9))
#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S)
#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_W_S 9
/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_R (BIT(10))
#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S)
#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_R_S 10
/** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region3 configuration
*/
#define LP_APM_REGION3_LOCK (BIT(11))
#define LP_APM_REGION3_LOCK_M (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S)
#define LP_APM_REGION3_LOCK_V 0x00000001U
#define LP_APM_REGION3_LOCK_S 11
/** LP_APM_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM_M0_PMS_FUNC_EN (BIT(0))
#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S)
#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U
#define LP_APM_M0_PMS_FUNC_EN_S 0
/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
#define LP_APM_M1_PMS_FUNC_EN (BIT(1))
#define LP_APM_M1_PMS_FUNC_EN_M (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S)
#define LP_APM_M1_PMS_FUNC_EN_V 0x00000001U
#define LP_APM_M1_PMS_FUNC_EN_S 1
/** LP_APM_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_S 0
/** LP_APM_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM_M0_REGION_STATUS_CLR (BIT(0))
#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S)
#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM_M0_REGION_STATUS_CLR_S 0
/** LP_APM_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_S 0
/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S)
#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_S 16
/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S)
#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_S 18
/** LP_APM_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S)
#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_S 0
/** LP_APM_M1_STATUS_REG register
* M1 status register
*/
#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8)
/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S)
#define LP_APM_M1_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_S 0
/** LP_APM_M1_STATUS_CLR_REG register
* M1 status clear register
*/
#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc)
/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM_M1_REGION_STATUS_CLR (BIT(0))
#define LP_APM_M1_REGION_STATUS_CLR_M (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S)
#define LP_APM_M1_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM_M1_REGION_STATUS_CLR_S 0
/** LP_APM_M1_EXCEPTION_INFO0_REG register
* M1 exception_info0 register
*/
#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0)
/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S)
#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_S 0
/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM_M1_EXCEPTION_MODE 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S)
#define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_S 16
/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM_M1_EXCEPTION_ID 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S)
#define LP_APM_M1_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_S 18
/** LP_APM_M1_EXCEPTION_INFO1_REG register
* M1 exception_info1 register
*/
#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4)
/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S)
#define LP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_S 0
/** LP_APM_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
#define LP_APM_M0_APM_INT_EN (BIT(0))
#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
#define LP_APM_M0_APM_INT_EN_V 0x00000001U
#define LP_APM_M0_APM_INT_EN_S 0
/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
* APM M1 interrupt enable
*/
#define LP_APM_M1_APM_INT_EN (BIT(1))
#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S)
#define LP_APM_M1_APM_INT_EN_V 0x00000001U
#define LP_APM_M1_APM_INT_EN_S 1
/** LP_APM_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_APM_CLK_EN (BIT(0))
#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)
#define LP_APM_CLK_EN_V 0x00000001U
#define LP_APM_CLK_EN_S 0
/** LP_APM_DATE_REG register
* Version register
*/
#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc)
/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664;
* reg_date
*/
#define LP_APM_DATE 0x0FFFFFFFU
#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S)
#define LP_APM_DATE_V 0x0FFFFFFFU
#define LP_APM_DATE_S 0
#ifdef __cplusplus
}
#endif

599
components/soc/esp32c5/beta3/include/soc/lp_apm_struct.h
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@ -1,599 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of region0_addr_start register
* Region address register
*/
typedef union {
struct {
/** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
uint32_t region0_addr_start:32;
};
uint32_t val;
} lp_apm_region0_addr_start_reg_t;
/** Type of region0_addr_end register
* Region address register
*/
typedef union {
struct {
/** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
uint32_t region0_addr_end:32;
};
uint32_t val;
} lp_apm_region0_addr_end_reg_t;
/** Type of region1_addr_start register
* Region address register
*/
typedef union {
struct {
/** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
uint32_t region1_addr_start:32;
};
uint32_t val;
} lp_apm_region1_addr_start_reg_t;
/** Type of region1_addr_end register
* Region address register
*/
typedef union {
struct {
/** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
uint32_t region1_addr_end:32;
};
uint32_t val;
} lp_apm_region1_addr_end_reg_t;
/** Type of region2_addr_start register
* Region address register
*/
typedef union {
struct {
/** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
uint32_t region2_addr_start:32;
};
uint32_t val;
} lp_apm_region2_addr_start_reg_t;
/** Type of region2_addr_end register
* Region address register
*/
typedef union {
struct {
/** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
uint32_t region2_addr_end:32;
};
uint32_t val;
} lp_apm_region2_addr_end_reg_t;
/** Type of region3_addr_start register
* Region address register
*/
typedef union {
struct {
/** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
uint32_t region3_addr_start:32;
};
uint32_t val;
} lp_apm_region3_addr_start_reg_t;
/** Type of region3_addr_end register
* Region address register
*/
typedef union {
struct {
/** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
uint32_t region3_addr_end:32;
};
uint32_t val;
} lp_apm_region3_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of region0_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region0_r0_pms_x:1;
/** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region0_r0_pms_w:1;
/** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region0_r0_pms_r:1;
uint32_t reserved_3:1;
/** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region0_r1_pms_x:1;
/** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region0_r1_pms_w:1;
/** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region0_r1_pms_r:1;
uint32_t reserved_7:1;
/** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region0_r2_pms_x:1;
/** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region0_r2_pms_w:1;
/** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region0_r2_pms_r:1;
/** region0_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t region0_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm_region0_pms_attr_reg_t;
/** Type of region1_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region1_r0_pms_x:1;
/** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region1_r0_pms_w:1;
/** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region1_r0_pms_r:1;
uint32_t reserved_3:1;
/** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region1_r1_pms_x:1;
/** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region1_r1_pms_w:1;
/** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region1_r1_pms_r:1;
uint32_t reserved_7:1;
/** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region1_r2_pms_x:1;
/** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region1_r2_pms_w:1;
/** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region1_r2_pms_r:1;
/** region1_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region1 configuration
*/
uint32_t region1_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm_region1_pms_attr_reg_t;
/** Type of region2_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region2_r0_pms_x:1;
/** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region2_r0_pms_w:1;
/** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region2_r0_pms_r:1;
uint32_t reserved_3:1;
/** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region2_r1_pms_x:1;
/** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region2_r1_pms_w:1;
/** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region2_r1_pms_r:1;
uint32_t reserved_7:1;
/** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region2_r2_pms_x:1;
/** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region2_r2_pms_w:1;
/** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region2_r2_pms_r:1;
/** region2_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region2 configuration
*/
uint32_t region2_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm_region2_pms_attr_reg_t;
/** Type of region3_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region3_r0_pms_x:1;
/** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region3_r0_pms_w:1;
/** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region3_r0_pms_r:1;
uint32_t reserved_3:1;
/** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region3_r1_pms_x:1;
/** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region3_r1_pms_w:1;
/** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region3_r1_pms_r:1;
uint32_t reserved_7:1;
/** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region3_r2_pms_x:1;
/** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region3_r2_pms_w:1;
/** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region3_r2_pms_r:1;
/** region3_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region3 configuration
*/
uint32_t region3_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm_region3_pms_attr_reg_t;
/** Group: PMS function control register */
/** Type of func_ctrl register
* PMS function control register
*/
typedef union {
struct {
/** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_pms_func_en:1;
/** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_pms_func_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m0_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m1_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m1_exception_region:4;
uint32_t reserved_4:12;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} lp_apm_m1_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* APM M1 interrupt enable
*/
uint32_t m1_apm_int_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725664;
* reg_date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm_date_reg_t;
typedef struct lp_apm_dev_t {
volatile lp_apm_region_filter_en_reg_t region_filter_en;
volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm_region0_addr_end_reg_t region0_addr_end;
volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr;
volatile lp_apm_region1_addr_start_reg_t region1_addr_start;
volatile lp_apm_region1_addr_end_reg_t region1_addr_end;
volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr;
volatile lp_apm_region2_addr_start_reg_t region2_addr_start;
volatile lp_apm_region2_addr_end_reg_t region2_addr_end;
volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr;
volatile lp_apm_region3_addr_start_reg_t region3_addr_start;
volatile lp_apm_region3_addr_end_reg_t region3_addr_end;
volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr;
uint32_t reserved_034[36];
volatile lp_apm_func_ctrl_reg_t func_ctrl;
volatile lp_apm_m0_status_reg_t m0_status;
volatile lp_apm_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm_m1_status_reg_t m1_status;
volatile lp_apm_m1_status_clr_reg_t m1_status_clr;
volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile lp_apm_int_en_reg_t int_en;
volatile lp_apm_clock_gate_reg_t clock_gate;
uint32_t reserved_0f0[3];
volatile lp_apm_date_reg_t date;
} lp_apm_dev_t;
extern lp_apm_dev_t LP_APM;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/lp_clkrst_reg.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_CLKRST_LP_CLK_CONF_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
* need_des
*/
#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_S 0
/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
* need_des
*/
#define LP_CLKRST_FAST_CLK_SEL 0x00000003U
#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U
#define LP_CLKRST_FAST_CLK_SEL_S 2
/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_S 4
/** LP_CLKRST_LP_CLK_PO_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
* need_des
*/
#define LP_CLKRST_AON_SLOW_OEN (BIT(0))
#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_AON_SLOW_OEN_S 0
/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
* need_des
*/
#define LP_CLKRST_AON_FAST_OEN (BIT(1))
#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U
#define LP_CLKRST_AON_FAST_OEN_S 1
/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
* need_des
*/
#define LP_CLKRST_SOSC_OEN (BIT(2))
#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
#define LP_CLKRST_SOSC_OEN_V 0x00000001U
#define LP_CLKRST_SOSC_OEN_S 2
/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
* need_des
*/
#define LP_CLKRST_FOSC_OEN (BIT(3))
#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
#define LP_CLKRST_FOSC_OEN_V 0x00000001U
#define LP_CLKRST_FOSC_OEN_S 3
/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
* need_des
*/
#define LP_CLKRST_OSC32K_OEN (BIT(4))
#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
#define LP_CLKRST_OSC32K_OEN_V 0x00000001U
#define LP_CLKRST_OSC32K_OEN_S 4
/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
* need_des
*/
#define LP_CLKRST_XTAL32K_OEN (BIT(5))
#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U
#define LP_CLKRST_XTAL32K_OEN_S 5
/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
* need_des
*/
#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6))
#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U
#define LP_CLKRST_CORE_EFUSE_OEN_S 6
/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
* need_des
*/
#define LP_CLKRST_SLOW_OEN (BIT(7))
#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
#define LP_CLKRST_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_SLOW_OEN_S 7
/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
* need_des
*/
#define LP_CLKRST_FAST_OEN (BIT(8))
#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
#define LP_CLKRST_FAST_OEN_V 0x00000001U
#define LP_CLKRST_FAST_OEN_S 8
/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
* need_des
*/
#define LP_CLKRST_RNG_OEN (BIT(9))
#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
#define LP_CLKRST_RNG_OEN_V 0x00000001U
#define LP_CLKRST_RNG_OEN_S 9
/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
* need_des
*/
#define LP_CLKRST_LPBUS_OEN (BIT(10))
#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
#define LP_CLKRST_LPBUS_OEN_V 0x00000001U
#define LP_CLKRST_LPBUS_OEN_S 10
/** LP_CLKRST_LP_CLK_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_FAST_ORI_GATE (BIT(31))
#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U
#define LP_CLKRST_FAST_ORI_GATE_S 31
/** LP_CLKRST_LP_RST_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
/** LP_CLKRST_HUK_RESET_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LP_CLKRST_HUK_RESET_EN (BIT(27))
#define LP_CLKRST_HUK_RESET_EN_M (LP_CLKRST_HUK_RESET_EN_V << LP_CLKRST_HUK_RESET_EN_S)
#define LP_CLKRST_HUK_RESET_EN_V 0x00000001U
#define LP_CLKRST_HUK_RESET_EN_S 27
/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28))
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28
/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29))
#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U
#define LP_CLKRST_LP_TIMER_RESET_EN_S 29
/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_WDT_RESET_EN (BIT(30))
#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U
#define LP_CLKRST_WDT_RESET_EN_S 30
/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31))
#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U
#define LP_CLKRST_ANA_PERI_RESET_EN_S 31
/** LP_CLKRST_RESET_CAUSE_REG register
* need_des
*/
#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
* need_des
*/
#define LP_CLKRST_RESET_CAUSE 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_S 0
/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5))
#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_S 5
/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29))
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29
/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30))
#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30
/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31))
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31
/** LP_CLKRST_CPU_RESET_REG register
* need_des
*/
#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1;
* write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
* reset feature
*/
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(21))
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 21
/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
* need_des
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22
/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25))
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25
/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
* need_des
*/
#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_S 26
/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CPU_STALL_EN (BIT(31))
#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U
#define LP_CLKRST_CPU_STALL_EN_S 31
/** LP_CLKRST_FOSC_CNTL_REG register
* need_des
*/
#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
#define LP_CLKRST_FOSC_DFREQ 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_S 22
/** LP_CLKRST_RC32K_CNTL_REG register
* need_des
*/
#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
#define LP_CLKRST_RC32K_DFREQ 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_S 22
/** LP_CLKRST_CLK_TO_HP_REG register
* need_des
*/
#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28))
#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_XTAL32K_S 28
/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_SOSC (BIT(29))
#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_SOSC_S 29
/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_OSC32K (BIT(30))
#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_OSC32K_S 30
/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_FOSC (BIT(31))
#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_FOSC_S 31
/** LP_CLKRST_LPMEM_FORCE_REG register
* need_des
*/
#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31))
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31
/** LP_CLKRST_LPPERI_REG register
* need_des
*/
#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28)
/** LP_CLKRST_HUK_CLK_SEL : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LP_CLKRST_HUK_CLK_SEL (BIT(29))
#define LP_CLKRST_HUK_CLK_SEL_M (LP_CLKRST_HUK_CLK_SEL_V << LP_CLKRST_HUK_CLK_SEL_S)
#define LP_CLKRST_HUK_CLK_SEL_V 0x00000001U
#define LP_CLKRST_HUK_CLK_SEL_S 29
/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30))
#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S)
#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_I2C_CLK_SEL_S 30
/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31))
#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S)
#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_UART_CLK_SEL_S 31
/** LP_CLKRST_XTAL32K_REG register
* need_des
*/
#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
* need_des
*/
#define LP_CLKRST_DRES_XTAL32K 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_S 22
/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
* need_des
*/
#define LP_CLKRST_DGM_XTAL32K 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_S 25
/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_CLKRST_DBUF_XTAL32K (BIT(28))
#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U
#define LP_CLKRST_DBUF_XTAL32K_S 28
/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
* need_des
*/
#define LP_CLKRST_DAC_XTAL32K 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_S 29
/** LP_CLKRST_DATE_REG register
* need_des
*/
#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36720768;
* need_des
*/
#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_S 0
/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CLK_EN (BIT(31))
#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
#define LP_CLKRST_CLK_EN_V 0x00000001U
#define LP_CLKRST_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

354
components/soc/esp32c5/beta3/include/soc/lp_clkrst_struct.h
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@ -1,354 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_clk_conf register
* need_des
*/
typedef union {
struct {
/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
* need_des
*/
uint32_t slow_clk_sel:2;
/** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
* need_des
*/
uint32_t fast_clk_sel:2;
/** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0;
* need_des
*/
uint32_t lp_peri_div_num:8;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_clkrst_lp_clk_conf_reg_t;
/** Type of lp_clk_po_en register
* need_des
*/
typedef union {
struct {
/** aon_slow_oen : R/W; bitpos: [0]; default: 1;
* need_des
*/
uint32_t aon_slow_oen:1;
/** aon_fast_oen : R/W; bitpos: [1]; default: 1;
* need_des
*/
uint32_t aon_fast_oen:1;
/** sosc_oen : R/W; bitpos: [2]; default: 1;
* need_des
*/
uint32_t sosc_oen:1;
/** fosc_oen : R/W; bitpos: [3]; default: 1;
* need_des
*/
uint32_t fosc_oen:1;
/** osc32k_oen : R/W; bitpos: [4]; default: 1;
* need_des
*/
uint32_t osc32k_oen:1;
/** xtal32k_oen : R/W; bitpos: [5]; default: 1;
* need_des
*/
uint32_t xtal32k_oen:1;
/** core_efuse_oen : R/W; bitpos: [6]; default: 1;
* need_des
*/
uint32_t core_efuse_oen:1;
/** slow_oen : R/W; bitpos: [7]; default: 1;
* need_des
*/
uint32_t slow_oen:1;
/** fast_oen : R/W; bitpos: [8]; default: 1;
* need_des
*/
uint32_t fast_oen:1;
/** rng_oen : R/W; bitpos: [9]; default: 1;
* need_des
*/
uint32_t rng_oen:1;
/** lpbus_oen : R/W; bitpos: [10]; default: 1;
* need_des
*/
uint32_t lpbus_oen:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_clkrst_lp_clk_po_en_reg_t;
/** Type of lp_clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** fast_ori_gate : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t fast_ori_gate:1;
};
uint32_t val;
} lp_clkrst_lp_clk_en_reg_t;
/** Type of lp_rst_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** huk_reset_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t huk_reset_en:1;
/** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t aon_efuse_core_reset_en:1;
/** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_timer_reset_en:1;
/** wdt_reset_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t wdt_reset_en:1;
/** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_peri_reset_en:1;
};
uint32_t val;
} lp_clkrst_lp_rst_en_reg_t;
/** Type of reset_cause register
* need_des
*/
typedef union {
struct {
/** reset_cause : RO; bitpos: [4:0]; default: 0;
* need_des
*/
uint32_t reset_cause:5;
/** core0_reset_flag : RO; bitpos: [5]; default: 1;
* need_des
*/
uint32_t core0_reset_flag:1;
uint32_t reserved_6:23;
/** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t core0_reset_cause_clr:1;
/** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t core0_reset_flag_set:1;
/** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t core0_reset_flag_clr:1;
};
uint32_t val;
} lp_clkrst_reset_cause_reg_t;
/** Type of cpu_reset register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1;
* write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
* reset feature
*/
uint32_t hpcore0_lockup_reset_en:1;
/** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
* need_des
*/
uint32_t rtc_wdt_cpu_reset_length:3;
/** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t rtc_wdt_cpu_reset_en:1;
/** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
* need_des
*/
uint32_t cpu_stall_wait:5;
/** cpu_stall_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t cpu_stall_en:1;
};
uint32_t val;
} lp_clkrst_cpu_reset_reg_t;
/** Type of fosc_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
uint32_t fosc_dfreq:10;
};
uint32_t val;
} lp_clkrst_fosc_cntl_reg_t;
/** Type of rc32k_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
uint32_t rc32k_dfreq:10;
};
uint32_t val;
} lp_clkrst_rc32k_cntl_reg_t;
/** Type of clk_to_hp register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
* need_des
*/
uint32_t icg_hp_xtal32k:1;
/** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t icg_hp_sosc:1;
/** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t icg_hp_osc32k:1;
/** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t icg_hp_fosc:1;
};
uint32_t val;
} lp_clkrst_clk_to_hp_reg_t;
/** Type of lpmem_force register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lpmem_clk_force_on:1;
};
uint32_t val;
} lp_clkrst_lpmem_force_reg_t;
/** Type of lpperi register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** huk_clk_sel : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t huk_clk_sel:1;
/** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_i2c_clk_sel:1;
/** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_uart_clk_sel:1;
};
uint32_t val;
} lp_clkrst_lpperi_reg_t;
/** Type of xtal32k register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
* need_des
*/
uint32_t dres_xtal32k:3;
/** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
* need_des
*/
uint32_t dgm_xtal32k:3;
/** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t dbuf_xtal32k:1;
/** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
* need_des
*/
uint32_t dac_xtal32k:3;
};
uint32_t val;
} lp_clkrst_xtal32k_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** clkrst_date : R/W; bitpos: [30:0]; default: 36720768;
* need_des
*/
uint32_t clkrst_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_clkrst_date_reg_t;
typedef struct lp_clkrst_dev_t {
volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
volatile lp_clkrst_reset_cause_reg_t reset_cause;
volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
volatile lp_clkrst_lpperi_reg_t lpperi;
volatile lp_clkrst_xtal32k_reg_t xtal32k;
uint32_t reserved_030[243];
volatile lp_clkrst_date_reg_t date;
} lp_clkrst_dev_t;
extern lp_clkrst_dev_t LP_CLKRST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

135
components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_reg.h
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@ -1,135 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_I2C_ANA_MST_I2C0_CTRL_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0)
/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CTRL 0x01FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CTRL_M (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S)
#define LP_I2C_ANA_MST_I2C0_CTRL_V 0x01FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CTRL_S 0
/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_BUSY (BIT(25))
#define LP_I2C_ANA_MST_I2C0_BUSY_M (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S)
#define LP_I2C_ANA_MST_I2C0_BUSY_V 0x00000001U
#define LP_I2C_ANA_MST_I2C0_BUSY_S 25
/** LP_I2C_ANA_MST_I2C0_CONF_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4)
/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CONF 0x00FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CONF_M (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S)
#define LP_I2C_ANA_MST_I2C0_CONF_V 0x00FFFFFFU
#define LP_I2C_ANA_MST_I2C0_CONF_S 0
/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7;
* reserved
*/
#define LP_I2C_ANA_MST_I2C0_STATUS 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_STATUS_M (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S)
#define LP_I2C_ANA_MST_I2C0_STATUS_V 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_STATUS_S 24
/** LP_I2C_ANA_MST_I2C0_DATA_REG register
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8)
/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_RDATA 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_RDATA_M (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S)
#define LP_I2C_ANA_MST_I2C0_RDATA_V 0x000000FFU
#define LP_I2C_ANA_MST_I2C0_RDATA_S 0
/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1;
* need_des
*/
#define LP_I2C_ANA_MST_I2C0_CLK_SEL 0x00000007U
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S)
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V 0x00000007U
#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S 8
/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1;
* need des
*/
#define LP_I2C_ANA_MST_I2C_MST_SEL (BIT(11))
#define LP_I2C_ANA_MST_I2C_MST_SEL_M (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S)
#define LP_I2C_ANA_MST_I2C_MST_SEL_V 0x00000001U
#define LP_I2C_ANA_MST_I2C_MST_SEL_S 11
/** LP_I2C_ANA_MST_ANA_CONF1_REG register
* need_des
*/
#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc)
/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_ANA_CONF1 0x00FFFFFFU
#define LP_I2C_ANA_MST_ANA_CONF1_M (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S)
#define LP_I2C_ANA_MST_ANA_CONF1_V 0x00FFFFFFU
#define LP_I2C_ANA_MST_ANA_CONF1_S 0
/** LP_I2C_ANA_MST_NOUSE_REG register
* need_des
*/
#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10)
/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFFU
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S)
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFFU
#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S 0
/** LP_I2C_ANA_MST_DEVICE_EN_REG register
* need_des
*/
#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14)
/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_DEVICE_EN 0x00000FFFU
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S)
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V 0x00000FFFU
#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S 0
/** LP_I2C_ANA_MST_DATE_REG register
* need_des
*/
#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc)
/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MAT_DATE 0x0FFFFFFFU
#define LP_I2C_ANA_MST_I2C_MAT_DATE_M (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S)
#define LP_I2C_ANA_MST_I2C_MAT_DATE_V 0x0FFFFFFFU
#define LP_I2C_ANA_MST_I2C_MAT_DATE_S 0
/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN (BIT(28))
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S)
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V 0x00000001U
#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S 28
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of i2c0_ctrl register
* need_des
*/
typedef union {
struct {
/** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
* need_des
*/
uint32_t i2c0_ctrl:25;
/** i2c0_busy : RO; bitpos: [25]; default: 0;
* need_des
*/
uint32_t i2c0_busy:1;
uint32_t reserved_26:6;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_ctrl_reg_t;
/** Type of i2c0_conf register
* need_des
*/
typedef union {
struct {
/** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
uint32_t i2c0_conf:24;
/** i2c0_status : RO; bitpos: [31:24]; default: 7;
* reserved
*/
uint32_t i2c0_status:8;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_conf_reg_t;
/** Type of i2c0_data register
* need_des
*/
typedef union {
struct {
/** i2c0_rdata : RO; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t i2c0_rdata:8;
/** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1;
* need_des
*/
uint32_t i2c0_clk_sel:3;
/** i2c_mst_sel : R/W; bitpos: [11]; default: 1;
* need des
*/
uint32_t i2c_mst_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2c_ana_mst_i2c0_data_reg_t;
/** Type of ana_conf1 register
* need_des
*/
typedef union {
struct {
/** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
* need_des
*/
uint32_t ana_conf1:24;
uint32_t reserved_24:8;
};
uint32_t val;
} lp_i2c_ana_mst_ana_conf1_reg_t;
/** Type of nouse register
* need_des
*/
typedef union {
struct {
/** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t i2c_mst_nouse:32;
};
uint32_t val;
} lp_i2c_ana_mst_nouse_reg_t;
/** Type of device_en register
* need_des
*/
typedef union {
struct {
/** i2c_device_en : R/W; bitpos: [11:0]; default: 0;
* need_des
*/
uint32_t i2c_device_en:12;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2c_ana_mst_device_en_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873;
* need_des
*/
uint32_t i2c_mat_date:28;
/** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t i2c_mat_clk_en:1;
uint32_t reserved_29:3;
};
uint32_t val;
} lp_i2c_ana_mst_date_reg_t;
typedef struct lp_i2c_ana_mst_dev_t {
volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data;
volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1;
volatile lp_i2c_ana_mst_nouse_reg_t nouse;
volatile lp_i2c_ana_mst_device_en_reg_t device_en;
uint32_t reserved_018[249];
volatile lp_i2c_ana_mst_date_reg_t date;
} lp_i2c_ana_mst_dev_t;
extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Timing registers */
/** Type of scl_low_period register
* Configures the low level width of the SCL
* Clock
*/
typedef union {
struct {
/** scl_low_period : R/W; bitpos: [8:0]; default: 0;
* Configures the low level width of the SCL Clock.
* Measurement unit: i2c_sclk.
*/
uint32_t scl_low_period:9;
uint32_t reserved_9:23;
};
uint32_t val;
} lp_i2c_scl_low_period_reg_t;
/** Type of sda_hold register
* Configures the hold time after a negative SCL edge.
*/
typedef union {
struct {
/** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
* Configures the time to hold the data after the falling edge of SCL.
* Measurement unit: i2c_sclk
*/
uint32_t sda_hold_time:9;
uint32_t reserved_9:23;
};
uint32_t val;
} lp_i2c_sda_hold_reg_t;
/** Type of sda_sample register
* Configures the sample time after a positive SCL edge.
*/
typedef union {
struct {
/** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
* Configures the sample time after a positive SCL edge.
* Measurement unit: i2c_sclk
*/
uint32_t sda_sample_time:9;
uint32_t reserved_9:23;
};
uint32_t val;
} lp_i2c_sda_sample_reg_t;
/** Type of scl_high_period register
* Configures the high level width of SCL
*/
typedef union {
struct {
/** scl_high_period : R/W; bitpos: [8:0]; default: 0;
* Configures for how long SCL remains high in master mode.
* Measurement unit: i2c_sclk
*/
uint32_t scl_high_period:9;
/** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
* Configures the SCL_FSM's waiting period for SCL high level in master mode.
* Measurement unit: i2c_sclk
*/
uint32_t scl_wait_high_period:7;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_i2c_scl_high_period_reg_t;
/** Type of scl_start_hold register
* Configures the delay between the SDA and SCL negative edge for a start condition
*/
typedef union {
struct {
/** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the falling edge of SDA and the falling edge of SCL for
* a START condition.
* Measurement unit: i2c_sclk.
*/
uint32_t scl_start_hold_time:9;
uint32_t reserved_9:23;
};
uint32_t val;
} lp_i2c_scl_start_hold_reg_t;
/** Type of scl_rstart_setup register
* Configures the delay between the positive
* edge of SCL and the negative edge of SDA
*/
typedef union {
struct {
/** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the positive edge of SCL and the negative edge of SDA
* for a RESTART condition.
* Measurement unit: i2c_sclk
*/
uint32_t scl_rstart_setup_time:9;
uint32_t reserved_9:23;
};
uint32_t val;
} lp_i2c_scl_rstart_setup_reg_t;
/** Type of scl_stop_hold register
* Configures the delay after the SCL clock
* edge for a stop condition
*/
typedef union {
struct {
/** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
* Configures the delay after the STOP condition.
* Measurement unit: i2c_sclk
*/
uint32_t scl_stop_hold_time:9;
uint32_t reserved_9:23;
};
uint32_t val;
} lp_i2c_scl_stop_hold_reg_t;
/** Type of scl_stop_setup register
* Configures the delay between the SDA and
* SCL positive edge for a stop condition
*/
typedef union {
struct {
/** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the rising edge of SCL and the rising edge of SDA.
* Measurement unit: i2c_sclk
*/
uint32_t scl_stop_setup_time:9;
uint32_t reserved_9:23;
};
uint32_t val;
} lp_i2c_scl_stop_setup_reg_t;
/** Type of scl_st_time_out register
* SCL status time out register
*/
typedef union {
struct {
/** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_FSM state unchanged period. It should be no
* more than 23.
* Measurement unit: i2c_sclk
*/
uint32_t scl_st_to_i2c:5;
uint32_t reserved_5:27;
};
uint32_t val;
} lp_i2c_scl_st_time_out_reg_t;
/** Type of scl_main_st_time_out register
* SCL main status time out register
*/
typedef union {
struct {
/** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
* no more than 23.
* Measurement unit: i2c_sclk
*/
uint32_t scl_main_st_to_i2c:5;
uint32_t reserved_5:27;
};
uint32_t val;
} lp_i2c_scl_main_st_time_out_reg_t;
/** Group: Configuration registers */
/** Type of ctr register
* Transmission setting
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** sample_scl_level : R/W; bitpos: [2]; default: 0;
* Configures the sample mode for SDA.
* 1: Sample SDA data on the SCL low level.
*
* 0: Sample SDA data on the SCL high level.
*/
uint32_t sample_scl_level:1;
/** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
* Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
* reached the threshold.
*/
uint32_t rx_full_ack_level:1;
uint32_t reserved_4:1;
/** trans_start : WT; bitpos: [5]; default: 0;
* Configures to start sending the data in txfifo for slave.
* 0: No effect
*
* 1: Start
*/
uint32_t trans_start:1;
/** tx_lsb_first : R/W; bitpos: [6]; default: 0;
* Configures to control the sending order for data needing to be sent.
* 1: send data from the least significant bit,
*
* 0: send data from the most significant bit.
*/
uint32_t tx_lsb_first:1;
/** rx_lsb_first : R/W; bitpos: [7]; default: 0;
* Configures to control the storage order for received data.
* 1: receive data from the least significant bit
*
* 0: receive data from the most significant bit.
*/
uint32_t rx_lsb_first:1;
/** clk_en : R/W; bitpos: [8]; default: 0;
* Configures whether to gate clock signal for registers.
*
* 0: Force clock on for registers
*
* 1: Support clock only when registers are read or written to by software.
*/
uint32_t clk_en:1;
/** arbitration_en : R/W; bitpos: [9]; default: 1;
* Configures to enable I2C bus arbitration detection.
* 0: No effect
*
* 1: Enable
*/
uint32_t arbitration_en:1;
/** fsm_rst : WT; bitpos: [10]; default: 0;
* Configures to reset the SCL_FSM.
* 0: No effect
*
* 1: Reset
*/
uint32_t fsm_rst:1;
/** conf_upgate : WT; bitpos: [11]; default: 0;
* Configures this bit for synchronization
* 0: No effect
*
* 1: Synchronize
*/
uint32_t conf_upgate:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_i2c_ctr_reg_t;
/** Type of to register
* Setting time out control for receiving data.
*/
typedef union {
struct {
/** time_out_value : R/W; bitpos: [4:0]; default: 16;
* Configures the timeout threshold period for SCL stucking at high or low level. The
* actual period is 2^(reg_time_out_value).
* Measurement unit: i2c_sclk.
*/
uint32_t time_out_value:5;
/** time_out_en : R/W; bitpos: [5]; default: 0;
* Configures to enable time out control.
* 0: No effect
*
* 1: Enable
*/
uint32_t time_out_en:1;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_i2c_to_reg_t;
/** Type of fifo_conf register
* FIFO configuration register.
*/
typedef union {
struct {
/** rxfifo_wm_thrhd : R/W; bitpos: [3:0]; default: 6;
* Configures the water mark threshold of RXFIFO in nonfifo access mode. When
* reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
* reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.
*/
uint32_t rxfifo_wm_thrhd:4;
uint32_t reserved_4:1;
/** txfifo_wm_thrhd : R/W; bitpos: [8:5]; default: 2;
* Configures the water mark threshold of TXFIFO in nonfifo access mode. When
* reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
* reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.
*/
uint32_t txfifo_wm_thrhd:4;
uint32_t reserved_9:1;
/** nonfifo_en : R/W; bitpos: [10]; default: 0;
* Configures to enable APB nonfifo access.
*/
uint32_t nonfifo_en:1;
uint32_t reserved_11:1;
/** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
* Configures to reset RXFIFO.
* 0: No effect
*
* 1: Reset
*/
uint32_t rx_fifo_rst:1;
/** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
* Configures to reset TXFIFO.
* 0: No effect
*
* 1: Reset
*/
uint32_t tx_fifo_rst:1;
/** fifo_prt_en : R/W; bitpos: [14]; default: 1;
* Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
* valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
* 0: No effect
*
* 1: Enable
*/
uint32_t fifo_prt_en:1;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_i2c_fifo_conf_reg_t;
/** Type of filter_cfg register
* SCL and SDA filter configuration register
*/
typedef union {
struct {
/** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
* Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
* input has smaller width than this register value, the I2C controller will ignore
* that pulse.
* Measurement unit: i2c_sclk
*/
uint32_t scl_filter_thres:4;
/** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
* Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
* input has smaller width than this register value, the I2C controller will ignore
* that pulse.
* Measurement unit: i2c_sclk
*/
uint32_t sda_filter_thres:4;
/** scl_filter_en : R/W; bitpos: [8]; default: 1;
* Configures to enable the filter function for SCL.
*/
uint32_t scl_filter_en:1;
/** sda_filter_en : R/W; bitpos: [9]; default: 1;
* Configures to enable the filter function for SDA.
*/
uint32_t sda_filter_en:1;
uint32_t reserved_10:22;
};
uint32_t val;
} lp_i2c_filter_cfg_reg_t;
/** Type of clk_conf register
* I2C CLK configuration register
*/
typedef union {
struct {
/** sclk_div_num : R/W; bitpos: [7:0]; default: 0;
* the integral part of the fractional divisor for i2c module
*/
uint32_t sclk_div_num:8;
/** sclk_div_a : R/W; bitpos: [13:8]; default: 0;
* the numerator of the fractional part of the fractional divisor for i2c module
*/
uint32_t sclk_div_a:6;
/** sclk_div_b : R/W; bitpos: [19:14]; default: 0;
* the denominator of the fractional part of the fractional divisor for i2c module
*/
uint32_t sclk_div_b:6;
/** sclk_sel : R/W; bitpos: [20]; default: 0;
* The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
*/
uint32_t sclk_sel:1;
/** sclk_active : R/W; bitpos: [21]; default: 1;
* The clock switch for i2c module
*/
uint32_t sclk_active:1;
uint32_t reserved_22:10;
};
uint32_t val;
} lp_i2c_clk_conf_reg_t;
/** Type of scl_sp_conf register
* Power configuration register
*/
typedef union {
struct {
/** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
* When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
* equals to reg_scl_rst_slv_num[4:0].
*/
uint32_t scl_rst_slv_en:1;
/** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
* Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
* equals to reg_scl_rst_slv_num[4:0].
*/
uint32_t scl_rst_slv_num:5;
/** scl_pd_en : R/W; bitpos: [6]; default: 0;
* Configure the pulses of SCL generated in I2C master mode.
* Valid when reg_scl_rst_slv_en is 1.
* Measurement unit: i2c_sclk
*/
uint32_t scl_pd_en:1;
/** sda_pd_en : R/W; bitpos: [7]; default: 0;
* Configures to power down the I2C output SCL line.
* 0: Not power down.
*
* 1: Power down.
* Valid only when reg_scl_force_out is 1.
*/
uint32_t sda_pd_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_i2c_scl_sp_conf_reg_t;
/** Group: Status registers */
/** Type of sr register
* Describe I2C work status.
*/
typedef union {
struct {
/** resp_rec : RO; bitpos: [0]; default: 0;
* Represents the received ACK value in master mode or slave mode.
* 0: ACK,
*
* 1: NACK.
*/
uint32_t resp_rec:1;
uint32_t reserved_1:2;
/** arb_lost : RO; bitpos: [3]; default: 0;
* Represents whether the I2C controller loses control of SCL line.
* 0: No arbitration lost
*
* 1: Arbitration lost
*/
uint32_t arb_lost:1;
/** bus_busy : RO; bitpos: [4]; default: 0;
* Represents the I2C bus state.
* 1: The I2C bus is busy transferring data,
*
* 0: The I2C bus is in idle state.
*/
uint32_t bus_busy:1;
uint32_t reserved_5:3;
/** rxfifo_cnt : RO; bitpos: [12:8]; default: 0;
* Represents the number of data bytes to be sent.
*/
uint32_t rxfifo_cnt:5;
uint32_t reserved_13:5;
/** txfifo_cnt : RO; bitpos: [22:18]; default: 0;
* Represents the number of data bytes received in RAM.
*/
uint32_t txfifo_cnt:5;
uint32_t reserved_23:1;
/** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
* Represents the states of the I2C module state machine.
* 0: Idle,
*
* 1: Address shift,
*
* 2: ACK address,
*
* 3: Rx data,
*
* 4: Tx data,
*
* 5: Send ACK,
*
* 6: Wait ACK
*/
uint32_t scl_main_state_last:3;
uint32_t reserved_27:1;
/** scl_state_last : RO; bitpos: [30:28]; default: 0;
* Represents the states of the state machine used to produce SCL.
* 0: Idle,
*
* 1: Start,
*
* 2: Negative edge,
*
* 3: Low,
*
* 4: Positive edge,
*
* 5: High,
*
* 6: Stop
*/
uint32_t scl_state_last:3;
uint32_t reserved_31:1;
};
uint32_t val;
} lp_i2c_sr_reg_t;
/** Type of fifo_st register
* FIFO status register.
*/
typedef union {
struct {
/** rxfifo_raddr : RO; bitpos: [3:0]; default: 0;
* Represents the offset address of the APB reading from RXFIFO
*/
uint32_t rxfifo_raddr:4;
uint32_t reserved_4:1;
/** rxfifo_waddr : RO; bitpos: [8:5]; default: 0;
* Represents the offset address of i2c module receiving data and writing to RXFIFO.
*/
uint32_t rxfifo_waddr:4;
uint32_t reserved_9:1;
/** txfifo_raddr : RO; bitpos: [13:10]; default: 0;
* Represents the offset address of i2c module reading from TXFIFO.
*/
uint32_t txfifo_raddr:4;
uint32_t reserved_14:1;
/** txfifo_waddr : RO; bitpos: [18:15]; default: 0;
* Represents the offset address of APB bus writing to TXFIFO.
*/
uint32_t txfifo_waddr:4;
uint32_t reserved_19:13;
};
uint32_t val;
} lp_i2c_fifo_st_reg_t;
/** Type of data register
* Rx FIFO read data.
*/
typedef union {
struct {
/** fifo_rdata : RO; bitpos: [7:0]; default: 0;
* Represents the value of RXFIFO read data.
*/
uint32_t fifo_rdata:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_i2c_data_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
*/
uint32_t rxfifo_wm_int_raw:1;
/** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
* The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
*/
uint32_t txfifo_wm_int_raw:1;
/** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
*/
uint32_t rxfifo_ovf_int_raw:1;
/** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
* The raw interrupt status of the I2C_END_DETECT_INT interrupt.
*/
uint32_t end_detect_int_raw:1;
/** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
* The raw interrupt status of the I2C_END_DETECT_INT interrupt.
*/
uint32_t byte_trans_done_int_raw:1;
/** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
* The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
*/
uint32_t arbitration_lost_int_raw:1;
/** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
* The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
*/
uint32_t mst_txfifo_udf_int_raw:1;
/** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
* The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
*/
uint32_t trans_complete_int_raw:1;
/** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
* The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
*/
uint32_t time_out_int_raw:1;
/** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
* The raw interrupt status of the I2C_TRANS_START_INT interrupt.
*/
uint32_t trans_start_int_raw:1;
/** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
* The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
*/
uint32_t nack_int_raw:1;
/** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
* The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
*/
uint32_t txfifo_ovf_int_raw:1;
/** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
* The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt.
*/
uint32_t rxfifo_udf_int_raw:1;
/** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
* The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
*/
uint32_t scl_st_to_int_raw:1;
/** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
* The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
*/
uint32_t scl_main_st_to_int_raw:1;
/** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
* The raw interrupt status of I2C_DET_START_INT interrupt.
*/
uint32_t det_start_int_raw:1;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_i2c_int_raw_reg_t;
/** Type of int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
*/
uint32_t rxfifo_wm_int_clr:1;
/** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
*/
uint32_t txfifo_wm_int_clr:1;
/** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
*/
uint32_t rxfifo_ovf_int_clr:1;
/** end_detect_int_clr : WT; bitpos: [3]; default: 0;
* Write 1 to clear the I2C_END_DETECT_INT interrupt.
*/
uint32_t end_detect_int_clr:1;
/** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
* Write 1 to clear the I2C_END_DETECT_INT interrupt.
*/
uint32_t byte_trans_done_int_clr:1;
/** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
* Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
*/
uint32_t arbitration_lost_int_clr:1;
/** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
* Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
*/
uint32_t mst_txfifo_udf_int_clr:1;
/** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
* Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
*/
uint32_t trans_complete_int_clr:1;
/** time_out_int_clr : WT; bitpos: [8]; default: 0;
* Write 1 to clear the I2C_TIME_OUT_INT interrupt.
*/
uint32_t time_out_int_clr:1;
/** trans_start_int_clr : WT; bitpos: [9]; default: 0;
* Write 1 to clear the I2C_TRANS_START_INT interrupt.
*/
uint32_t trans_start_int_clr:1;
/** nack_int_clr : WT; bitpos: [10]; default: 0;
* Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
*/
uint32_t nack_int_clr:1;
/** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
* Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
*/
uint32_t txfifo_ovf_int_clr:1;
/** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
* Write 1 to clear I2C_RXFIFO_UDF_INT interrupt.
*/
uint32_t rxfifo_udf_int_clr:1;
/** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
* Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
*/
uint32_t scl_st_to_int_clr:1;
/** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
* Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
*/
uint32_t scl_main_st_to_int_clr:1;
/** det_start_int_clr : WT; bitpos: [15]; default: 0;
* Write 1 to clear I2C_DET_START_INT interrupt.
*/
uint32_t det_start_int_clr:1;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_i2c_int_clr_reg_t;
/** Type of int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to anable I2C_RXFIFO_WM_INT interrupt.
*/
uint32_t rxfifo_wm_int_ena:1;
/** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to anable I2C_TXFIFO_WM_INT interrupt.
*/
uint32_t txfifo_wm_int_ena:1;
/** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to anable I2C_RXFIFO_OVF_INT interrupt.
*/
uint32_t rxfifo_ovf_int_ena:1;
/** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
* Write 1 to anable the I2C_END_DETECT_INT interrupt.
*/
uint32_t end_detect_int_ena:1;
/** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
* Write 1 to anable the I2C_END_DETECT_INT interrupt.
*/
uint32_t byte_trans_done_int_ena:1;
/** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
* Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt.
*/
uint32_t arbitration_lost_int_ena:1;
/** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
* Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt.
*/
uint32_t mst_txfifo_udf_int_ena:1;
/** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
* Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt.
*/
uint32_t trans_complete_int_ena:1;
/** time_out_int_ena : R/W; bitpos: [8]; default: 0;
* Write 1 to anable the I2C_TIME_OUT_INT interrupt.
*/
uint32_t time_out_int_ena:1;
/** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
* Write 1 to anable the I2C_TRANS_START_INT interrupt.
*/
uint32_t trans_start_int_ena:1;
/** nack_int_ena : R/W; bitpos: [10]; default: 0;
* Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt.
*/
uint32_t nack_int_ena:1;
/** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
* Write 1 to anable I2C_TXFIFO_OVF_INT interrupt.
*/
uint32_t txfifo_ovf_int_ena:1;
/** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
* Write 1 to anable I2C_RXFIFO_UDF_INT interrupt.
*/
uint32_t rxfifo_udf_int_ena:1;
/** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
* Write 1 to anable I2C_SCL_ST_TO_INT interrupt.
*/
uint32_t scl_st_to_int_ena:1;
/** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
* Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt.
*/
uint32_t scl_main_st_to_int_ena:1;
/** det_start_int_ena : R/W; bitpos: [15]; default: 0;
* Write 1 to anable I2C_DET_START_INT interrupt.
*/
uint32_t det_start_int_ena:1;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_i2c_int_ena_reg_t;
/** Type of int_status register
* Status of captured I2C communication events
*/
typedef union {
struct {
/** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
*/
uint32_t rxfifo_wm_int_st:1;
/** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
*/
uint32_t txfifo_wm_int_st:1;
/** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
*/
uint32_t rxfifo_ovf_int_st:1;
/** end_detect_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
*/
uint32_t end_detect_int_st:1;
/** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
* The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
*/
uint32_t byte_trans_done_int_st:1;
/** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
* The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
*/
uint32_t arbitration_lost_int_st:1;
/** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
* The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
*/
uint32_t mst_txfifo_udf_int_st:1;
/** trans_complete_int_st : RO; bitpos: [7]; default: 0;
* The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
*/
uint32_t trans_complete_int_st:1;
/** time_out_int_st : RO; bitpos: [8]; default: 0;
* The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
*/
uint32_t time_out_int_st:1;
/** trans_start_int_st : RO; bitpos: [9]; default: 0;
* The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
*/
uint32_t trans_start_int_st:1;
/** nack_int_st : RO; bitpos: [10]; default: 0;
* The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
*/
uint32_t nack_int_st:1;
/** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
* The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
*/
uint32_t txfifo_ovf_int_st:1;
/** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
* The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt.
*/
uint32_t rxfifo_udf_int_st:1;
/** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
* The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
*/
uint32_t scl_st_to_int_st:1;
/** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
* The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
*/
uint32_t scl_main_st_to_int_st:1;
/** det_start_int_st : RO; bitpos: [15]; default: 0;
* The masked interrupt status status of I2C_DET_START_INT interrupt.
*/
uint32_t det_start_int_st:1;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_i2c_int_status_reg_t;
/** Group: Command registers */
/** Type of comd register
* I2C command register n
*/
typedef union {
struct {
/** command : R/W; bitpos: [13:0]; default: 0;
* Configures command 0. It consists of three parts:
* op_code is the command,
* 0: RSTART,
* 1: WRITE,
* 2: READ,
* 3: STOP,
* 4: END.
*
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more information.
*/
uint32_t command:14;
uint32_t reserved_14:17;
/** command_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command n is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command_done:1;
};
uint32_t val;
} lp_i2c_comd_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 35656003;
* Version control register.
*/
uint32_t date:32;
};
uint32_t val;
} lp_i2c_date_reg_t;
/** Group: Address register */
/** Type of txfifo_start_addr register
* I2C TXFIFO base address register
*/
typedef union {
struct {
/** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
* Represents the I2C txfifo first address.
*/
uint32_t txfifo_start_addr:32;
};
uint32_t val;
} lp_i2c_txfifo_start_addr_reg_t;
/** Type of rxfifo_start_addr register
* I2C RXFIFO base address register
*/
typedef union {
struct {
/** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
* Represents the I2C rxfifo first address.
*/
uint32_t rxfifo_start_addr:32;
};
uint32_t val;
} lp_i2c_rxfifo_start_addr_reg_t;
typedef struct lp_i2c_dev_t {
volatile lp_i2c_scl_low_period_reg_t scl_low_period;
volatile lp_i2c_ctr_reg_t ctr;
volatile lp_i2c_sr_reg_t sr;
volatile lp_i2c_to_reg_t to;
uint32_t reserved_010;
volatile lp_i2c_fifo_st_reg_t fifo_st;
volatile lp_i2c_fifo_conf_reg_t fifo_conf;
volatile lp_i2c_data_reg_t data;
volatile lp_i2c_int_raw_reg_t int_raw;
volatile lp_i2c_int_clr_reg_t int_clr;
volatile lp_i2c_int_ena_reg_t int_ena;
volatile lp_i2c_int_status_reg_t int_status;
volatile lp_i2c_sda_hold_reg_t sda_hold;
volatile lp_i2c_sda_sample_reg_t sda_sample;
volatile lp_i2c_scl_high_period_reg_t scl_high_period;
uint32_t reserved_03c;
volatile lp_i2c_scl_start_hold_reg_t scl_start_hold;
volatile lp_i2c_scl_rstart_setup_reg_t scl_rstart_setup;
volatile lp_i2c_scl_stop_hold_reg_t scl_stop_hold;
volatile lp_i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile lp_i2c_filter_cfg_reg_t filter_cfg;
volatile lp_i2c_clk_conf_reg_t clk_conf;
volatile lp_i2c_comd_reg_t comd[8];
volatile lp_i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile lp_i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile lp_i2c_scl_sp_conf_reg_t scl_sp_conf;
uint32_t reserved_084[29];
volatile lp_i2c_date_reg_t date;
uint32_t reserved_0fc;
volatile lp_i2c_txfifo_start_addr_reg_t txfifo_start_addr;
uint32_t reserved_104[31];
volatile lp_i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
} lp_i2c_dev_t;
extern lp_i2c_dev_t LP_I2C;
#ifndef __cplusplus
_Static_assert(sizeof(lp_i2c_dev_t) == 0x184, "Invalid size of lp_i2c_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/lp_io_reg.h
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components/soc/esp32c5/beta3/include/soc/lp_io_struct.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of out_data register
* need des
*/
typedef union {
struct {
/** lp_gpio_out_data : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t lp_gpio_out_data:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_reg_t;
/** Type of out_data_w1ts register
* need des
*/
typedef union {
struct {
/** lp_gpio_out_data_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t lp_gpio_out_data_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_w1ts_reg_t;
/** Type of out_data_w1tc register
* need des
*/
typedef union {
struct {
/** lp_gpio_out_data_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t lp_gpio_out_data_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_w1tc_reg_t;
/** Type of out_enable register
* need des
*/
typedef union {
struct {
/** lp_gpio_enable : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t lp_gpio_enable:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_reg_t;
/** Type of out_enable_w1ts register
* need des
*/
typedef union {
struct {
/** lp_gpio_enable_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t lp_gpio_enable_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_w1ts_reg_t;
/** Type of out_enable_w1tc register
* need des
*/
typedef union {
struct {
/** lp_gpio_enable_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t lp_gpio_enable_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_w1tc_reg_t;
/** Type of status register
* need des
*/
typedef union {
struct {
/** lp_gpio_status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t lp_gpio_status_interrupt:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_reg_t;
/** Type of status_w1ts register
* need des
*/
typedef union {
struct {
/** lp_gpio_status_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t lp_gpio_status_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_w1ts_reg_t;
/** Type of status_w1tc register
* need des
*/
typedef union {
struct {
/** lp_gpio_status_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t lp_gpio_status_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_w1tc_reg_t;
/** Type of in register
* need des
*/
typedef union {
struct {
/** lp_gpio_in_data_next : RO; bitpos: [7:0]; default: 0;
* need des
*/
uint32_t lp_gpio_in_data_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_in_reg_t;
/** Type of pin n register
* need des
*/
typedef union {
struct {
/** lp_gpio_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio_sync_bypass:2;
/** lp_gpio_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio_pad_driver:1;
/** lp_gpio_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio_int_type:3;
/** lp_gpio_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio_wakeup_enable:1;
/** lp_gpio_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin_reg_t;
/** Type of gpio n register
* need des
*/
typedef union {
struct {
/** lp_gpio_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio_mcu_oe:1;
/** lp_gpio_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio_slp_sel:1;
/** lp_gpio_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio_mcu_wpd:1;
/** lp_gpio_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio_mcu_wpu:1;
/** lp_gpio_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio_mcu_ie:1;
/** lp_gpio_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio_mcu_drv:2;
/** lp_gpio_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio_fun_wpd:1;
/** lp_gpio_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio_fun_wpu:1;
/** lp_gpio_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio_fun_ie:1;
/** lp_gpio_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio_fun_drv:2;
/** lp_gpio_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio_reg_t;
/** Type of gpio1 register
* need des
*/
typedef union {
struct {
/** lp_gpio1_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_oe:1;
/** lp_gpio1_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio1_slp_sel:1;
/** lp_gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_wpd:1;
/** lp_gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_wpu:1;
/** lp_gpio1_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_ie:1;
/** lp_gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_drv:2;
/** lp_gpio1_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio1_fun_wpd:1;
/** lp_gpio1_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio1_fun_wpu:1;
/** lp_gpio1_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio1_fun_ie:1;
/** lp_gpio1_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio1_fun_drv:2;
/** lp_gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio1_reg_t;
/** Type of gpio2 register
* need des
*/
typedef union {
struct {
/** lp_gpio2_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_oe:1;
/** lp_gpio2_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio2_slp_sel:1;
/** lp_gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_wpd:1;
/** lp_gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_wpu:1;
/** lp_gpio2_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_ie:1;
/** lp_gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_drv:2;
/** lp_gpio2_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio2_fun_wpd:1;
/** lp_gpio2_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio2_fun_wpu:1;
/** lp_gpio2_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio2_fun_ie:1;
/** lp_gpio2_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio2_fun_drv:2;
/** lp_gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio2_reg_t;
/** Type of gpio3 register
* need des
*/
typedef union {
struct {
/** lp_gpio3_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_oe:1;
/** lp_gpio3_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio3_slp_sel:1;
/** lp_gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_wpd:1;
/** lp_gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_wpu:1;
/** lp_gpio3_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_ie:1;
/** lp_gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_drv:2;
/** lp_gpio3_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio3_fun_wpd:1;
/** lp_gpio3_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio3_fun_wpu:1;
/** lp_gpio3_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio3_fun_ie:1;
/** lp_gpio3_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio3_fun_drv:2;
/** lp_gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio3_reg_t;
/** Type of gpio4 register
* need des
*/
typedef union {
struct {
/** lp_gpio4_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_oe:1;
/** lp_gpio4_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio4_slp_sel:1;
/** lp_gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_wpd:1;
/** lp_gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_wpu:1;
/** lp_gpio4_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_ie:1;
/** lp_gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_drv:2;
/** lp_gpio4_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio4_fun_wpd:1;
/** lp_gpio4_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio4_fun_wpu:1;
/** lp_gpio4_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio4_fun_ie:1;
/** lp_gpio4_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio4_fun_drv:2;
/** lp_gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio4_reg_t;
/** Type of gpio5 register
* need des
*/
typedef union {
struct {
/** lp_gpio5_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_oe:1;
/** lp_gpio5_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio5_slp_sel:1;
/** lp_gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_wpd:1;
/** lp_gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_wpu:1;
/** lp_gpio5_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_ie:1;
/** lp_gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_drv:2;
/** lp_gpio5_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio5_fun_wpd:1;
/** lp_gpio5_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio5_fun_wpu:1;
/** lp_gpio5_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio5_fun_ie:1;
/** lp_gpio5_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio5_fun_drv:2;
/** lp_gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio5_reg_t;
/** Type of gpio6 register
* need des
*/
typedef union {
struct {
/** lp_gpio6_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_oe:1;
/** lp_gpio6_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio6_slp_sel:1;
/** lp_gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_wpd:1;
/** lp_gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_wpu:1;
/** lp_gpio6_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_ie:1;
/** lp_gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_drv:2;
/** lp_gpio6_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio6_fun_wpd:1;
/** lp_gpio6_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio6_fun_wpu:1;
/** lp_gpio6_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio6_fun_ie:1;
/** lp_gpio6_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio6_fun_drv:2;
/** lp_gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio6_reg_t;
/** Type of gpio7 register
* need des
*/
typedef union {
struct {
/** lp_gpio7_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_oe:1;
/** lp_gpio7_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio7_slp_sel:1;
/** lp_gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_wpd:1;
/** lp_gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_wpu:1;
/** lp_gpio7_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_ie:1;
/** lp_gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_drv:2;
/** lp_gpio7_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio7_fun_wpd:1;
/** lp_gpio7_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio7_fun_wpu:1;
/** lp_gpio7_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio7_fun_ie:1;
/** lp_gpio7_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio7_fun_drv:2;
/** lp_gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio7_reg_t;
/** Type of status_interrupt register
* need des
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
* need des
*/
uint32_t status_interrupt_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_interrupt_reg_t;
/** Type of debug_sel0 register
* need des
*/
typedef union {
struct {
/** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t lp_debug_sel0:7;
/** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0;
* need des
*/
uint32_t lp_debug_sel1:7;
/** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0;
* need des
*/
uint32_t lp_debug_sel2:7;
/** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0;
* need des
*/
uint32_t lp_debug_sel3:7;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_io_debug_sel0_reg_t;
/** Type of debug_sel1 register
* need des
*/
typedef union {
struct {
/** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t lp_debug_sel4:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_io_debug_sel1_reg_t;
/** Type of lpi2c register
* need des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1;
* need des
*/
uint32_t lp_i2c_sda_ie:1;
/** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1;
* need des
*/
uint32_t lp_i2c_scl_ie:1;
};
uint32_t val;
} lp_io_lpi2c_reg_t;
/** Type of date register
* need des
*/
typedef union {
struct {
/** lp_io_date : R/W; bitpos: [30:0]; default: 35660032;
* need des
*/
uint32_t lp_io_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_io_date_reg_t;
typedef struct lp_io_dev_t {
volatile lp_io_out_data_reg_t out_data;
volatile lp_io_out_data_w1ts_reg_t out_data_w1ts;
volatile lp_io_out_data_w1tc_reg_t out_data_w1tc;
volatile lp_io_out_enable_reg_t out_enable;
volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts;
volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc;
volatile lp_io_status_reg_t status;
volatile lp_io_status_w1ts_reg_t status_w1ts;
volatile lp_io_status_w1tc_reg_t status_w1tc;
volatile lp_io_in_reg_t in;
volatile lp_io_pin_reg_t pin[8];
volatile lp_io_gpio_reg_t gpio[8];
volatile lp_io_status_interrupt_reg_t status_interrupt;
volatile lp_io_debug_sel0_reg_t debug_sel0;
volatile lp_io_debug_sel1_reg_t debug_sel1;
volatile lp_io_lpi2c_reg_t lpi2c;
uint32_t reserved_078[225];
volatile lp_io_date_reg_t date;
} lp_io_dev_t;
extern lp_io_dev_t LP_IO;
#ifndef __cplusplus
_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

72
components/soc/esp32c5/beta3/include/soc/lp_tee_reg.h
View File

@ -1,72 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TEE_M0_MODE_CTRL_REG register
* Tee mode control register
*/
#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define LP_TEE_M0_MODE 0x00000003U
#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
#define LP_TEE_M0_MODE_V 0x00000003U
#define LP_TEE_M0_MODE_S 0
/** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
*/
#define LP_TEE_M0_LOCK (BIT(2))
#define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S)
#define LP_TEE_M0_LOCK_V 0x00000001U
#define LP_TEE_M0_LOCK_S 2
/** LP_TEE_CLOCK_GATE_REG register
* Clock gating register
*/
#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4)
/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_TEE_CLK_EN (BIT(0))
#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
#define LP_TEE_CLK_EN_V 0x00000001U
#define LP_TEE_CLK_EN_S 0
/** LP_TEE_FORCE_ACC_HP_REG register
* need_des
*/
#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0))
#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U
#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0
/** LP_TEE_DATE_REG register
* Version register
*/
#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
* reg_tee_date
*/
#define LP_TEE_DATE_REG 0x0FFFFFFFU
#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S)
#define LP_TEE_DATE_REG_V 0x0FFFFFFFU
#define LP_TEE_DATE_REG_S 0
#ifdef __cplusplus
}
#endif

99
components/soc/esp32c5/beta3/include/soc/lp_tee_struct.h
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@ -1,99 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 3;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m0_mode:2;
/** m0_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
*/
uint32_t m0_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} lp_tee_m0_mode_ctrl_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_clock_gate_reg_t;
/** Group: configure_register */
/** Type of force_acc_hp register
* need_des
*/
typedef union {
struct {
/** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t force_acc_hpmem_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_force_acc_hp_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date_reg : R/W; bitpos: [27:0]; default: 35725664;
* reg_tee_date
*/
uint32_t date_reg:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_tee_date_reg_t;
typedef struct lp_tee_dev_t {
volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
volatile lp_tee_clock_gate_reg_t clock_gate;
uint32_t reserved_008[34];
volatile lp_tee_force_acc_hp_reg_t force_acc_hp;
uint32_t reserved_094[26];
volatile lp_tee_date_reg_t date;
} lp_tee_dev_t;
extern lp_tee_dev_t LP_TEE;
#ifndef __cplusplus
_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

342
components/soc/esp32c5/beta3/include/soc/lp_timer_reg.h
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@ -1,342 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TIMER_TAR0_LOW_REG register
* need_des
*/
#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0
/** LP_TIMER_TAR0_HIGH_REG register
* need_des
*/
#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31
/** LP_TIMER_TAR1_LOW_REG register
* need_des
*/
#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8)
/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0
/** LP_TIMER_TAR1_HIGH_REG register
* need_des
*/
#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31
/** LP_TIMER_UPDATE_REG register
* need_des
*/
#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28))
#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_UPDATE_S 28
/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29
/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30
/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31
/** LP_TIMER_MAIN_BUF0_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0
/** LP_TIMER_MAIN_BUF0_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
/** LP_TIMER_MAIN_BUF1_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0
/** LP_TIMER_MAIN_BUF1_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
/** LP_TIMER_MAIN_OVERFLOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31))
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S)
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31
/** LP_TIMER_INT_RAW_REG register
* need_des
*/
#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_RAW (BIT(30))
#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U
#define LP_TIMER_OVERFLOW_RAW_S 30
/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31
/** LP_TIMER_INT_ST_REG register
* need_des
*/
#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ST (BIT(30))
#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
#define LP_TIMER_OVERFLOW_ST_V 0x00000001U
#define LP_TIMER_OVERFLOW_ST_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31
/** LP_TIMER_INT_ENA_REG register
* need_des
*/
#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30)
/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ENA (BIT(30))
#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U
#define LP_TIMER_OVERFLOW_ENA_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31
/** LP_TIMER_INT_CLR_REG register
* need_des
*/
#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34)
/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_CLR (BIT(30))
#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U
#define LP_TIMER_OVERFLOW_CLR_S 30
/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31
/** LP_TIMER_LP_INT_RAW_REG register
* need_des
*/
#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31
/** LP_TIMER_LP_INT_ST_REG register
* need_des
*/
#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31
/** LP_TIMER_LP_INT_ENA_REG register
* need_des
*/
#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31
/** LP_TIMER_LP_INT_CLR_REG register
* need_des
*/
#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31
/** LP_TIMER_DATE_REG register
* need_des
*/
#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc)
/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
#define LP_TIMER_DATE 0x7FFFFFFFU
#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
#define LP_TIMER_DATE_V 0x7FFFFFFFU
#define LP_TIMER_DATE_S 0
/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_CLK_EN (BIT(31))
#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S)
#define LP_TIMER_CLK_EN_V 0x00000001U
#define LP_TIMER_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

335
components/soc/esp32c5/beta3/include/soc/lp_timer_struct.h
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@ -1,335 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of tar_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low:32;
};
uint32_t val;
} lp_timer_tar_low_reg_t;
/** Type of tar_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high:16;
uint32_t reserved_16:15;
/** main_timer_tar_en : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en:1;
};
uint32_t val;
} lp_timer_tar_high_reg_t;
/** Type of update register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** main_timer_update : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t main_timer_update:1;
/** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t main_timer_xtal_off:1;
/** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_sys_stall:1;
/** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_sys_rst:1;
};
uint32_t val;
} lp_timer_update_reg_t;
/** Type of main_buf_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf_low:32;
};
uint32_t val;
} lp_timer_main_buf_low_reg_t;
/** Type of main_buf_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf_high_reg_t;
/** Type of main_buf1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_low:32;
};
uint32_t val;
} lp_timer_main_buf1_low_reg_t;
/** Type of main_buf1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf1_high_reg_t;
/** Type of main_overflow register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_alarm_load:1;
};
uint32_t val;
} lp_timer_main_overflow_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_raw:1;
/** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_raw:1;
};
uint32_t val;
} lp_timer_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_st:1;
/** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_st:1;
};
uint32_t val;
} lp_timer_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_ena:1;
/** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_ena:1;
};
uint32_t val;
} lp_timer_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_clr:1;
/** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_clr:1;
};
uint32_t val;
} lp_timer_int_clr_reg_t;
/** Type of lp_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_raw:1;
/** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_raw:1;
};
uint32_t val;
} lp_timer_lp_int_raw_reg_t;
/** Type of lp_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_st:1;
/** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_st:1;
};
uint32_t val;
} lp_timer_lp_int_st_reg_t;
/** Type of lp_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_ena:1;
/** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_ena:1;
};
uint32_t val;
} lp_timer_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_clr:1;
/** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_clr:1;
};
uint32_t val;
} lp_timer_lp_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_timer_date_reg_t;
typedef struct {
volatile lp_timer_tar_low_reg_t lo;
volatile lp_timer_tar_high_reg_t hi;
} lp_timer_target_reg_t;
typedef struct {
volatile lp_timer_main_buf_low_reg_t lo;
volatile lp_timer_main_buf_high_reg_t hi;
} lp_timer_counter_reg_t;
typedef struct lp_timer_dev_t {
volatile lp_timer_target_reg_t target[2];
volatile lp_timer_update_reg_t update;
volatile lp_timer_counter_reg_t counter[2];
volatile lp_timer_main_overflow_reg_t main_overflow;
volatile lp_timer_int_raw_reg_t int_raw;
volatile lp_timer_int_st_reg_t int_st;
volatile lp_timer_int_ena_reg_t int_ena;
volatile lp_timer_int_clr_reg_t int_clr;
volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
volatile lp_timer_lp_int_st_reg_t lp_int_st;
volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_048[237];
volatile lp_timer_date_reg_t date;
} lp_timer_dev_t;
extern lp_timer_dev_t LP_TIMER;
#ifndef __cplusplus
_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/lp_uart_reg.h
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components/soc/esp32c5/beta3/include/soc/lp_uart_struct.h
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components/soc/esp32c5/beta3/include/soc/lp_wdt_reg.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_WDT_CONFIG0_REG register
* need_des
*/
#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
* need_des
*/
#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9))
#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
#define LP_WDT_WDT_PAUSE_IN_SLP_S 9
/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
* need_des
*/
#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10))
#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_APPCPU_RESET_EN_S 10
/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
* need_des
*/
#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11))
#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
#define LP_WDT_WDT_PROCPU_RESET_EN_S 11
/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
* need_des
*/
#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12
/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
* need_des
*/
#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
* need_des
*/
#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
* need_des
*/
#define LP_WDT_WDT_STG3 0x00000007U
#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
#define LP_WDT_WDT_STG3_V 0x00000007U
#define LP_WDT_WDT_STG3_S 19
/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
* need_des
*/
#define LP_WDT_WDT_STG2 0x00000007U
#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
#define LP_WDT_WDT_STG2_V 0x00000007U
#define LP_WDT_WDT_STG2_S 22
/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
* need_des
*/
#define LP_WDT_WDT_STG1 0x00000007U
#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
#define LP_WDT_WDT_STG1_V 0x00000007U
#define LP_WDT_WDT_STG1_S 25
/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
#define LP_WDT_WDT_STG0 0x00000007U
#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
#define LP_WDT_WDT_STG0_V 0x00000007U
#define LP_WDT_WDT_STG0_S 28
/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_WDT_EN (BIT(31))
#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
#define LP_WDT_WDT_EN_V 0x00000001U
#define LP_WDT_WDT_EN_S 31
/** LP_WDT_CONFIG1_REG register
* need_des
*/
#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
* need_des
*/
#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG0_HOLD_S 0
/** LP_WDT_CONFIG2_REG register
* need_des
*/
#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
* need_des
*/
#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG1_HOLD_S 0
/** LP_WDT_CONFIG3_REG register
* need_des
*/
#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG2_HOLD_S 0
/** LP_WDT_CONFIG4_REG register
* need_des
*/
#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG3_HOLD_S 0
/** LP_WDT_FEED_REG register
* need_des
*/
#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_RTC_WDT_FEED (BIT(31))
#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S)
#define LP_WDT_RTC_WDT_FEED_V 0x00000001U
#define LP_WDT_RTC_WDT_FEED_S 31
/** LP_WDT_WPROTECT_REG register
* need_des
*/
#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_WDT_WDT_WKEY 0xFFFFFFFFU
#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU
#define LP_WDT_WDT_WKEY_S 0
/** LP_WDT_SWD_CONFIG_REG register
* need_des
*/
#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
* need_des
*/
#define LP_WDT_SWD_RESET_FLAG (BIT(0))
#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U
#define LP_WDT_SWD_RESET_FLAG_S 0
/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
* need_des
*/
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18))
#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
#define LP_WDT_SWD_AUTO_FEED_EN_S 18
/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
* need_des
*/
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19))
#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
#define LP_WDT_SWD_RST_FLAG_CLR_S 19
/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
* need_des
*/
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_S 20
/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SWD_DISABLE (BIT(30))
#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
#define LP_WDT_SWD_DISABLE_V 0x00000001U
#define LP_WDT_SWD_DISABLE_S 30
/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_SWD_FEED (BIT(31))
#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
#define LP_WDT_SWD_FEED_V 0x00000001U
#define LP_WDT_SWD_FEED_S 31
/** LP_WDT_SWD_WPROTECT_REG register
* need_des
*/
#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_WDT_SWD_WKEY 0xFFFFFFFFU
#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU
#define LP_WDT_SWD_WKEY_S 0
/** LP_WDT_INT_RAW_REG register
* need_des
*/
#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30))
#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_RAW_S 30
/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_LP_WDT_INT_RAW (BIT(31))
#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U
#define LP_WDT_LP_WDT_INT_RAW_S 31
/** LP_WDT_INT_ST_REG register
* need_des
*/
#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SUPER_WDT_INT_ST (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ST_S 30
/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_LP_WDT_INT_ST (BIT(31))
#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U
#define LP_WDT_LP_WDT_INT_ST_S 31
/** LP_WDT_INT_ENA_REG register
* need_des
*/
#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ENA_S 30
/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_LP_WDT_INT_ENA (BIT(31))
#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U
#define LP_WDT_LP_WDT_INT_ENA_S 31
/** LP_WDT_INT_CLR_REG register
* need_des
*/
#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30))
#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_CLR_S 30
/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_LP_WDT_INT_CLR (BIT(31))
#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U
#define LP_WDT_LP_WDT_INT_CLR_S 31
/** LP_WDT_DATE_REG register
* need_des
*/
#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
* need_des
*/
#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU
#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
#define LP_WDT_LP_WDT_DATE_S 0
/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_WDT_CLK_EN (BIT(31))
#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
#define LP_WDT_CLK_EN_V 0x00000001U
#define LP_WDT_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

317
components/soc/esp32c5/beta3/include/soc/lp_wdt_struct.h
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@ -1,317 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of config0 register
* need_des
*/
typedef union {
struct {
/** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
* need_des
*/
uint32_t wdt_chip_reset_width:8;
/** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0;
* need_des
*/
uint32_t wdt_chip_reset_en:1;
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
* need_des
*/
uint32_t wdt_pause_in_slp:1;
/** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
* need_des
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
* need_des
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
* need_des
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
* need_des
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
* need_des
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
* need_des
*/
uint32_t wdt_stg3:3;
/** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
* need_des
*/
uint32_t wdt_stg2:3;
/** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
* need_des
*/
uint32_t wdt_stg1:3;
/** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
uint32_t wdt_stg0:3;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t wdt_en:1;
};
uint32_t val;
} lp_wdt_config0_reg_t;
/** Type of config1 register
* need_des
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
* need_des
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} lp_wdt_config1_reg_t;
/** Type of config2 register
* need_des
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
* need_des
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} lp_wdt_config2_reg_t;
/** Type of config3 register
* need_des
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} lp_wdt_config3_reg_t;
/** Type of config4 register
* need_des
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
* need_des
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} lp_wdt_config4_reg_t;
/** Type of feed register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** rtc_wdt_feed : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t rtc_wdt_feed:1;
};
uint32_t val;
} lp_wdt_feed_reg_t;
/** Type of wprotect register
* need_des
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} lp_wdt_wprotect_reg_t;
/** Type of swd_config register
* need_des
*/
typedef union {
struct {
/** swd_reset_flag : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t swd_reset_flag:1;
uint32_t reserved_1:17;
/** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
* need_des
*/
uint32_t swd_auto_feed_en:1;
/** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
* need_des
*/
uint32_t swd_rst_flag_clr:1;
/** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
* need_des
*/
uint32_t swd_signal_width:10;
/** swd_disable : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t swd_disable:1;
/** swd_feed : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t swd_feed:1;
};
uint32_t val;
} lp_wdt_swd_config_reg_t;
/** Type of swd_wprotect register
* need_des
*/
typedef union {
struct {
/** swd_wkey : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t swd_wkey:32;
};
uint32_t val;
} lp_wdt_swd_wprotect_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_raw:1;
/** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_raw:1;
};
uint32_t val;
} lp_wdt_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_st:1;
/** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_st:1;
};
uint32_t val;
} lp_wdt_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_ena:1;
/** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_ena:1;
};
uint32_t val;
} lp_wdt_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t super_wdt_int_clr:1;
/** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_wdt_int_clr:1;
};
uint32_t val;
} lp_wdt_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
* need_des
*/
uint32_t lp_wdt_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_wdt_date_reg_t;
typedef struct lp_wdt_dev_t {
volatile lp_wdt_config0_reg_t config0;
volatile lp_wdt_config1_reg_t config1;
volatile lp_wdt_config2_reg_t config2;
volatile lp_wdt_config3_reg_t config3;
volatile lp_wdt_config4_reg_t config4;
volatile lp_wdt_feed_reg_t feed;
volatile lp_wdt_wprotect_reg_t wprotect;
volatile lp_wdt_swd_config_reg_t swd_config;
volatile lp_wdt_swd_wprotect_reg_t swd_wprotect;
volatile lp_wdt_int_raw_reg_t int_raw;
volatile lp_wdt_int_st_reg_t int_st;
volatile lp_wdt_int_ena_reg_t int_ena;
volatile lp_wdt_int_clr_reg_t int_clr;
uint32_t reserved_034[242];
volatile lp_wdt_date_reg_t date;
} lp_wdt_dev_t;
extern lp_wdt_dev_t LP_WDT;
#ifndef __cplusplus
_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

317
components/soc/esp32c5/beta3/include/soc/lpperi_reg.h
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@ -1,317 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LPPERI_CLK_EN_REG register
* need_des
*/
#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
* need_des
*/
#define LPPERI_RNG_CK_EN (BIT(24))
#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S)
#define LPPERI_RNG_CK_EN_V 0x00000001U
#define LPPERI_RNG_CK_EN_S 24
/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1;
* need_des
*/
#define LPPERI_OTP_DBG_CK_EN (BIT(25))
#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S)
#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U
#define LPPERI_OTP_DBG_CK_EN_S 25
/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1;
* need_des
*/
#define LPPERI_LP_UART_CK_EN (BIT(26))
#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S)
#define LPPERI_LP_UART_CK_EN_V 0x00000001U
#define LPPERI_LP_UART_CK_EN_S 26
/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1;
* need_des
*/
#define LPPERI_LP_IO_CK_EN (BIT(27))
#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S)
#define LPPERI_LP_IO_CK_EN_V 0x00000001U
#define LPPERI_LP_IO_CK_EN_S 27
/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1;
* need_des
*/
#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S)
#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_CK_EN_S 28
/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S)
#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_CK_EN_S 29
/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LPPERI_EFUSE_CK_EN (BIT(30))
#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S)
#define LPPERI_EFUSE_CK_EN_V 0x00000001U
#define LPPERI_EFUSE_CK_EN_S 30
/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_LP_CPU_CK_EN (BIT(31))
#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S)
#define LPPERI_LP_CPU_CK_EN_V 0x00000001U
#define LPPERI_LP_CPU_CK_EN_S 31
/** LPPERI_RESET_EN_REG register
* need_des
*/
#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0;
* need_des
*/
#define LPPERI_BUS_RESET_EN (BIT(23))
#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S)
#define LPPERI_BUS_RESET_EN_V 0x00000001U
#define LPPERI_BUS_RESET_EN_S 23
/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define LPPERI_OTP_DBG_RESET_EN (BIT(25))
#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S)
#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U
#define LPPERI_OTP_DBG_RESET_EN_S 25
/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define LPPERI_LP_UART_RESET_EN (BIT(26))
#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S)
#define LPPERI_LP_UART_RESET_EN_V 0x00000001U
#define LPPERI_LP_UART_RESET_EN_S 26
/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LPPERI_LP_IO_RESET_EN (BIT(27))
#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S)
#define LPPERI_LP_IO_RESET_EN_V 0x00000001U
#define LPPERI_LP_IO_RESET_EN_S 27
/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S)
#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_RESET_EN_S 28
/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S)
#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_RESET_EN_S 29
/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_EFUSE_RESET_EN (BIT(30))
#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S)
#define LPPERI_EFUSE_RESET_EN_V 0x00000001U
#define LPPERI_EFUSE_RESET_EN_S 30
/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_LP_CPU_RESET_EN (BIT(31))
#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S)
#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U
#define LPPERI_LP_CPU_RESET_EN_S 31
/** LPPERI_RNG_DATA_REG register
* need_des
*/
#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8)
/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LPPERI_RND_DATA 0xFFFFFFFFU
#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S)
#define LPPERI_RND_DATA_V 0xFFFFFFFFU
#define LPPERI_RND_DATA_S 0
/** LPPERI_CPU_REG register
* need_des
*/
#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31))
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S)
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31
/** LPPERI_BUS_TIMEOUT_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10)
/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S)
#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14
/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30))
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S)
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30
/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31))
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S)
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31
/** LPPERI_BUS_TIMEOUT_ADDR_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14)
/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S)
#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0
/** LPPERI_BUS_TIMEOUT_UID_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18)
/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S)
#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_S 0
/** LPPERI_MEM_CTRL_REG register
* need_des
*/
#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c)
/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0))
#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S)
#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0
/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_FLAG (BIT(1))
#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S)
#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_S 1
/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_EN (BIT(29))
#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S)
#define LPPERI_UART_WAKEUP_EN_V 0x00000001U
#define LPPERI_UART_WAKEUP_EN_S 29
/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_UART_MEM_FORCE_PD (BIT(30))
#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S)
#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PD_S 30
/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_UART_MEM_FORCE_PU (BIT(31))
#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S)
#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PU_S 31
/** LPPERI_INTERRUPT_SOURCE_REG register
* need_des
*/
#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S)
#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_S 0
/** LPPERI_RNG_CFG_REG register
* need_des
*/
#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x24)
/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
* need des
*/
#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0))
#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S)
#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U
#define LPPERI_RNG_SAMPLE_ENABLE_S 0
/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255;
* need des
*/
#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU
#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S)
#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU
#define LPPERI_RNG_TIMER_PSCALE_S 1
/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1;
* need des
*/
#define LPPERI_RNG_TIMER_EN (BIT(9))
#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S)
#define LPPERI_RNG_TIMER_EN_V 0x00000001U
#define LPPERI_RNG_TIMER_EN_S 9
/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU
#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S)
#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU
#define LPPERI_RNG_SAMPLE_CNT_S 24
/** LPPERI_DATE_REG register
* need_des
*/
#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 36720720;
* need_des
*/
#define LPPERI_LPPERI_DATE 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_S 0
/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_CLK_EN (BIT(31))
#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
#define LPPERI_CLK_EN_V 0x00000001U
#define LPPERI_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/lpperi_struct.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
* need_des
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1;
* need_des
*/
uint32_t otp_dbg_ck_en:1;
/** lp_uart_ck_en : R/W; bitpos: [26]; default: 1;
* need_des
*/
uint32_t lp_uart_ck_en:1;
/** lp_io_ck_en : R/W; bitpos: [27]; default: 1;
* need_des
*/
uint32_t lp_io_ck_en:1;
/** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1;
* need_des
*/
uint32_t lp_ext_i2c_ck_en:1;
/** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t lp_ana_i2c_ck_en:1;
/** efuse_ck_en : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t efuse_ck_en:1;
/** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cpu_ck_en:1;
};
uint32_t val;
} lpperi_clk_en_reg_t;
/** Type of reset_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** bus_reset_en : WT; bitpos: [23]; default: 0;
* need_des
*/
uint32_t bus_reset_en:1;
uint32_t reserved_24:1;
/** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t otp_dbg_reset_en:1;
/** lp_uart_reset_en : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t lp_uart_reset_en:1;
/** lp_io_reset_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t lp_io_reset_en:1;
/** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t lp_ext_i2c_reset_en:1;
/** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_ana_i2c_reset_en:1;
/** efuse_reset_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t efuse_reset_en:1;
/** lp_cpu_reset_en : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cpu_reset_en:1;
};
uint32_t val;
} lpperi_reset_en_reg_t;
/** Type of rng_data register
* need_des
*/
typedef union {
struct {
/** rnd_data : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t rnd_data:32;
};
uint32_t val;
} lpperi_rng_data_reg_t;
/** Type of cpu register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lpcore_dbgm_unavaliable:1;
};
uint32_t val;
} lpperi_cpu_reg_t;
/** Type of bus_timeout register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535;
* need_des
*/
uint32_t lp_peri_timeout_thres:16;
/** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_int_clear:1;
/** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lp_peri_timeout_protect_en:1;
};
uint32_t val;
} lpperi_bus_timeout_reg_t;
/** Type of bus_timeout_addr register
* need_des
*/
typedef union {
struct {
/** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_addr:32;
};
uint32_t val;
} lpperi_bus_timeout_addr_reg_t;
/** Type of bus_timeout_uid register
* need_des
*/
typedef union {
struct {
/** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lpperi_bus_timeout_uid_reg_t;
/** Type of mem_ctrl register
* need_des
*/
typedef union {
struct {
/** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t uart_wakeup_flag_clr:1;
/** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t uart_wakeup_flag:1;
uint32_t reserved_2:27;
/** uart_wakeup_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t uart_wakeup_en:1;
/** uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t uart_mem_force_pd:1;
/** uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t uart_mem_force_pu:1;
};
uint32_t val;
} lpperi_mem_ctrl_reg_t;
/** Type of interrupt_source register
* need_des
*/
typedef union {
struct {
/** lp_interrupt_source : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
uint32_t lp_interrupt_source:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lpperi_interrupt_source_reg_t;
/** Type of rng_cfg register
* need_des
*/
typedef union {
struct {
/** rng_sample_enable : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t rng_sample_enable:1;
/** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255;
* need des
*/
uint32_t rng_timer_pscale:8;
/** rng_timer_en : R/W; bitpos: [9]; default: 1;
* need des
*/
uint32_t rng_timer_en:1;
uint32_t reserved_10:14;
/** rng_sample_cnt : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t rng_sample_cnt:8;
};
uint32_t val;
} lpperi_rng_cfg_reg_t;
/** Group: Version register */
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lpperi_date : R/W; bitpos: [30:0]; default: 36720720;
* need_des
*/
uint32_t lpperi_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lpperi_date_reg_t;
typedef struct lpperi_dev_t {
volatile lpperi_clk_en_reg_t clk_en;
volatile lpperi_reset_en_reg_t reset_en;
volatile lpperi_rng_data_reg_t rng_data;
volatile lpperi_cpu_reg_t cpu;
volatile lpperi_bus_timeout_reg_t bus_timeout;
volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr;
volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid;
volatile lpperi_mem_ctrl_reg_t mem_ctrl;
volatile lpperi_interrupt_source_reg_t interrupt_source;
volatile lpperi_rng_cfg_reg_t rng_cfg;
uint32_t reserved_028[245];
volatile lpperi_date_reg_t date;
} lpperi_dev_t;
extern lpperi_dev_t LPPERI;
#ifndef __cplusplus
_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/mcpwm_reg.h
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components/soc/esp32c5/beta3/include/soc/mcpwm_struct.h
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components/soc/esp32c5/beta3/include/soc/mem_monitor_reg.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
* log config regsiter
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
* enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA
*/
#define MEM_MONITOR_LOG_ENA 0x00000007U
#define MEM_MONITOR_LOG_ENA_M (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
#define MEM_MONITOR_LOG_ENA_V 0x00000007U
#define MEM_MONITOR_LOG_ENA_S 0
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
* Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE
* monitor
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
#define MEM_MONITOR_LOG_MODE_S 3
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(7))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
* check data regsiter
*/
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
/** MEM_MONITOR_LOG_DATA_MASK_REG register
* check data mask register
*/
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_S 0
/** MEM_MONITOR_LOG_MIN_REG register
* log boundary regsiter
*/
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_S 0
/** MEM_MONITOR_LOG_MAX_REG register
* log boundary regsiter
*/
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_S 0
/** MEM_MONITOR_LOG_MEM_START_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_S 0
/** MEM_MONITOR_LOG_MEM_END_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_S 0
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
* current writing address.
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
* writing address update
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
* full flag status register
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
/** MEM_MONITOR_CLOCK_GATE_REG register
* clock gate force on register
*/
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
#define MEM_MONITOR_CLK_EN_V 0x00000001U
#define MEM_MONITOR_CLK_EN_S 0
/** MEM_MONITOR_DATE_REG register
* version register
*/
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34632336;
* version register
*/
#define MEM_MONITOR_DATE 0x0FFFFFFFU
#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
#define MEM_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/mem_monitor_struct.h
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
* log config regsiter
*/
typedef union {
struct {
/** log_ena : R/W; bitpos: [2:0]; default: 0;
* enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA
*/
uint32_t log_ena:3;
/** log_mode : R/W; bitpos: [6:3]; default: 0;
* Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE
* monitor
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [7]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
uint32_t log_mem_loop_enable:1;
uint32_t reserved_8:24;
};
uint32_t val;
} mem_monitor_log_setting_reg_t;
/** Type of log_check_data register
* check data regsiter
*/
typedef union {
struct {
/** log_check_data : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
uint32_t log_check_data:32;
};
uint32_t val;
} mem_monitor_log_check_data_reg_t;
/** Type of log_data_mask register
* check data mask register
*/
typedef union {
struct {
/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
uint32_t log_data_mask:4;
uint32_t reserved_4:28;
};
uint32_t val;
} mem_monitor_log_data_mask_reg_t;
/** Type of log_min register
* log boundary regsiter
*/
typedef union {
struct {
/** log_min : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
uint32_t log_min:32;
};
uint32_t val;
} mem_monitor_log_min_reg_t;
/** Type of log_max register
* log boundary regsiter
*/
typedef union {
struct {
/** log_max : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
uint32_t log_max:32;
};
uint32_t val;
} mem_monitor_log_max_reg_t;
/** Type of log_mem_start register
* log message store range register
*/
typedef union {
struct {
/** log_mem_start : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
uint32_t log_mem_start:32;
};
uint32_t val;
} mem_monitor_log_mem_start_reg_t;
/** Type of log_mem_end register
* log message store range register
*/
typedef union {
struct {
/** log_mem_end : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
uint32_t log_mem_end:32;
};
uint32_t val;
} mem_monitor_log_mem_end_reg_t;
/** Type of log_mem_current_addr register
* current writing address.
*/
typedef union {
struct {
/** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
uint32_t log_mem_current_addr:32;
};
uint32_t val;
} mem_monitor_log_mem_current_addr_reg_t;
/** Type of log_mem_addr_update register
* writing address update
*/
typedef union {
struct {
/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
uint32_t log_mem_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_log_mem_addr_update_reg_t;
/** Type of log_mem_full_flag register
* full flag status register
*/
typedef union {
struct {
/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
uint32_t log_mem_full_flag:1;
/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
uint32_t clr_log_mem_full_flag:1;
uint32_t reserved_2:30;
};
uint32_t val;
} mem_monitor_log_mem_full_flag_reg_t;
/** Group: clk register */
/** Type of clock_gate register
* clock gate force on register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_clock_gate_reg_t;
/** Group: version register */
/** Type of date register
* version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 34632336;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} mem_monitor_date_reg_t;
typedef struct mem_monitor_dev_t {
volatile mem_monitor_log_setting_reg_t log_setting;
volatile mem_monitor_log_check_data_reg_t log_check_data;
volatile mem_monitor_log_data_mask_reg_t log_data_mask;
volatile mem_monitor_log_min_reg_t log_min;
volatile mem_monitor_log_max_reg_t log_max;
volatile mem_monitor_log_mem_start_reg_t log_mem_start;
volatile mem_monitor_log_mem_end_reg_t log_mem_end;
volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
volatile mem_monitor_clock_gate_reg_t clock_gate;
uint32_t reserved_02c[244];
volatile mem_monitor_date_reg_t date;
} mem_monitor_dev_t;
extern mem_monitor_dev_t MEM_MONITOR;
#ifndef __cplusplus
_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/beta3/include/soc/otp_debug_reg.h
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