mirror of
https://github.com/espressif/esp-idf.git
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271 lines
7.1 KiB
C
271 lines
7.1 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: configure_register */
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/** Type of bod_mode0_cntl register
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* Configure brownout mode0
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*/
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typedef union {
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struct {
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uint32_t reserved_0:6;
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/** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
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* enable suspend spi when brownout interrupt or not
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* 1:enable
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* 0:disable
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*/
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uint32_t bod_mode0_close_flash_ena:1;
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/** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
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* enable power down RF when brownout interrupt or not
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* 1:enable
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* 0:disable
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*/
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uint32_t bod_mode0_pd_rf_ena:1;
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/** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
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* set the undervoltage hold time for triggering brownout interrupt
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*/
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uint32_t bod_mode0_intr_wait:10;
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/** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
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* set the undervoltage hold time for triggering brownout reset
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*/
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uint32_t bod_mode0_reset_wait:10;
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/** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
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* clear brownout count or not
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* 1: clear
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* 0: no operation
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*/
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uint32_t bod_mode0_cnt_clr:1;
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/** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
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* enable brownout interrupt or not
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* 1: enable
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* 0: disable
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*/
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uint32_t bod_mode0_intr_ena:1;
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/** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
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* select brownout reset level
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* 1: system reset
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* 0: chip reset
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*/
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uint32_t bod_mode0_reset_sel:1;
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/** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
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* enable brownout reset or not
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* 1: enable
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* 0: disable
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*/
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uint32_t bod_mode0_reset_ena:1;
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};
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uint32_t val;
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} lp_ana_bod_mode0_cntl_reg_t;
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/** Type of bod_mode1_cntl register
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* Configure brownout mode1
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
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* enable brownout mode1 reset or not
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* 1: enable
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* 0: disable
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*/
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uint32_t bod_mode1_reset_ena:1;
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};
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uint32_t val;
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} lp_ana_bod_mode1_cntl_reg_t;
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/** Type of ck_glitch_cntl register
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* Configure power glitch
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*/
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typedef union {
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struct {
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uint32_t reserved_0:27;
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/** pwr_glitch_reset_ena : R/W; bitpos: [30:27]; default: 0;
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* enable powerglitch or not
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*/
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uint32_t pwr_glitch_reset_ena:4;
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/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
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* reserved
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*/
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uint32_t ck_glitch_reset_ena:1;
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};
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uint32_t val;
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} lp_ana_ck_glitch_cntl_reg_t;
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/** Type of fib_enable register
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* configure FIB REG
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*/
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typedef union {
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struct {
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/** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
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* configure analog fib by software
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*/
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uint32_t ana_fib_ena:32;
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};
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uint32_t val;
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} lp_ana_fib_enable_reg_t;
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/** Type of int_raw register
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* interrpt raw register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
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* brownout mode0 interrupt raw register
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*/
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uint32_t bod_mode0_int_raw:1;
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};
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uint32_t val;
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} lp_ana_int_raw_reg_t;
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/** Type of int_st register
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* interrpt status register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** bod_mode0_int_st : RO; bitpos: [31]; default: 0;
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* brownout mode0 interrupt status register
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*/
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uint32_t bod_mode0_int_st:1;
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};
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uint32_t val;
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} lp_ana_int_st_reg_t;
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/** Type of int_ena register
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* interrpt enable register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
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* brownout mode0 interrupt enable register
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*/
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uint32_t bod_mode0_int_ena:1;
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};
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uint32_t val;
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} lp_ana_int_ena_reg_t;
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/** Type of int_clr register
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* interrpt clear register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
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* brownout mode0 interrupt clear register
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*/
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uint32_t bod_mode0_int_clr:1;
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};
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uint32_t val;
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} lp_ana_int_clr_reg_t;
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/** Type of lp_int_raw register
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* lp interrupt raw register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
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* brownout mode0 lp interrupt raw register
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*/
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uint32_t bod_mode0_lp_int_raw:1;
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};
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uint32_t val;
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} lp_ana_lp_int_raw_reg_t;
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/** Type of lp_int_st register
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* lp interrupt status register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
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* brownout mode0 lp interrupt status register
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*/
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uint32_t bod_mode0_lp_int_st:1;
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};
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uint32_t val;
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} lp_ana_lp_int_st_reg_t;
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/** Type of lp_int_ena register
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* lp interrupt enable register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
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* brownout mode0 lp interrupt enable register
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*/
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uint32_t bod_mode0_lp_int_ena:1;
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};
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uint32_t val;
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} lp_ana_lp_int_ena_reg_t;
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/** Type of lp_int_clr register
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* lp interrupt clear register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
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* brownout mode0 lp interrupt clear register
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*/
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uint32_t bod_mode0_lp_int_clr:1;
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};
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uint32_t val;
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} lp_ana_lp_int_clr_reg_t;
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/** Type of date register
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* version register
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*/
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typedef union {
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struct {
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/** lp_ana_date : R/W; bitpos: [30:0]; default: 36774528;
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* version register
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*/
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uint32_t lp_ana_date:31;
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/** clk_en : R/W; bitpos: [31]; default: 0;
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* reserved
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*/
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uint32_t clk_en:1;
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};
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uint32_t val;
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} lp_ana_date_reg_t;
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typedef struct {
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volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
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volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
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volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
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volatile lp_ana_fib_enable_reg_t fib_enable;
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volatile lp_ana_int_raw_reg_t int_raw;
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volatile lp_ana_int_st_reg_t int_st;
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volatile lp_ana_int_ena_reg_t int_ena;
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volatile lp_ana_int_clr_reg_t int_clr;
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volatile lp_ana_lp_int_raw_reg_t lp_int_raw;
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volatile lp_ana_lp_int_st_reg_t lp_int_st;
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volatile lp_ana_lp_int_ena_reg_t lp_int_ena;
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volatile lp_ana_lp_int_clr_reg_t lp_int_clr;
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uint32_t reserved_030[243];
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volatile lp_ana_date_reg_t date;
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} lp_ana_dev_t;
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extern lp_ana_dev_t LP_ANA_PERI;
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#ifndef __cplusplus
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_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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