baohongde d1db2df316 components/bt: High level interrupt in bluetooth ... components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt components/os: high level interrupt(5) components/os: hli_api: meta queue: fix out of bounds access, check for overflow components/os: hli: don't spill registers, instead save them to a separate region Level 4 interrupt has a chance of preempting a window overflow or underflow exception. Therefore it is not possible to use standard context save functions, as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4). Instead, mask window overflows and save the entire general purpose register file, plus some of the special registers. Then clear WindowStart, allowing the C handler to execute without spilling the old windows. On exit from the interrupt handler, do everything in reverse. components/bt: using high level interrupt in lc components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory` components/bt: optimize code structure components/os: Modify the BT assert process to adapt to coredump and HLI components/os: Disable exception mode after saving special registers To store some registers first, avoid stuck due to live lock after disabling exception mode components/os: using dport instead of AHB in BT to fix live lock components/bt: Fix hli queue send error components/bt: Fix CI fail # Conflicts: # components/bt/CMakeLists.txt # components/bt/component.mk # components/bt/controller/bt.c # components/bt/controller/lib # components/esp_common/src/int_wdt.c # components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S # components/soc/esp32/include/soc/soc.h		2021-09-09 11:29:06 +08:00
..
cache_err_int.c	esp32: move brownout and cache err int setup	2021-03-31 19:13:03 +08:00
cache_err_int.h	esp32: move brownout and cache err int setup	2021-03-31 19:13:03 +08:00
clk.c	soc: add reset reasons in soc component	2021-07-13 10:45:38 +08:00
CMakeLists.txt	esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt	2021-08-03 14:35:29 +08:00
component.mk	esp_system: support riscv panic	2020-11-13 07:49:11 +11:00
highint_hdl.S	components/bt: High level interrupt in bluetooth	2021-09-09 11:29:06 +08:00
intr.c	esp_system: support riscv panic	2020-11-13 07:49:11 +11:00
reset_reason.c	soc: add reset reasons in soc component	2021-07-13 10:45:38 +08:00
system_internal.c	esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt	2021-08-03 14:35:29 +08:00