mirror of
https://github.com/espressif/esp-idf.git
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199 lines
8.6 KiB
C
199 lines
8.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <sys/cdefs.h>
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#include <sys/time.h>
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_clk_internal.h"
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#include "esp32c61/rom/ets_sys.h"
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#include "esp32c61/rom/uart.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_periph.h"
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#include "esp_cpu.h"
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#include "hal/wdt_hal.h"
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#include "esp_private/esp_modem_clock.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_clk.h"
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#include "esp_private/esp_pmu.h"
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#include "esp_rom_uart.h"
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#include "esp_rom_sys.h"
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#include "ocode_init.h"
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// TODO: [ESP32C61] IDF-9249
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/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
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* Larger values increase startup delay. Smaller values may cause false positive
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* detection (i.e. oscillator runs for a few cycles and then stops).
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*/
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#define SLOW_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
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#define MHZ (1000000)
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static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
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static const char *TAG = "clk";
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__attribute__((weak)) void esp_clk_init(void)
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{
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#if !CONFIG_IDF_ENV_FPGA
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pmu_init();
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if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) {
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esp_ocode_calib_init();
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}
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assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M);
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rtc_clk_8m_enable(true);
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rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
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#endif
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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// WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
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// If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
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// Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
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// This prevents excessive delay before resetting in case the supply voltage is drawdown.
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// (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
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wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
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uint32_t stage_timeout_ticks = (uint32_t)(1600ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_feed(&rtc_wdt_ctx);
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//Bootloader has enabled RTC WDT until now. We're only modifying timeout, so keep the stage and timeout action the same
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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#if defined(CONFIG_RTC_CLK_SRC_EXT_CRYS)
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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#elif defined(CONFIG_RTC_CLK_SRC_EXT_OSC)
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_OSC_SLOW);
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#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K)
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC32K);
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#else
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
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#endif
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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// After changing a frequency WDT timeout needs to be set for new frequency.
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stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_feed(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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#endif
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rtc_cpu_freq_config_t old_config, new_config;
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rtc_clk_cpu_freq_get_config(&old_config);
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const uint32_t old_freq_mhz = old_config.freq_mhz;
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const uint32_t new_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;
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bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
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assert(res);
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// Wait for UART TX to finish, otherwise some UART output will be lost
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// when switching APB frequency
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esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
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if (res) {
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rtc_clk_cpu_freq_set_config(&new_config);
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}
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// Re calculate the ccount to make time calculation correct.
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esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
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}
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static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
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{
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uint32_t cal_val = 0;
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/* number of times to repeat 32k XTAL calibration
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* before giving up and switching to the internal RC
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*/
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int retry_32k_xtal = 3;
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do {
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if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K || rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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/* 32k XTAL oscillator needs to be enabled and running before it can
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* be used. Hardware doesn't have a direct way of checking if the
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* oscillator is running. Here we use rtc_clk_cal function to count
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* the number of main XTAL cycles in the given number of 32k XTAL
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* oscillator cycles. If the 32k XTAL has not started up, calibration
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* will time out, returning 0.
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*/
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ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
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rtc_cal_sel_t cal_sel = 0;
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if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
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rtc_clk_32k_enable(true);
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cal_sel = RTC_CAL_32K_XTAL;
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} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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rtc_clk_32k_enable_external();
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cal_sel = RTC_CAL_32K_OSC_SLOW;
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}
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// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
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if (SLOW_CLK_CAL_CYCLES > 0) {
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cal_val = rtc_clk_cal(cal_sel, SLOW_CLK_CAL_CYCLES);
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if (cal_val == 0) {
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if (retry_32k_xtal-- > 0) {
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continue;
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}
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ESP_EARLY_LOGW(TAG, "32 kHz clock not found, switching to internal 150 kHz oscillator");
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rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
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}
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}
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} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
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rtc_clk_rc32k_enable(true);
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}
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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*/
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cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
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} else {
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const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz());
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}
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} while (cal_val == 0);
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ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
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esp_clk_slowclk_cal_set(cal_val);
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}
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void rtc_clk_select_rtc_slow_clk(void)
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{
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select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_XTAL32K);
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}
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/* This function is not exposed as an API at this point.
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* All peripheral clocks are default enabled after chip is powered on.
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* This function disables some peripheral clocks when cpu starts.
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* These peripheral clocks are enabled when the peripherals are initialized
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* and disabled when they are de-initialized.
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*/
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__attribute__((weak)) void esp_perip_clk_init(void)
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{
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/* During system initialization, the low-power clock source of the modem
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* (WiFi, BLE or Coexist) follows the configuration of the slow clock source
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* of the system. If the WiFi, BLE or Coexist module needs a higher
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* precision sleep clock (for example, the BLE needs to use the main XTAL
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* oscillator (40 MHz) to provide the clock during the sleep process in some
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* scenarios), the module needs to switch to the required clock source by
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* itself. */ //TODO - WIFI-5233
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soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
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modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)(\
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(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW \
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: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \
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: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \
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: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \
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: SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
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modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
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ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
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}
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