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esp-idf/components/esp_gdbstub/src
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Mahavir Jain 614ad494f6
fix(soc): change debug addr range to CPU subsystem range 
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
2024-01-24 12:52:27 +05:30
..
port fix(soc): change debug addr range to CPU subsystem range 2024-01-24 12:52:27 +05:30
gdbstub_transport.c esp_gdbstub: refactor code 2023-04-28 12:38:26 +08:00
gdbstub.c esp_gdbstub: refactor code 2023-04-28 12:38:26 +08:00
packet.c coverity: fix uninit variable issue in driver 2022-08-03 10:46:50 +08:00