Armando c331c85318 mspi: make cpu clock source switch safe
For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be
cleared. When system clock switches up, the delays should be restored.
2021-10-19 21:47:27 +08:00
..
2021-08-26 11:25:39 +08:00
2021-07-16 20:14:26 +08:00
2020-10-28 07:21:29 +08:00

esp_hw_support

This component contains hardware-related operations for supporting the system. These operations are one level above that of hal in that these(1) use system services such as memory allocation, logging, scheduling or (2) may be multi-step operations involving/affecting multiple parts of the SoC.

Implementations that don't fit other components cleanly, but are not worth creating a new component for (yet) may also be placed here as long as they don't pull dependencies other than the core system components.