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102 lines
4.9 KiB
Plaintext
102 lines
4.9 KiB
Plaintext
menu "Hardware Settings"
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menu "MAC Config"
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config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
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bool
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config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
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bool
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config ESP_MAC_ADDR_UNIVERSE_BT
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bool
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config ESP_MAC_ADDR_UNIVERSE_ETH
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bool
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# Insert chip-specific MAC config
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rsource "./port/$IDF_TARGET/Kconfig.mac"
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endmenu
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menu "Sleep Config"
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# This is here since this option affect behavior of esp_light_sleep_start
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# regardless of power management configuration.
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config ESP_SLEEP_POWER_DOWN_FLASH
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bool "Power down flash in light sleep when there is no SPIRAM"
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depends on !SPIRAM
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default n
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help
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If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs
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more time when chip wakes up. Can only be enabled if there is no SPIRAM configured.
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This option will power down flash under a strict but relatively safe condition. Also, it is possible to
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power down flash under a relaxed condition by using esp_sleep_pd_config() to set ESP_PD_DOMAIN_VDDSDIO
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to ESP_PD_OPTION_OFF. It should be noted that there is a risk in powering down flash, you can refer
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`ESP-IDF Programming Guide/API Reference/System API/Sleep Modes/Power-down of Flash` for more details.
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config ESP_SLEEP_RTC_BUS_ISO_WORKAROUND
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bool
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default y if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
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config ESP_SLEEP_GPIO_RESET_WORKAROUND
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bool "light sleep GPIO reset workaround"
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default y if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32H2
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select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
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help
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esp32c3, esp32s3 and esp32h2 will reset at wake-up if GPIO is received a small electrostatic
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pulse during light sleep, with specific condition
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- GPIO needs to be configured as input-mode only
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- The pin receives a small electrostatic pulse, and reset occurs when the pulse
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voltage is higher than 6 V
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For GPIO set to input mode only, it is not a good practice to leave it open/floating,
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The hardware design needs to controlled it with determined supply or ground voltage
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is necessary.
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This option provides a software workaround for this issue. Configure to isolate all
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GPIO pins in sleep state.
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config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND
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bool "PSRAM leakage current workaround in light sleep"
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depends on SPIRAM
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default y
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help
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When the CS pin of SPIRAM is not pulled up, the sleep current will
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increase during light sleep. If the CS pin of SPIRAM has an external
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pull-up, you do not need to select this option, otherwise, you
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should enable this option.
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config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
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bool "Flash leakage current workaround in light sleep"
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default y
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help
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When the CS pin of Flash is not pulled up, the sleep current will
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increase during light sleep. If the CS pin of Flash has an external
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pull-up, you do not need to select this option, otherwise, you
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should enable this option.
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config ESP_SLEEP_MSPI_NEED_ALL_IO_PU
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bool "All pins of mspi need pull up"
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depends on ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND || ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
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default y if IDF_TARGET_ESP32S3
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help
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To reduce leakage current, some types of SPI Flash/RAM only need to pull up the CS pin
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during light sleep. But there are also some kinds of SPI Flash/RAM that need to pull up
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all pins. It depends on the SPI Flash/RAM chip used.
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endmenu
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menu "RTC Clock Config"
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# This is used for configure the RTC clock.
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config RTC_CLOCK_BBPLL_POWER_ON_WITH_USB
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bool "Keep BBPLL clock always work"
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depends on ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
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default y
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help
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When the chip goes sleep or software reset, the clock source would change to XTAL
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and switch off the BBPLL clock for saving power. However, this might make the
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USB_SERIAL_JTAG down which depends on BBPLL as its unique clock source.
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Therefore, this is used for keeping bbpll clock always on when USB_SERIAL_JTAG PORT is using.
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If you want to use USB_SERIAL_JTAG under sw_reset case or sleep-wakeup case, you shoule select
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this option. But be aware that this might increase the power consumption.
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endmenu
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endmenu
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