Sudeep Mohanty b9ecc1e57a feat(ulp-riscv): Added SW interrupt capability for ULP RISC-V ... This commit adds a feature to ULP RISC-V where the user can trigger a software interrupt on the ULP RISC-V core.		2024-01-18 15:59:40 +01:00
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include	feat(ulp-riscv): Added SW interrupt capability for ULP RISC-V	2024-01-18 15:59:40 +01:00
start.S	feat(ulp-riscv): Added interrupt vector handling for ULP RISC-V	2024-01-18 15:59:27 +01:00
ulp_riscv_adc.c	ulp: migrate tests to pytest embedded	2022-08-03 09:36:17 +08:00
ulp_riscv_i2c.c	ulp-riscv-i2c: Add ULP RISC-V I2C read/write timeout config option	2023-05-09 11:17:01 +02:00
ulp_riscv_interrupt.c	feat(ulp-riscv): Added SW interrupt capability for ULP RISC-V	2024-01-18 15:59:40 +01:00
ulp_riscv_lock.c	ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.	2022-08-05 18:16:31 +08:00
ulp_riscv_print.c	Add ULP-RISCV print and bitbanged UART tx API	2022-07-29 12:18:01 +08:00
ulp_riscv_touch.c	ulp-riscv-touch: Added support for the touch sensor on ULP RISC-V	2023-06-09 08:41:34 +02:00
ulp_riscv_uart.c	Add ULP-RISCV print and bitbanged UART tx API	2022-07-29 12:18:01 +08:00
ulp_riscv_utils.c	feat(ulp-riscv): Added SW interrupt capability for ULP RISC-V	2024-01-18 15:59:40 +01:00
ulp_riscv_vectors.S	feat(ulp-riscv): Added interrupt vector handling for ULP RISC-V	2024-01-18 15:59:27 +01:00