Sudeep Mohanty b9ecc1e57a feat(ulp-riscv): Added SW interrupt capability for ULP RISC-V ...

This commit adds a feature to ULP RISC-V where the user can trigger
a software interrupt on the ULP RISC-V core.

2024-01-18 15:59:40 +01:00

..

include

ulp-riscv-i2c: Add ULP RISC-V I2C read/write timeout config option

2023-05-09 11:17:01 +02:00

shared/include

ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.

2022-08-05 18:16:31 +08:00

ulp_core

feat(ulp-riscv): Added SW interrupt capability for ULP RISC-V

2024-01-18 15:59:40 +01:00

ulp_riscv_i2c.c

fix(ulp-i2c): fixed ulp i2c not working from main cpu if compiled with 0S or O2

2023-09-13 09:41:00 +08:00

ulp_riscv_lock.c

ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.

2022-08-05 18:16:31 +08:00

ulp_riscv.c

ulp: Added APIs to handle ULP signal ISRs for the main CPU

2023-02-24 07:25:39 +00:00