mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
531 lines
22 KiB
C
531 lines
22 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_SENS_STRUCT_H_
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#define _SOC_SENS_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct sens_dev_s {
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union {
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struct {
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uint32_t sar1_clk_div : 8; /*clock divider*/
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uint32_t reserved8 : 10;
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uint32_t sar1_clk_gated : 1;
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uint32_t sar1_sample_num : 8;
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uint32_t reserved27 : 1;
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uint32_t sar1_data_inv : 1; /*Invert SAR ADC1 data*/
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uint32_t sar1_int_en : 1; /*enable saradc1 to send out interrupt*/
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uint32_t reserved30 : 2;
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};
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uint32_t val;
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} sar_reader1_ctrl;
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uint32_t sar_reader1_status;
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union {
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struct {
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uint32_t reserved0 : 24;
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uint32_t force_xpd_amp : 2;
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uint32_t amp_rst_fb_force : 2;
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uint32_t amp_short_ref_force : 2;
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uint32_t amp_short_ref_gnd_force : 2;
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};
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uint32_t val;
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} sar_meas1_ctrl1;
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union {
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struct {
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uint32_t meas1_data_sar : 16; /*SAR ADC1 data*/
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uint32_t meas1_done_sar : 1; /*SAR ADC1 conversion done indication*/
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uint32_t meas1_start_sar : 1; /*SAR ADC1 controller (in RTC) starts conversion*/
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uint32_t meas1_start_force : 1; /*1: SAR ADC1 controller (in RTC) is started by SW*/
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uint32_t sar1_en_pad : 12; /*SAR ADC1 pad enable bitmap*/
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uint32_t sar1_en_pad_force : 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW*/
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};
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uint32_t val;
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} sar_meas1_ctrl2;
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union {
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struct {
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uint32_t reserved0 : 31;
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uint32_t sar1_dig_force : 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/
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};
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uint32_t val;
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} sar_meas1_mux;
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uint32_t sar_atten1;
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union {
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struct {
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uint32_t sar_amp_wait1 : 16;
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uint32_t sar_amp_wait2 : 16;
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};
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uint32_t val;
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} sar_amp_ctrl1;
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union {
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struct {
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uint32_t sar1_dac_xpd_fsm_idle : 1;
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uint32_t xpd_sar_amp_fsm_idle : 1;
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uint32_t amp_rst_fb_fsm_idle : 1;
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uint32_t amp_short_ref_fsm_idle : 1;
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uint32_t amp_short_ref_gnd_fsm_idle : 1;
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uint32_t xpd_sar_fsm_idle : 1;
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uint32_t sar_rstb_fsm_idle : 1;
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uint32_t reserved7 : 9;
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uint32_t sar_amp_wait3 : 16;
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};
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uint32_t val;
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} sar_amp_ctrl2;
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union {
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struct {
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uint32_t sar1_dac_xpd_fsm : 4;
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uint32_t xpd_sar_amp_fsm : 4;
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uint32_t amp_rst_fb_fsm : 4;
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uint32_t amp_short_ref_fsm : 4;
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uint32_t amp_short_ref_gnd_fsm : 4;
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uint32_t xpd_sar_fsm : 4;
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uint32_t sar_rstb_fsm : 4;
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uint32_t reserved28 : 4;
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};
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uint32_t val;
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} sar_amp_ctrl3;
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union {
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struct {
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uint32_t sar2_clk_div : 8; /*clock divider*/
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uint32_t reserved8 : 8;
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uint32_t sar2_wait_arb_cycle : 2; /*wait arbit stable after sar_done*/
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uint32_t sar2_clk_gated : 1;
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uint32_t sar2_sample_num : 8;
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uint32_t reserved27 : 2;
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uint32_t sar2_data_inv : 1; /*Invert SAR ADC2 data*/
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uint32_t sar2_int_en : 1; /*enable saradc2 to send out interrupt*/
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} sar_reader2_ctrl;
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uint32_t sar_reader2_status;
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union {
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struct {
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uint32_t sar2_cntl_state : 3; /*saradc2_cntl_fsm*/
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uint32_t sar2_pwdet_cal_en : 1; /*rtc control pwdet enable*/
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uint32_t sar2_pkdet_cal_en : 1; /*rtc control pkdet enable*/
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uint32_t sar2_en_test : 1; /*SAR2_EN_TEST*/
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uint32_t sar2_rstb_force : 2;
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uint32_t sar2_standby_wait : 8;
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uint32_t sar2_rstb_wait : 8;
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uint32_t sar2_xpd_wait : 8;
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};
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uint32_t val;
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} sar_meas2_ctrl1;
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union {
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struct {
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uint32_t meas2_data_sar : 16; /*SAR ADC2 data*/
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uint32_t meas2_done_sar : 1; /*SAR ADC2 conversion done indication*/
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uint32_t meas2_start_sar : 1; /*SAR ADC2 controller (in RTC) starts conversion*/
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uint32_t meas2_start_force : 1; /*1: SAR ADC2 controller (in RTC) is started by SW*/
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uint32_t sar2_en_pad : 12; /*SAR ADC2 pad enable bitmap*/
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uint32_t sar2_en_pad_force : 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW*/
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};
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uint32_t val;
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} sar_meas2_ctrl2;
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union {
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struct {
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uint32_t reserved0 : 28;
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uint32_t sar2_pwdet_cct : 3; /*SAR2_PWDET_CCT*/
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uint32_t sar2_rtc_force : 1; /*in sleep, force to use rtc to control ADC*/
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};
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uint32_t val;
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} sar_meas2_mux;
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uint32_t sar_atten2;
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union {
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struct {
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uint32_t reserved0 : 29;
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uint32_t force_xpd_sar : 2;
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uint32_t sarclk_en : 1;
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};
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uint32_t val;
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} sar_power_xpd_sar;
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union {
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struct {
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uint32_t i2c_slave_addr1 : 11;
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uint32_t i2c_slave_addr0 : 11;
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uint32_t meas_status : 8;
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uint32_t reserved30 : 2;
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};
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uint32_t val;
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} sar_slave_addr1;
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union {
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struct {
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uint32_t i2c_slave_addr3 : 11;
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uint32_t i2c_slave_addr2 : 11;
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uint32_t reserved22 : 10;
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};
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uint32_t val;
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} sar_slave_addr2;
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union {
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struct {
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uint32_t i2c_slave_addr5 : 11;
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uint32_t i2c_slave_addr4 : 11;
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uint32_t reserved22 : 10;
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};
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uint32_t val;
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} sar_slave_addr3;
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union {
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struct {
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uint32_t i2c_slave_addr7 : 11;
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uint32_t i2c_slave_addr6 : 11;
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uint32_t reserved22 : 10;
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};
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uint32_t val;
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} sar_slave_addr4;
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union {
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struct {
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uint32_t tsens_out : 8; /*temperature sensor data out*/
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uint32_t tsens_ready : 1; /*indicate temperature sensor out ready*/
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uint32_t reserved9 : 3;
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uint32_t tsens_int_en : 1; /*enable temperature sensor to send out interrupt*/
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uint32_t tsens_in_inv : 1; /*invert temperature sensor data*/
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uint32_t tsens_clk_div : 8; /*temperature sensor clock divider*/
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uint32_t tsens_power_up : 1; /*temperature sensor power up*/
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uint32_t tsens_power_up_force : 1; /*1: dump out & power up controlled by SW*/
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uint32_t tsens_dump_out : 1; /*temperature sensor dump out*/
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uint32_t reserved25 : 7;
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};
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uint32_t val;
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} sar_tctrl;
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union {
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struct {
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uint32_t tsens_xpd_wait : 12;
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uint32_t tsens_xpd_force : 2;
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uint32_t tsens_clk_inv : 1;
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uint32_t reserved15 : 17;
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};
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uint32_t val;
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} sar_tctrl2;
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union {
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struct {
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uint32_t sar_i2c_ctrl : 28; /*I2C control data*/
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uint32_t sar_i2c_start : 1; /*start I2C*/
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uint32_t sar_i2c_start_force : 1; /*1: I2C started by SW*/
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uint32_t reserved30 : 2;
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};
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uint32_t val;
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} sar_i2c_ctrl;
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union {
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struct {
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uint32_t touch_outen : 15; /*touch controller output enable*/
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uint32_t touch_status_clr : 1; /*clear all touch active status*/
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uint32_t touch_data_sel : 2; /*3: smooth data 2: baseline 1,0: raw_data*/
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uint32_t touch_denoise_end : 1; /*touch_denoise_done*/
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uint32_t touch_unit_end : 1; /*touch_unit_done*/
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uint32_t touch_approach_pad2 : 4; /*indicate which pad is approach pad2*/
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uint32_t touch_approach_pad1 : 4; /*indicate which pad is approach pad1*/
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uint32_t touch_approach_pad0 : 4; /*indicate which pad is approach pad0*/
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};
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uint32_t val;
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} sar_touch_conf;
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union {
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struct {
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uint32_t touch_denoise_data : 22;
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uint32_t reserved22 : 10;
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};
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uint32_t val;
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} sar_touch_denoise;
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union {
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struct {
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uint32_t thresh : 22; /*Finger threshold for touch pad 1*/
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uint32_t reserved22 : 10;
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};
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uint32_t val;
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} touch_thresh[14];
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union {
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struct {
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uint32_t touch_pad_active : 15; /*touch active status*/
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uint32_t touch_channel_clr : 15; /*Clear touch channel*/
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uint32_t reserved30 : 1;
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uint32_t touch_meas_done : 1;
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};
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uint32_t val;
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} sar_touch_chn_st;
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union {
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struct {
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uint32_t touch_denoise_data : 22; /*the counter for touch pad 0*/
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uint32_t touch_scan_curr : 4;
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uint32_t reserved26 : 6;
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};
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uint32_t val;
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} sar_touch_status0;
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union {
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struct {
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uint32_t touch_pad_data : 22;
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uint32_t reserved22 : 7;
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uint32_t touch_pad_debounce : 3;
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};
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uint32_t val;
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} sar_touch_status[14];
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union {
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struct {
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uint32_t touch_slp_data : 22;
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uint32_t reserved22 : 7;
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uint32_t touch_slp_debounce : 3;
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};
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uint32_t val;
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} sar_touch_slp_status;
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union {
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struct {
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uint32_t touch_approach_pad2_cnt : 8;
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uint32_t touch_approach_pad1_cnt : 8;
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uint32_t touch_approach_pad0_cnt : 8;
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uint32_t touch_slp_approach_cnt : 8;
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};
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uint32_t val;
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} sar_touch_appr_status;
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union {
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struct {
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uint32_t reserved0 : 25;
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uint32_t dbg_trigger : 1; /*trigger cocpu debug registers*/
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uint32_t clk_en_st : 1; /*check cocpu whether clk on*/
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uint32_t reset_n : 1; /*check cocpu whether in reset state*/
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uint32_t eoi : 1; /*check cocpu whether in interrupt state*/
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uint32_t trap : 1; /*check cocpu whether in trap state*/
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uint32_t ebreak : 1; /*check cocpu whether in ebreak*/
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} sar_cocpu_state;
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union {
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struct {
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uint32_t touch_done : 1; /*int from touch done*/
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uint32_t touch_inactive : 1; /*int from touch inactive*/
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uint32_t touch_active : 1; /*int from touch active*/
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uint32_t saradc1 : 1; /*int from saradc1*/
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uint32_t saradc2 : 1; /*int from saradc2*/
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uint32_t tsens : 1; /*int from tsens*/
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uint32_t start : 1; /*int from start*/
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uint32_t sw : 1; /*int from software*/
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uint32_t swd : 1; /*int from super watch dog*/
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uint32_t touch_timeout : 1;
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uint32_t touch_approach_loop_done : 1;
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uint32_t touch_scan_done : 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} sar_cocpu_int_raw;
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union {
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struct {
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uint32_t touch_done : 1;
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uint32_t touch_inactive : 1;
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uint32_t touch_active : 1;
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uint32_t saradc1 : 1;
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uint32_t saradc2 : 1;
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uint32_t tsens : 1;
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uint32_t start : 1;
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uint32_t sw : 1; /*cocpu int enable*/
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uint32_t swd : 1;
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uint32_t touch_timeout : 1;
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uint32_t touch_approach_loop_done : 1;
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uint32_t touch_scan_done : 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} sar_cocpu_int_ena;
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union {
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struct {
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uint32_t touch_done : 1;
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uint32_t touch_inactive : 1;
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uint32_t touch_active : 1;
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uint32_t saradc1 : 1;
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uint32_t saradc2 : 1;
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uint32_t tsens : 1;
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uint32_t start : 1;
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uint32_t sw : 1; /*cocpu int status*/
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uint32_t swd : 1;
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uint32_t touch_timeout : 1;
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uint32_t touch_approach_loop_done : 1;
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uint32_t touch_scan_done : 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} sar_cocpu_int_st;
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union {
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struct {
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uint32_t touch_done : 1;
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uint32_t touch_inactive : 1;
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uint32_t touch_active : 1;
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uint32_t saradc1 : 1;
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uint32_t saradc2 : 1;
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uint32_t tsens : 1;
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uint32_t start : 1;
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uint32_t sw : 1; /*cocpu int clear*/
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uint32_t swd : 1;
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uint32_t touch_timeout : 1;
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uint32_t touch_approach_loop_done : 1;
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uint32_t touch_scan_done : 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} sar_cocpu_int_clr;
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union {
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struct {
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uint32_t pc : 13; /*cocpu Program counter*/
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uint32_t mem_vld : 1; /*cocpu mem valid output*/
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uint32_t mem_rdy : 1; /*cocpu mem ready input*/
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uint32_t mem_wen : 4; /*cocpu mem write enable output*/
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uint32_t mem_addr : 13; /*cocpu mem address output*/
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};
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uint32_t val;
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} sar_cocpu_debug;
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union {
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struct {
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uint32_t reserved0 : 28;
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uint32_t xpd_hall : 1; /*Power on hall sensor and connect to VP and VN*/
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uint32_t xpd_hall_force : 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
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uint32_t hall_phase : 1; /*Reverse phase of hall sensor*/
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uint32_t hall_phase_force : 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
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};
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uint32_t val;
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} sar_hall_ctrl;
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uint32_t sar_nouse;
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union {
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struct {
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uint32_t reserved0 : 27;
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uint32_t rtc_i2c_clk_en : 1;
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uint32_t reserved28 : 1;
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uint32_t tsens_clk_en : 1;
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uint32_t saradc_clk_en : 1;
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uint32_t iomux_clk_en : 1;
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};
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uint32_t val;
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} sar_peri_clk_gate_conf;
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union {
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struct {
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uint32_t reserved0 : 25;
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uint32_t reset : 1;
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uint32_t reserved26 : 1;
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uint32_t rtc_i2c_reset : 1;
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uint32_t reserved28 : 1;
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uint32_t tsens_reset : 1;
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uint32_t saradc_reset : 1;
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uint32_t reserved31 : 1;
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};
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uint32_t val;
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} sar_peri_reset_conf;
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union {
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struct {
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uint32_t touch_done_w1ts : 1;
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uint32_t touch_inactive_w1ts : 1;
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uint32_t touch_active_w1ts : 1;
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uint32_t saradc1_w1ts : 1;
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uint32_t saradc2_w1ts : 1;
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uint32_t tsens_w1ts : 1;
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uint32_t start_w1ts : 1;
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uint32_t sw_w1ts : 1;
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uint32_t swd_w1ts : 1;
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uint32_t touch_timeout_w1ts : 1;
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uint32_t touch_approach_loop_done_w1ts : 1;
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uint32_t touch_scan_done_w1ts : 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} sar_cocpu_int_ena_w1ts;
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union {
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struct {
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uint32_t touch_done_w1tc : 1;
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uint32_t touch_inactive_w1tc : 1;
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uint32_t touch_active_w1tc : 1;
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uint32_t saradc1_w1tc : 1;
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uint32_t saradc2_w1tc : 1;
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uint32_t tsens_w1tc : 1;
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uint32_t start_w1tc : 1;
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uint32_t sw_w1tc : 1;
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uint32_t swd_w1tc : 1;
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uint32_t touch_timeout_w1tc : 1;
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uint32_t touch_approach_loop_done_w1tc : 1;
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uint32_t touch_scan_done_w1tc : 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} sar_cocpu_int_ena_w1tc;
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union {
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struct {
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|
uint32_t debug_bit_sel : 5;
|
|
uint32_t reserved5 : 27;
|
|
};
|
|
uint32_t val;
|
|
} sar_debug_conf;
|
|
uint32_t reserved_118;
|
|
uint32_t reserved_11c;
|
|
uint32_t reserved_120;
|
|
uint32_t reserved_124;
|
|
uint32_t reserved_128;
|
|
uint32_t reserved_12c;
|
|
uint32_t reserved_130;
|
|
uint32_t reserved_134;
|
|
uint32_t reserved_138;
|
|
uint32_t reserved_13c;
|
|
uint32_t reserved_140;
|
|
uint32_t reserved_144;
|
|
uint32_t reserved_148;
|
|
uint32_t reserved_14c;
|
|
uint32_t reserved_150;
|
|
uint32_t reserved_154;
|
|
uint32_t reserved_158;
|
|
uint32_t reserved_15c;
|
|
uint32_t reserved_160;
|
|
uint32_t reserved_164;
|
|
uint32_t reserved_168;
|
|
uint32_t reserved_16c;
|
|
uint32_t reserved_170;
|
|
uint32_t reserved_174;
|
|
uint32_t reserved_178;
|
|
uint32_t reserved_17c;
|
|
uint32_t reserved_180;
|
|
uint32_t reserved_184;
|
|
uint32_t reserved_188;
|
|
uint32_t reserved_18c;
|
|
uint32_t reserved_190;
|
|
uint32_t reserved_194;
|
|
uint32_t reserved_198;
|
|
uint32_t reserved_19c;
|
|
uint32_t reserved_1a0;
|
|
uint32_t reserved_1a4;
|
|
uint32_t reserved_1a8;
|
|
uint32_t reserved_1ac;
|
|
uint32_t reserved_1b0;
|
|
uint32_t reserved_1b4;
|
|
uint32_t reserved_1b8;
|
|
uint32_t reserved_1bc;
|
|
uint32_t reserved_1c0;
|
|
uint32_t reserved_1c4;
|
|
uint32_t reserved_1c8;
|
|
uint32_t reserved_1cc;
|
|
uint32_t reserved_1d0;
|
|
uint32_t reserved_1d4;
|
|
uint32_t reserved_1d8;
|
|
uint32_t reserved_1dc;
|
|
uint32_t reserved_1e0;
|
|
uint32_t reserved_1e4;
|
|
uint32_t reserved_1e8;
|
|
uint32_t reserved_1ec;
|
|
uint32_t reserved_1f0;
|
|
uint32_t reserved_1f4;
|
|
uint32_t reserved_1f8;
|
|
union {
|
|
struct {
|
|
uint32_t sar_date : 28;
|
|
uint32_t reserved28 : 4;
|
|
};
|
|
uint32_t val;
|
|
} sardate;
|
|
} sens_dev_t;
|
|
extern sens_dev_t SENS;
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
|
|
|
|
#endif /*_SOC_SENS_STRUCT_H_ */
|