esp-idf/components/soc
2024-06-18 15:04:20 +08:00
..
esp32 fix(esp_hw_support): clear reserved interrupts that are not applicable for each target 2024-05-30 12:12:44 +08:00
esp32c2 fix(uart): correct C2 UART_BITRATE_MAX value 2024-04-24 16:19:41 +08:00
esp32c3 fix(esp_hw_support/sleep): stop TG0/TG1 watchdog if XTAL not power down in lightsleep 2024-06-04 21:30:28 +08:00
esp32c6 feat(uart): support uart module sleep retention on c6/h2 2024-06-18 15:04:20 +08:00
esp32h2 feat(uart): support uart module sleep retention on c6/h2 2024-06-18 15:04:20 +08:00
esp32p4 fix(gpio_etm): allow one GPIO binds to multiple ETM tasks 2024-04-24 16:01:34 +08:00
esp32s2 fix(esp_hw_support): clear reserved interrupts that are not applicable for each target 2024-05-30 12:12:44 +08:00
esp32s3 fix(esp_hw_support): clear reserved interrupts that are not applicable for each target 2024-05-30 12:12:44 +08:00
include/soc fix(soc): fixed uart_periph.h not including reg.h issue 2024-05-28 10:57:59 +08:00
linux/include/soc fix(console): enable to select UART1 port for console output 2023-11-30 11:26:09 +08:00
CMakeLists.txt refactor(soc): Rename usb_otg_periph to usb_dwc_periph 2024-02-19 15:45:04 +08:00
dport_access_common.c
Kconfig
linker.lf
lldesc.c
README.md

soc

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware