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fix(uart): correct C2 UART_BITRATE_MAX value
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@ -617,7 +617,7 @@ config SOC_UART_FIFO_LEN
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config SOC_UART_BITRATE_MAX
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int
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default 5000000
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default 2500000
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config SOC_UART_SUPPORT_WAKEUP_INT
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bool
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@ -190,9 +190,6 @@ typedef enum {
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UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F40M, /*!< UART source clock default choice is PLL_F40M */
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} soc_periph_uart_clk_src_legacy_t;
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/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
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/**
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@ -209,6 +206,8 @@ typedef enum {
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SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
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} soc_periph_spi_clk_src_t;
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/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of I2C
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*/
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@ -289,7 +289,7 @@
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#define SOC_UART_NUM (2)
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#define SOC_UART_HP_NUM (2)
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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#define SOC_UART_BITRATE_MAX (2500000) /*!< Max bit rate supported by UART */
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#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
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#define SOC_UART_SUPPORT_PLL_F40M_CLK (1) /*!< Support APB as the clock source */
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#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
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