esp-idf/components/ulp/ulp_riscv
Sudeep Mohanty f709faea7c ulp: Keep RTC_CNTL_COCPU_SHUT_RESET_EN set for ULP RISC-V
RTC_CNTL_COCPU_SHUT_RESET_EN register was being reset during ULP RISC-V
initialization which does not let the ULP RISC-V coprocessor to reset
after it goes to halt. For proper operation of the coprocessor, it must
be reset after each cycle and hence this commit keeps
RTC_CNTL_COCPU_SHUT_RESET_EN set.
2022-04-28 13:41:07 +05:30
..
include ULP: Add example of using GPIO to wakeup the ULP-RISCV processor 2022-02-28 14:15:25 +08:00
start.S ULP: add functions for stopping/restarting the ulp-riscv 2022-01-20 11:34:53 +08:00
ulp_riscv_utils.c ulp: Keep RTC_CNTL_COCPU_SHUT_RESET_EN set for ULP RISC-V 2022-04-28 13:41:07 +05:30
ulp_riscv.c ulp: Keep RTC_CNTL_COCPU_SHUT_RESET_EN set for ULP RISC-V 2022-04-28 13:41:07 +05:30