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https://github.com/espressif/esp-idf.git
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112 lines
3.1 KiB
C
112 lines
3.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "soc/soc_caps.h"
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#include "hal/parlio_types.h"
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#include "hal/parlio_hal.h"
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#include "hal/parlio_ll.h"
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#include "hal/dma_types.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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#include "rom/cache.h"
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#include "esp_heap_caps.h"
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#include "driver/parlio_types.h"
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#include "esp_private/periph_ctrl.h"
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#if CONFIG_PARLIO_ISR_IRAM_SAFE
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#define PARLIO_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define PARLIO_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
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#endif
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#if SOC_PARLIO_TX_RX_SHARE_INTERRUPT
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#define PARLIO_INTR_ALLOC_FLAG_SHARED ESP_INTR_FLAG_SHARED
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#else
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#define PARLIO_INTR_ALLOC_FLAG_SHARED 0
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#endif
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#if CONFIG_PARLIO_ISR_IRAM_SAFE
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#define PARLIO_INTR_ALLOC_FLAG (ESP_INTR_FLAG_LOWMED | PARLIO_INTR_ALLOC_FLAG_SHARED | ESP_INTR_FLAG_IRAM)
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#else
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#define PARLIO_INTR_ALLOC_FLAG (ESP_INTR_FLAG_LOWMED | PARLIO_INTR_ALLOC_FLAG_SHARED)
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#endif
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#if SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS == SOC_GDMA_BUS_AXI
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/* The parlio peripheral uses DMA via AXI bus, which requires the descriptor aligned with 8 */
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typedef dma_descriptor_align8_t parlio_dma_desc_t;
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#else
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typedef dma_descriptor_align4_t parlio_dma_desc_t;
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#endif
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#ifdef CACHE_LL_L2MEM_NON_CACHE_ADDR
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/* The descriptor address can be mapped by a fixed offset */
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#define PARLIO_GET_NON_CACHED_DESC_ADDR(desc) (desc ? (parlio_dma_desc_t *)(CACHE_LL_L2MEM_NON_CACHE_ADDR(desc)) : NULL)
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#else
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#define PARLIO_GET_NON_CACHED_DESC_ADDR(desc) (desc)
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#endif // CACHE_LL_L2MEM_NON_CACHE_ADDR
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#if SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS == SOC_GDMA_BUS_AXI
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#define PARLIO_DMA_DESC_ALIGNMENT 8
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#define PARLIO_DMA_DESC_SIZE 8
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#else
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#define PARLIO_DMA_DESC_ALIGNMENT 4
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#define PARLIO_DMA_DESC_SIZE sizeof(parlio_dma_desc_t)
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#endif
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#if SOC_PERIPH_CLK_CTRL_SHARED
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#define PARLIO_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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#define PARLIO_CLOCK_SRC_ATOMIC()
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#endif
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#if !SOC_RCC_IS_INDEPENDENT
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// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
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#define PARLIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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#define PARLIO_RCC_ATOMIC()
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#endif // SOC_RCC_IS_INDEPENDENT
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#define PARLIO_PM_LOCK_NAME_LEN_MAX 16
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum {
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PARLIO_TX_QUEUE_READY,
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PARLIO_TX_QUEUE_PROGRESS,
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PARLIO_TX_QUEUE_COMPLETE,
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PARLIO_TX_QUEUE_MAX,
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};
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typedef enum {
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PARLIO_TX_FSM_INIT_WAIT,
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PARLIO_TX_FSM_INIT,
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PARLIO_TX_FSM_ENABLE_WAIT,
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PARLIO_TX_FSM_ENABLE,
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PARLIO_TX_FSM_RUN_WAIT,
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PARLIO_TX_FSM_RUN,
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} parlio_tx_fsm_t;
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typedef struct parlio_group_t {
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int group_id; // group ID, index from 0
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portMUX_TYPE spinlock; // to protect per-group register level concurrent access
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parlio_hal_context_t hal; // hal layer for each group
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parlio_tx_unit_handle_t tx_units[SOC_PARLIO_TX_UNITS_PER_GROUP]; // tx unit handles
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} parlio_group_t;
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parlio_group_t *parlio_acquire_group_handle(int group_id);
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void parlio_release_group_handle(parlio_group_t *group);
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#ifdef __cplusplus
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}
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#endif
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