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fd5a63f31e
update efuse_reg.h & efuse_struct.h & references in rst file
14 KiB
14 KiB
1 | # field_name, | efuse_block, | bit_start, | bit_count, |comment # |
---|---|
2 | # | (EFUSE_BLK0 | (0..255) | (1..-) | # |
3 | # | EFUSE_BLK1 | |MAX_BLK_LEN*| # |
4 | # | ... | | | # |
5 | # | EFUSE_BLK10)| | | # |
6 | ########################################################################## |
7 | # !!!!!!!!!!! # |
8 | # this will generate new source files, next rebuild all the sources. |
9 | # !!!!!!!!!!! # |
10 | # EFUSE_RD_REPEAT_DATA BLOCK # |
11 | ############################## |
12 | # EFUSE_RD_WR_DIS_REG # |
13 | # EFUSE_WR_DIS [WR_DIS 0 32] # |
14 | WR_DIS_RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 |
15 | WR_DIS_GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT |
16 | WR_DIS_GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL |
17 | WR_DIS_SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT |
18 | WR_DIS_SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 |
19 | WR_DIS_SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 |
20 | WR_DIS_SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 |
21 | WR_DIS_KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 |
22 | WR_DIS_KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 |
23 | WR_DIS_KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 |
24 | WR_DIS_KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 |
25 | WR_DIS_KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 |
26 | WR_DIS_KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 |
27 | WR_DIS_SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN |
28 | WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE |
29 | WR_DIS_GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION |
30 | WR_DIS_BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS |
31 | WR_DIS_SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 |
32 | WR_DIS_USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA |
33 | WR_DIS_KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 |
34 | WR_DIS_KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 |
35 | WR_DIS_KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 |
36 | WR_DIS_KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 |
37 | WR_DIS_KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 |
38 | WR_DIS_KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 |
39 | WR_DIS_SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 |
40 | # EFUSE_RD_REPEAT_DATA0_REG # |
41 | # [RD_DIS 0 7] # |
42 | RD_DIS_KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 |
43 | RD_DIS_KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 |
44 | RD_DIS_KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 |
45 | RD_DIS_KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 |
46 | RD_DIS_KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 |
47 | RD_DIS_KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 |
48 | RD_DIS_SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 |
49 | DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache |
50 | DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG |
51 | DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode |
52 | DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE |
53 | DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function |
54 | DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function |
55 | DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function |
56 | JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. |
57 | SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. |
58 | DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently. |
59 | DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes. |
60 | USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. |
61 | USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. |
62 | USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins |
63 | VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio |
64 | BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enable btlc gpio |
65 | POWERGLITCH_EN, EFUSE_BLK0, 61, 1, Set this bit to enable power glitch function |
66 | POWER_GLITCH_DSENSE, EFUSE_BLK0, 62, 2, Sample delay configuration of power glitch |
67 | # EFUSE_RD_REPEAT_DATA1_REG # |
68 | WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold |
69 | SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable |
70 | SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key |
71 | SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key |
72 | SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key |
73 | KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose |
74 | KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose |
75 | # EFUSE_RD_REPEAT_DATA2_REG # |
76 | KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose |
77 | KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose |
78 | KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose |
79 | KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose |
80 | SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable |
81 | SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke |
82 | FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms |
83 | # EFUSE_RD_REPEAT_DATA3_REG # |
84 | DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 |
85 | DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 |
86 | UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, 0: UART0. 1: UART1 |
87 | FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode |
88 | DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB |
89 | ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode |
90 | UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. |
91 | PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. |
92 | FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line |
93 | FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, Flash page size |
94 | FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enable ECC for flash boot |
95 | FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot |
96 | SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback |
97 | # EFUSE_RD_REPEAT_DATA4_REG # |
98 | # MAC_SPI_SYS BLOCK# |
99 | ####################### |
100 | MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] |
101 | , EFUSE_BLK1, 32, 8, Factory MAC addr [1] |
102 | , EFUSE_BLK1, 24, 8, Factory MAC addr [2] |
103 | , EFUSE_BLK1, 16, 8, Factory MAC addr [3] |
104 | , EFUSE_BLK1, 8, 8, Factory MAC addr [4] |
105 | , EFUSE_BLK1, 0, 8, Factory MAC addr [5] |
106 | SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK |
107 | SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) |
108 | SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) |
109 | SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS |
110 | SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) |
111 | SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) |
112 | SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS |
113 | SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 |
114 | SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 |
115 | SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 |
116 | SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 |
117 | WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version |
118 | PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3 |
119 | BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version |
120 | # SYS_DATA_PART1 BLOCK# - System configuration |
121 | ####################### |
122 | OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID |
123 | BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2 |
124 | TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data |
125 | OCODE, EFUSE_BLK2, 140, 8, ADC OCode |
126 | ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0 |
127 | ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1 |
128 | ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2 |
129 | ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3 |
130 | ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0 |
131 | ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1 |
132 | ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2 |
133 | ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3 |
134 | ################ |
135 | USER_DATA, EFUSE_BLK3, 0, 256, User data |
136 | KEY0, EFUSE_BLK4, 0, 256, Key0 or user data |
137 | KEY1, EFUSE_BLK5, 0, 256, Key1 or user data |
138 | KEY2, EFUSE_BLK6, 0, 256, Key2 or user data |
139 | KEY3, EFUSE_BLK7, 0, 256, Key3 or user data |
140 | KEY4, EFUSE_BLK8, 0, 256, Key4 or user data |
141 | KEY5, EFUSE_BLK9, 0, 256, Key5 or user data |
142 | SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration |
143 | # AUTO CONFIG DIG&RTC DBIAS# |
144 | ################ |
145 | K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO |
146 | K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO |
147 | V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20 |
148 | V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20 |
149 | DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt |
150 | THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt |