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https://github.com/espressif/esp-idf.git
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101 lines
3.1 KiB
C
101 lines
3.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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#include "soc/sensitive_reg.h"
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#include "esp32c3/rom/cache.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef union {
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struct {
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uint32_t cat0 : 2;
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uint32_t cat1 : 2;
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uint32_t cat2 : 2;
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uint32_t res0 : 8;
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uint32_t splitaddr : 8;
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uint32_t res1 : 10;
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};
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uint32_t val;
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} constrain_reg_fields_t;
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#ifndef I_D_SRAM_SEGMENT_SIZE
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#define I_D_SRAM_SEGMENT_SIZE 0x20000
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#endif
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#define I_D_SPLIT_LINE_SHIFT 0x9
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#define I_D_FAULT_ADDR_SHIFT 0x2
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#define DRAM_SRAM_START 0x3FC7C000
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#ifndef MAP_DRAM_TO_IRAM
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#define MAP_DRAM_TO_IRAM(addr) (addr - DRAM_SRAM_START + SOC_IRAM_LOW)
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#endif
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#ifndef MAP_IRAM_TO_DRAM
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#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_IRAM_LOW + DRAM_SRAM_START)
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#endif
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//IRAM0
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//16kB (ICACHE)
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#define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000
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#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF
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//128kB (LEVEL 1)
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#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000
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#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF
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//128kB (LEVEL 2)
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#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000
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#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF
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//128kB (LEVEL 3)
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#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000
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#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF
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//permission bits
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4
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//DRAM0
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//16kB ICACHE not available from DRAM0
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//128kB (LEVEL 1)
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#define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000
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#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF
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//128kB (LEVEL 2)
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#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000
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#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF
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//128kB (LEVEL 3)
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#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000
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#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF
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#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1
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#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2
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//RTC FAST
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//permission bits
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#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1
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#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2
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#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4
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#define AREA_LOW 0
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#define AREA_HIGH 1
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#ifdef __cplusplus
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}
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#endif
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