mirror of
https://github.com/espressif/esp-idf.git
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365 lines
14 KiB
C
365 lines
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "hal/adc_hal.h"
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#include "hal/adc_hal_conf.h"
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#include "hal/assert.h"
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#include "soc/lldesc.h"
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#include "soc/soc_caps.h"
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#if CONFIG_IDF_TARGET_ESP32
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//ADC utilises I2S0 DMA on ESP32
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#include "hal/i2s_hal.h"
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#include "hal/i2s_types.h"
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#include "soc/i2s_struct.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2
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//ADC utilises SPI3 DMA on ESP32S2
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#include "hal/spi_ll.h"
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#include "soc/spi_struct.h"
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#endif
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/*---------------------------------------------------------------
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Define all ADC DMA required operations here
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---------------------------------------------------------------*/
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#if SOC_GDMA_SUPPORTED
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#define adc_dma_ll_rx_clear_intr(dev, chan, mask) gdma_ll_rx_clear_interrupt_status(dev, chan, mask)
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#define adc_dma_ll_rx_enable_intr(dev, chan, mask) gdma_ll_rx_enable_interrupt(dev, chan, mask, true)
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#define adc_dma_ll_rx_disable_intr(dev, chan, mask) gdma_ll_rx_enable_interrupt(dev, chan, mask, false)
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#define adc_dma_ll_rx_reset_channel(dev, chan) gdma_ll_rx_reset_channel(dev, chan)
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#define adc_dma_ll_rx_stop(dev, chan) gdma_ll_rx_stop(dev, chan)
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#define adc_dma_ll_rx_start(dev, chan, addr) do { \
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gdma_ll_rx_set_desc_addr(dev, chan, (uint32_t)addr); \
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gdma_ll_rx_start(dev, chan); \
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} while (0)
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#define adc_ll_digi_dma_set_eof_num(dev, num) adc_ll_digi_dma_set_eof_num(num)
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#define adc_ll_digi_reset(dev) adc_ll_digi_reset()
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#define adc_ll_digi_trigger_enable(dev) adc_ll_digi_trigger_enable()
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#define adc_ll_digi_trigger_disable(dev) adc_ll_digi_trigger_disable()
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//ADC utilises SPI3 DMA on ESP32S2
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define adc_dma_ll_rx_get_intr(dev, mask) spi_ll_get_intr(dev, mask)
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#define adc_dma_ll_rx_clear_intr(dev, chan, mask) spi_ll_clear_intr(dev, mask)
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#define adc_dma_ll_rx_enable_intr(dev, chan, mask) spi_ll_enable_intr(dev, mask)
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#define adc_dma_ll_rx_disable_intr(dev, chan, mask) spi_ll_disable_intr(dev, mask)
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#define adc_dma_ll_rx_reset_channel(dev, chan) spi_dma_ll_rx_reset(dev, chan)
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#define adc_dma_ll_rx_stop(dev, chan) spi_dma_ll_rx_stop(dev, chan)
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#define adc_dma_ll_rx_start(dev, chan, addr) spi_dma_ll_rx_start(dev, chan, addr)
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#define adc_dma_ll_get_in_suc_eof_desc_addr(dev, chan) spi_dma_ll_get_in_suc_eof_desc_addr(dev, chan)
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#define adc_ll_digi_dma_set_eof_num(dev, num) adc_ll_digi_dma_set_eof_num(num)
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#define adc_ll_digi_reset(dev) adc_ll_digi_reset()
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#define adc_ll_digi_trigger_enable(dev) adc_ll_digi_trigger_enable()
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#define adc_ll_digi_trigger_disable(dev) adc_ll_digi_trigger_disable()
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//ADC utilises I2S0 DMA on ESP32
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#else //CONFIG_IDF_TARGET_ESP32
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#define adc_dma_ll_rx_get_intr(dev, mask) ({i2s_ll_get_intr_status(dev) & mask;})
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#define adc_dma_ll_rx_clear_intr(dev, chan, mask) i2s_ll_clear_intr_status(dev, mask)
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#define adc_dma_ll_rx_enable_intr(dev, chan, mask) do {((i2s_dev_t *)(dev))->int_ena.val |= mask;} while (0)
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#define adc_dma_ll_rx_disable_intr(dev, chan, mask) do {((i2s_dev_t *)(dev))->int_ena.val &= ~mask;} while (0)
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#define adc_dma_ll_rx_reset_channel(dev, chan) i2s_ll_rx_reset_dma(dev)
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#define adc_dma_ll_rx_stop(dev, chan) i2s_ll_rx_stop_link(dev)
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#define adc_dma_ll_rx_start(dev, chan, address) do { \
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((i2s_dev_t *)(dev))->in_link.addr = (uint32_t)(address); \
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i2s_ll_enable_dma(dev, 1); \
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((i2s_dev_t *)(dev))->in_link.start = 1; \
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} while (0)
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#define adc_dma_ll_get_in_suc_eof_desc_addr(dev, chan) ({uint32_t addr; i2s_ll_rx_get_eof_des_addr(dev, &addr); addr;})
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#define adc_ll_digi_dma_set_eof_num(dev, num) do {((i2s_dev_t *)(dev))->rx_eof_num = num;} while (0)
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#define adc_ll_digi_reset(dev) do { \
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i2s_ll_rx_reset(dev); \
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i2s_ll_rx_reset_fifo(dev); \
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} while (0)
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#define adc_ll_digi_trigger_enable(dev) i2s_ll_rx_start(dev)
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#define adc_ll_digi_trigger_disable(dev) i2s_ll_rx_stop(dev)
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#define adc_ll_digi_dma_enable() adc_ll_digi_set_data_source(1) //Will this influence I2S0
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#define adc_ll_digi_dma_disable() adc_ll_digi_set_data_source(0)
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//ESP32 ADC uses the DMA through I2S. The I2S needs to be configured.
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#define I2S_BASE_CLK (2*APB_CLK_FREQ)
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#define SAMPLE_BITS 16
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#define ADC_LL_CLKM_DIV_NUM_DEFAULT 2
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#define ADC_LL_CLKM_DIV_B_DEFAULT 0
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#define ADC_LL_CLKM_DIV_A_DEFAULT 1
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#endif
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void adc_hal_dma_ctx_config(adc_hal_dma_ctx_t *hal, const adc_hal_dma_config_t *config)
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{
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hal->desc_dummy_head.next = hal->rx_desc;
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hal->dev = config->dev;
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hal->eof_desc_num = config->eof_desc_num;
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hal->eof_step = config->eof_step;
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hal->dma_chan = config->dma_chan;
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hal->eof_num = config->eof_num;
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}
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void adc_hal_digi_init(adc_hal_dma_ctx_t *hal)
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{
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// Set internal FSM wait time, fixed value.
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adc_ll_digi_set_fsm_time(ADC_HAL_FSM_RSTB_WAIT_DEFAULT, ADC_HAL_FSM_START_WAIT_DEFAULT,
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ADC_HAL_FSM_STANDBY_WAIT_DEFAULT);
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adc_ll_set_sample_cycle(ADC_HAL_SAMPLE_CYCLE_DEFAULT);
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adc_hal_pwdet_set_cct(ADC_HAL_PWDET_CCT_DEFAULT);
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adc_ll_digi_output_invert(ADC_UNIT_1, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_1));
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adc_ll_digi_output_invert(ADC_UNIT_2, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_2));
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adc_ll_digi_set_clk_div(ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT);
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adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, ADC_HAL_DMA_INTR_MASK);
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adc_dma_ll_rx_enable_intr(hal->dev, hal->dma_chan, ADC_HAL_DMA_INTR_MASK);
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adc_ll_digi_dma_set_eof_num(hal->dev, hal->eof_num);
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#if CONFIG_IDF_TARGET_ESP32
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i2s_ll_rx_set_sample_bit(hal->dev, SAMPLE_BITS, SAMPLE_BITS);
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i2s_ll_rx_enable_mono_mode(hal->dev, 1);
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i2s_ll_rx_force_enable_fifo_mod(hal->dev, 1);
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i2s_ll_enable_builtin_adc(hal->dev, 1);
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#endif
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adc_oneshot_ll_disable_all_unit();
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}
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void adc_hal_digi_deinit(adc_hal_dma_ctx_t *hal)
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{
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adc_ll_digi_trigger_disable(hal->dev);
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adc_ll_digi_dma_disable();
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adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
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adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
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adc_ll_digi_reset(hal->dev);
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adc_ll_digi_controller_clk_disable();
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}
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/*---------------------------------------------------------------
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DMA read
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---------------------------------------------------------------*/
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static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t convert_mode)
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{
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#if CONFIG_IDF_TARGET_ESP32
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return ADC_LL_DIGI_CONV_ONLY_ADC1;
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#endif
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#if (SOC_ADC_DIGI_CONTROLLER_NUM == 1)
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return ADC_LL_DIGI_CONV_ALTER_UNIT;
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#elif (SOC_ADC_DIGI_CONTROLLER_NUM >= 2)
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switch (convert_mode) {
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case ADC_CONV_SINGLE_UNIT_1:
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return ADC_LL_DIGI_CONV_ONLY_ADC1;
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case ADC_CONV_SINGLE_UNIT_2:
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return ADC_LL_DIGI_CONV_ONLY_ADC2;
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case ADC_CONV_BOTH_UNIT:
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return ADC_LL_DIGI_CONV_BOTH_UNIT;
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case ADC_CONV_ALTER_UNIT:
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return ADC_LL_DIGI_CONV_ALTER_UNIT;
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default:
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abort();
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}
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#endif
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}
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/**
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* For esp32s2 and later chips
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* - Set ADC digital controller clock division factor. The clock is divided from `APLL` or `APB` clock.
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* Expression: controller_clk = APLL/APB * (div_num + div_a / div_b + 1).
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* - Enable clock and select clock source for ADC digital controller.
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* For esp32, use I2S clock
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*/
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static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, uint32_t freq)
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{
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#if !CONFIG_IDF_TARGET_ESP32
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uint32_t interval = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / freq;
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//set sample interval
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adc_ll_digi_set_trigger_interval(interval);
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//Here we set the clock divider factor to make the digital clock to 5M Hz
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adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT);
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adc_ll_digi_clk_sel(0); //use APB
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#else
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i2s_ll_rx_clk_set_src(hal->dev, I2S_CLK_SRC_DEFAULT); /*!< Clock from PLL_D2_CLK(160M)*/
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uint32_t bclk_div = 16;
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uint32_t bclk = freq * 2;
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uint32_t mclk = bclk * bclk_div;
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i2s_ll_mclk_div_t mclk_div = {};
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i2s_hal_calc_mclk_precise_division(I2S_BASE_CLK, mclk, &mclk_div);
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i2s_ll_rx_set_mclk(hal->dev, &mclk_div);
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i2s_ll_rx_set_bck_div_num(hal->dev, bclk_div);
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#endif
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}
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void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg)
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{
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#if (SOC_ADC_DIGI_CONTROLLER_NUM == 1)
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//Only one pattern table, this variable is for readability
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const int pattern_both = 0;
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adc_ll_digi_clear_pattern_table(pattern_both);
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adc_ll_digi_set_pattern_table_len(pattern_both, cfg->adc_pattern_len);
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for (int i = 0; i < cfg->adc_pattern_len; i++) {
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adc_ll_digi_set_pattern_table(pattern_both, i, cfg->adc_pattern[i]);
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}
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#elif (SOC_ADC_DIGI_CONTROLLER_NUM >= 2)
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uint32_t adc1_pattern_idx = 0;
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uint32_t adc2_pattern_idx = 0;
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adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
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adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
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for (int i = 0; i < cfg->adc_pattern_len; i++) {
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if (cfg->adc_pattern[i].unit == ADC_UNIT_1) {
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adc_ll_digi_set_pattern_table(ADC_UNIT_1, adc1_pattern_idx, cfg->adc_pattern[i]);
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adc1_pattern_idx++;
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} else if (cfg->adc_pattern[i].unit == ADC_UNIT_2) {
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adc_ll_digi_set_pattern_table(ADC_UNIT_2, adc2_pattern_idx, cfg->adc_pattern[i]);
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adc2_pattern_idx++;
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} else {
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abort();
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}
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}
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adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, adc1_pattern_idx);
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adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, adc2_pattern_idx);
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#endif
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adc_ll_digi_convert_limit_enable(ADC_LL_DEFAULT_CONV_LIMIT_EN);
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adc_ll_digi_set_convert_limit_num(ADC_LL_DEFAULT_CONV_LIMIT_NUM);
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adc_ll_digi_set_convert_mode(get_convert_mode(cfg->conv_mode));
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//clock and sample frequency
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adc_hal_digi_sample_freq_config(hal, cfg->sample_freq_hz);
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}
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static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *data_buf, uint32_t per_eof_size, uint32_t eof_step, uint32_t eof_num)
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{
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HAL_ASSERT(((uint32_t)data_buf % 4) == 0);
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HAL_ASSERT((per_eof_size % 4) == 0);
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uint32_t n = 0;
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dma_descriptor_t *desc_head = desc;
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while (eof_num--) {
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uint32_t eof_size = per_eof_size;
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for (int i = 0; i < eof_step; i++) {
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uint32_t this_len = eof_size;
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if (this_len > DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED) {
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this_len = DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
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}
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desc[n] = (dma_descriptor_t) {
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.dw0.size = this_len,
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.dw0.length = 0,
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.dw0.suc_eof = 0,
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.dw0.owner = 1,
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.buffer = data_buf,
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.next = &desc[n+1]
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};
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eof_size -= this_len;
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data_buf += this_len;
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n++;
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}
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}
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desc[n-1].next = desc_head;
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}
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void adc_hal_digi_start(adc_hal_dma_ctx_t *hal, uint8_t *data_buf)
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{
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//stop peripheral and DMA
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adc_hal_digi_stop(hal);
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//reset DMA
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adc_dma_ll_rx_reset_channel(hal->dev, hal->dma_chan);
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//reset peripheral
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adc_ll_digi_reset(hal->dev);
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//reset the current descriptor address
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hal->cur_desc_ptr = &hal->desc_dummy_head;
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adc_hal_digi_dma_link_descriptors(hal->rx_desc, data_buf, hal->eof_num * SOC_ADC_DIGI_DATA_BYTES_PER_CONV, hal->eof_step, hal->eof_desc_num);
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//start DMA
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adc_dma_ll_rx_start(hal->dev, hal->dma_chan, (lldesc_t *)hal->rx_desc);
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//connect DMA and peripheral
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adc_ll_digi_dma_enable();
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//start ADC
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adc_ll_digi_trigger_enable(hal->dev);
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}
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#if !SOC_GDMA_SUPPORTED
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intptr_t adc_hal_get_desc_addr(adc_hal_dma_ctx_t *hal)
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{
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return adc_dma_ll_get_in_suc_eof_desc_addr(hal->dev, hal->dma_chan);
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}
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bool adc_hal_check_event(adc_hal_dma_ctx_t *hal, uint32_t mask)
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{
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return adc_dma_ll_rx_get_intr(hal->dev, mask);
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}
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#endif //#if !SOC_GDMA_SUPPORTED
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adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len)
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{
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HAL_ASSERT(hal->cur_desc_ptr);
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if (!hal->cur_desc_ptr->next) {
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return ADC_HAL_DMA_DESC_NULL;
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}
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if ((intptr_t)hal->cur_desc_ptr == eof_desc_addr) {
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return ADC_HAL_DMA_DESC_WAITING;
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}
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uint8_t *buffer_start = NULL;
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uint32_t eof_len = 0;
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dma_descriptor_t *eof_desc = hal->cur_desc_ptr;
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//Find the eof list start
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eof_desc = eof_desc->next;
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eof_desc->dw0.owner = 1;
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buffer_start = eof_desc->buffer;
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eof_len += eof_desc->dw0.length;
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if ((intptr_t)eof_desc == eof_desc_addr) {
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goto valid;
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}
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//Find the eof list end
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for (int i = 1; i < hal->eof_step; i++) {
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eof_desc = eof_desc->next;
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eof_desc->dw0.owner = 1;
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eof_len += eof_desc->dw0.length;
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if ((intptr_t)eof_desc == eof_desc_addr) {
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goto valid;
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}
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}
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valid:
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hal->cur_desc_ptr = eof_desc;
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*buffer = buffer_start;
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*len = eof_len;
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return ADC_HAL_DMA_DESC_VALID;
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}
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void adc_hal_digi_clr_intr(adc_hal_dma_ctx_t *hal, uint32_t mask)
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{
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adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, mask);
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}
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void adc_hal_digi_dis_intr(adc_hal_dma_ctx_t *hal, uint32_t mask)
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{
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adc_dma_ll_rx_disable_intr(hal->dev, hal->dma_chan, mask);
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}
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void adc_hal_digi_stop(adc_hal_dma_ctx_t *hal)
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{
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//stop ADC
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adc_ll_digi_trigger_disable(hal->dev);
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//stop DMA
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adc_dma_ll_rx_stop(hal->dev, hal->dma_chan);
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//disconnect DMA and peripheral
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adc_ll_digi_dma_disable();
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}
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