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i2s: fixed i2s_ll compiling failure under C++ evironment
Closes: https://github.com/espressif/esp-idf/issues/11625
This commit is contained in:
laokaiyao
parent
96119acc8b
commit
a2cf3ae4df
@ -74,7 +74,7 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
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#if SOC_I2S_HW_VERSION_2
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/* Work around for PDM TX clock, overwrite the raw division directly to reduce the noise
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* This set of coefficients is a special division to reduce the background noise in PDM TX mode */
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i2s_ll_tx_set_raw_clk_div(handle->controller->hal.dev, 1, 1, 0, 0);
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i2s_ll_tx_set_raw_clk_div(handle->controller->hal.dev, clk_info.mclk_div, 1, 1, 0, 0);
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#endif
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portEXIT_CRITICAL(&g_i2s.spinlock);
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -14,7 +14,7 @@
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#if CONFIG_IDF_TARGET_ESP32
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//ADC utilises I2S0 DMA on ESP32
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#include "hal/i2s_ll.h"
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#include "hal/i2s_hal.h"
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#include "hal/i2s_types.h"
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#include "soc/i2s_struct.h"
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#endif
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@ -184,8 +184,9 @@ static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, uint32_t fre
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uint32_t bclk_div = 16;
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uint32_t bclk = freq * 2;
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uint32_t mclk = bclk * bclk_div;
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uint32_t mclk_div = I2S_BASE_CLK / mclk;
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i2s_ll_rx_set_mclk(hal->dev, I2S_BASE_CLK, mclk, mclk_div);
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i2s_ll_mclk_div_t mclk_div = {};
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i2s_hal_calc_mclk_precise_division(I2S_BASE_CLK, mclk, &mclk_div);
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i2s_ll_rx_set_mclk(hal->dev, &mclk_div);
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i2s_ll_rx_set_bck_div_num(hal->dev, bclk_div);
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#endif
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}
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -45,11 +45,14 @@ extern "C" {
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#define I2S_LL_TX_EVENT_MASK I2S_LL_EVENT_TX_EOF
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#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
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/* I2S clock configuration structure */
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/**
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* @brief I2S clock configuration structure
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* @note Fmclk = Fsclk /(integ+numer/denom)
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*/
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typedef struct {
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uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
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uint16_t a;
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uint16_t b; // The decimal part of module clock divider, the decimal is: b/a
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uint16_t integ; // Integer part of I2S module clock divider
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uint16_t denom; // Denominator part of I2S module clock divider
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uint16_t numer; // Numerator part of I2S module clock divider
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} i2s_ll_mclk_div_t;
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/**
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@ -282,54 +285,6 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
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hw->sample_rate_conf.tx_bck_div_num = val;
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}
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/**
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* @brief Configure I2S TX module clock divider
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* @note mclk on ESP32 is shared by both TX and RX channel
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*
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* @param hw Peripheral I2S hardware instance address.
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* @param sclk system clock, 0 means use apll
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* @param mclk module clock
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* @param mclk_div integer part of the division from sclk to mclk
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*/
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static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
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{
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int ma = 0;
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int mb = 0;
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int denominator = 1;
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int numerator = 0;
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uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
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if (!freq_diff) {
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goto finish;
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}
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float decimal = freq_diff / (float)mclk;
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// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
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if (decimal > 125.0 / 126.0) {
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mclk_div++;
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goto finish;
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}
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uint32_t min = ~0;
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for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
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int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
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ma = freq_diff * a;
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mb = mclk * b;
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if (ma == mb) {
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denominator = a;
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numerator = b;
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goto finish;
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}
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if (abs((mb - ma)) < min) {
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denominator = a;
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numerator = b;
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min = abs(mb - ma);
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}
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}
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finish:
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, mclk_div);
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hw->clkm_conf.clkm_div_b = numerator;
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hw->clkm_conf.clkm_div_a = denominator;
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}
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/**
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* @brief Configure I2S module clock divider
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* @note mclk on ESP32 is shared by both TX and RX channel
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@ -347,6 +302,23 @@ static inline void i2s_ll_set_raw_mclk_div(i2s_dev_t *hw, uint32_t mclk_div, uin
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hw->clkm_conf.clkm_div_a = a;
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}
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/**
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* @brief Configure I2S TX module clock divider
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* @note mclk on ESP32 is shared by both TX and RX channel
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*
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* @param hw Peripheral I2S hardware instance address.
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* @param mclk_div The mclk division coefficients
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*/
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static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
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{
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/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
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* Set to particular coefficients first then update to the target coefficients,
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* otherwise the clock division might be inaccurate.
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* the general idea is to set a value that unlike to calculate from the regular decimal */
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i2s_ll_set_raw_mclk_div(hw, 7, 47, 3);
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i2s_ll_set_raw_mclk_div(hw, mclk_div->integ, mclk_div->denom, mclk_div->numer);
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}
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/**
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* @brief Set I2S rx bck div num
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*
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@ -363,13 +335,12 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
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* @note mclk on ESP32 is shared by both TX and RX channel
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*
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* @param hw Peripheral I2S hardware instance address.
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* @param sclk system clock, 0 means use apll
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* @param mclk module clock
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* @param mclk_div integer part of the division from sclk to mclk
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* @param mclk_div The mclk division coefficients
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*/
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static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
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static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
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{
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i2s_ll_tx_set_mclk(hw, sclk, mclk, mclk_div);
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// TX and RX channel on ESP32 shares a same mclk
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i2s_ll_tx_set_mclk(hw, mclk_div);
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}
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/**
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@ -381,11 +352,13 @@ static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
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*/
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static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
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{
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uint32_t int_ena_mask = hw->int_ena.val;
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if (en) {
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hw->int_ena.val |= mask;
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int_ena_mask |= mask;
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} else {
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hw->int_ena.val &= ~mask;
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int_ena_mask &= ~mask;
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}
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hw->int_ena.val = int_ena_mask;
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}
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/**
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -32,11 +32,14 @@ extern "C" {
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#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9)
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#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
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/* I2S clock configuration structure */
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/**
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* @brief I2S clock configuration structure
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* @note Fmclk = Fsclk /(integ+numer/denom)
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*/
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typedef struct {
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uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
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uint16_t a;
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uint16_t b; // The decimal part of module clock divider, the decimal is: b/a
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uint16_t integ; // Integer part of I2S module clock divider
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uint16_t denom; // Denominator part of I2S module clock divider
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uint16_t numer; // Numerator part of I2S module clock divider
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} i2s_ll_mclk_div_t;
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/**
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@ -222,96 +225,74 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
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* @brief Set I2S tx raw clock division
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*
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* @param hw Peripheral I2S hardware instance address.
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* @param div_int Integer part of division
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* @param x div x
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* @param y div y
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* @param z div z
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* @param yn1 yn1
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*/
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static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
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static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
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{
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hw->tx_clkm_div_conf.tx_clkm_div_x = x;
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hw->tx_clkm_div_conf.tx_clkm_div_y = y;
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hw->tx_clkm_div_conf.tx_clkm_div_z = z;
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hw->tx_clkm_div_conf.tx_clkm_div_yn1 = yn1;
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/* Set the integer part of mclk division */
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, div_int);
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/* Set the decimal part of the mclk division */
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typeof(hw->tx_clkm_div_conf) div = {};
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div.tx_clkm_div_x = x;
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div.tx_clkm_div_y = y;
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div.tx_clkm_div_z = z;
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div.tx_clkm_div_yn1 = yn1;
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hw->tx_clkm_div_conf.val = div.val;
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}
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/**
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* @brief Set I2S rx raw clock division
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*
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* @param hw Peripheral I2S hardware instance address.
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* @param div_int Integer part of division
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* @param x div x
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* @param y div y
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* @param z div z
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* @param yn1 yn1
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*/
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static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
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static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
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{
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hw->rx_clkm_div_conf.rx_clkm_div_x = x;
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hw->rx_clkm_div_conf.rx_clkm_div_y = y;
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hw->rx_clkm_div_conf.rx_clkm_div_z = z;
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hw->rx_clkm_div_conf.rx_clkm_div_yn1 = yn1;
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/* Set the integer part of mclk division */
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, div_int);
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/* Set the decimal part of the mclk division */
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typeof(hw->rx_clkm_div_conf) div = {};
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div.rx_clkm_div_x = x;
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div.rx_clkm_div_y = y;
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div.rx_clkm_div_z = z;
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div.rx_clkm_div_yn1 = yn1;
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hw->rx_clkm_div_conf.val = div.val;
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}
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/**
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* @brief Configure I2S TX module clock divider
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*
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* @param hw Peripheral I2S hardware instance address.
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* @param sclk system clock, 0 means use apll
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* @param mclk module clock
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* @param mclk_div integer part of the division from sclk to mclk
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* @param mclk_div The mclk division coefficients
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*/
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static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
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static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
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{
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int ma = 0;
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int mb = 0;
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int denominator = 1;
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int numerator = 0;
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/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
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* Set to particular coefficients first then update to the target coefficients,
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* otherwise the clock division might be inaccurate.
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* the general idea is to set a value that impossible to calculate from the regular decimal */
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i2s_ll_tx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
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uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
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if (!freq_diff) {
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goto finish;
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uint32_t div_x = 0;
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uint32_t div_y = 0;
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uint32_t div_z = 0;
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uint32_t div_yn1 = 0;
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/* If any of denominator and numerator is 0, set all the coefficients to 0 */
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if (mclk_div->denom && mclk_div->numer) {
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div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
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div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
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div_x = mclk_div->denom / div_z - 1;
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div_y = mclk_div->denom % div_z;
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}
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float decimal = freq_diff / (float)mclk;
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// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
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if (decimal > 125.0 / 126.0) {
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mclk_div++;
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goto finish;
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}
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uint32_t min = ~0;
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for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
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int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
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ma = freq_diff * a;
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mb = mclk * b;
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if (ma == mb) {
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denominator = a;
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numerator = b;
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goto finish;
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}
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if (abs((mb - ma)) < min) {
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denominator = a;
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numerator = b;
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min = abs(mb - ma);
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}
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}
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finish:
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if (denominator == 0 || numerator == 0) {
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hw->tx_clkm_div_conf.tx_clkm_div_x = 0;
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hw->tx_clkm_div_conf.tx_clkm_div_y = 0;
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hw->tx_clkm_div_conf.tx_clkm_div_z = 0;
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} else {
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if (numerator > denominator / 2) {
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hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / (denominator - numerator) - 1;
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hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % (denominator - numerator);
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hw->tx_clkm_div_conf.tx_clkm_div_z = denominator - numerator;
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hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 1;
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} else {
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hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / numerator - 1;
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hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % numerator;
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hw->tx_clkm_div_conf.tx_clkm_div_z = numerator;
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hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
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}
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
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i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
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}
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/**
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@ -330,62 +311,28 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
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* @note mclk on ESP32 is shared by both TX and RX channel
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*
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* @param hw Peripheral I2S hardware instance address.
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* @param sclk system clock, 0 means use apll
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* @param mclk module clock
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* @param mclk_div integer part of the division from sclk to mclk
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* @param mclk_div The mclk division coefficients
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*/
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static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
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static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
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{
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int ma = 0;
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int mb = 0;
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int denominator = 1;
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int numerator = 0;
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/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
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* Set to particular coefficients first then update to the target coefficients,
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* otherwise the clock division might be inaccurate.
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* the general idea is to set a value that impossible to calculate from the regular decimal */
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i2s_ll_rx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
|
||||
|
||||
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
|
||||
if (!freq_diff) {
|
||||
goto finish;
|
||||
uint32_t div_x = 0;
|
||||
uint32_t div_y = 0;
|
||||
uint32_t div_z = 0;
|
||||
uint32_t div_yn1 = 0;
|
||||
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
|
||||
if (mclk_div->denom && mclk_div->numer) {
|
||||
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
|
||||
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
|
||||
div_x = mclk_div->denom / div_z - 1;
|
||||
div_y = mclk_div->denom % div_z;
|
||||
}
|
||||
float decimal = freq_diff / (float)mclk;
|
||||
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
|
||||
if (decimal > 125.0 / 126.0) {
|
||||
mclk_div++;
|
||||
goto finish;
|
||||
}
|
||||
uint32_t min = ~0;
|
||||
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
|
||||
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
|
||||
ma = freq_diff * a;
|
||||
mb = mclk * b;
|
||||
if (ma == mb) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
goto finish;
|
||||
}
|
||||
if (abs((mb - ma)) < min) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
min = abs(mb - ma);
|
||||
}
|
||||
}
|
||||
finish:
|
||||
if (denominator == 0 || numerator == 0) {
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = 0;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = 0;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = 0;
|
||||
} else {
|
||||
if (numerator > denominator / 2) {
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / (denominator - numerator) - 1;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % (denominator - numerator);
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = denominator - numerator;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 1;
|
||||
} else {
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / numerator - 1;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % numerator;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = numerator;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
|
||||
}
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
|
||||
i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -565,10 +512,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
|
||||
*/
|
||||
static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
|
||||
{
|
||||
typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl;
|
||||
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
|
||||
hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val;
|
||||
uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
|
||||
tdm_ctrl &= 0xFFFF0000;
|
||||
tdm_ctrl |= chan_mask;
|
||||
hw->tx_tdm_ctrl.val = tdm_ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -579,10 +526,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
|
||||
*/
|
||||
static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
|
||||
{
|
||||
typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl;
|
||||
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
|
||||
hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val;
|
||||
uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
|
||||
tdm_ctrl &= 0xFFFF0000;
|
||||
tdm_ctrl |= chan_mask;
|
||||
hw->rx_tdm_ctrl.val = tdm_ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -596,21 +543,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
|
||||
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
|
||||
* Otherwise always enable the first two slots */
|
||||
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
|
||||
hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
uint32_t chan_mask = 0;
|
||||
switch (slot_mask)
|
||||
{
|
||||
case I2S_STD_SLOT_LEFT:
|
||||
hw->tx_tdm_ctrl.val |= 0x01;
|
||||
chan_mask |= 0x01;
|
||||
break;
|
||||
case I2S_STD_SLOT_RIGHT:
|
||||
hw->tx_tdm_ctrl.val |= 0x02;
|
||||
chan_mask |= 0x02;
|
||||
break;
|
||||
case I2S_STD_SLOT_BOTH:
|
||||
hw->tx_tdm_ctrl.val |= 0x03;
|
||||
chan_mask |= 0x03;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -624,21 +572,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
|
||||
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
|
||||
* Otherwise always enable the first two slots */
|
||||
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
|
||||
hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
uint32_t chan_mask = 0;
|
||||
switch (slot_mask)
|
||||
{
|
||||
case I2S_STD_SLOT_LEFT:
|
||||
hw->rx_tdm_ctrl.val |= 0x01;
|
||||
chan_mask |= 0x01;
|
||||
break;
|
||||
case I2S_STD_SLOT_RIGHT:
|
||||
hw->rx_tdm_ctrl.val |= 0x02;
|
||||
chan_mask |= 0x02;
|
||||
break;
|
||||
case I2S_STD_SLOT_BOTH:
|
||||
hw->rx_tdm_ctrl.val |= 0x03;
|
||||
chan_mask |= 0x03;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -34,11 +34,14 @@ extern "C" {
|
||||
#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9)
|
||||
#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
|
||||
|
||||
/* I2S clock configuration structure */
|
||||
/**
|
||||
* @brief I2S clock configuration structure
|
||||
* @note Fmclk = Fsclk /(integ+numer/denom)
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
|
||||
uint16_t a;
|
||||
uint16_t b; // The decimal part of module clock divider, the decimal is: b/a
|
||||
uint16_t integ; // Integer part of I2S module clock divider
|
||||
uint16_t denom; // Denominator part of I2S module clock divider
|
||||
uint16_t numer; // Numerator part of I2S module clock divider
|
||||
} i2s_ll_mclk_div_t;
|
||||
|
||||
/**
|
||||
@ -224,96 +227,74 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
|
||||
* @brief Set I2S tx raw clock division
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param div_int Integer part of division
|
||||
* @param x div x
|
||||
* @param y div y
|
||||
* @param z div z
|
||||
* @param yn1 yn1
|
||||
*/
|
||||
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
|
||||
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
|
||||
{
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_x = x;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_y = y;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_z = z;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = yn1;
|
||||
/* Set the integer part of mclk division */
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, div_int);
|
||||
/* Set the decimal part of the mclk division */
|
||||
typeof(hw->tx_clkm_div_conf) div = {};
|
||||
div.tx_clkm_div_x = x;
|
||||
div.tx_clkm_div_y = y;
|
||||
div.tx_clkm_div_z = z;
|
||||
div.tx_clkm_div_yn1 = yn1;
|
||||
hw->tx_clkm_div_conf.val = div.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set I2S rx raw clock division
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param div_int Integer part of division
|
||||
* @param x div x
|
||||
* @param y div y
|
||||
* @param z div z
|
||||
* @param yn1 yn1
|
||||
*/
|
||||
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
|
||||
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
|
||||
{
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = x;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = y;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = z;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = yn1;
|
||||
/* Set the integer part of mclk division */
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, div_int);
|
||||
/* Set the decimal part of the mclk division */
|
||||
typeof(hw->rx_clkm_div_conf) div = {};
|
||||
div.rx_clkm_div_x = x;
|
||||
div.rx_clkm_div_y = y;
|
||||
div.rx_clkm_div_z = z;
|
||||
div.rx_clkm_div_yn1 = yn1;
|
||||
hw->rx_clkm_div_conf.val = div.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2S TX module clock divider
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param sclk system clock, 0 means use apll
|
||||
* @param mclk module clock
|
||||
* @param mclk_div integer part of the division from sclk to mclk
|
||||
* @param mclk_div The mclk division coefficients
|
||||
*/
|
||||
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
|
||||
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
|
||||
{
|
||||
int ma = 0;
|
||||
int mb = 0;
|
||||
int denominator = 1;
|
||||
int numerator = 0;
|
||||
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
|
||||
* Set to particular coefficients first then update to the target coefficients,
|
||||
* otherwise the clock division might be inaccurate.
|
||||
* the general idea is to set a value that impossible to calculate from the regular decimal */
|
||||
i2s_ll_tx_set_raw_clk_div(hw, 8, 1, 1, 73, 1);
|
||||
|
||||
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
|
||||
if (!freq_diff) {
|
||||
goto finish;
|
||||
uint32_t div_x = 0;
|
||||
uint32_t div_y = 0;
|
||||
uint32_t div_z = 0;
|
||||
uint32_t div_yn1 = 0;
|
||||
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
|
||||
if (mclk_div->denom && mclk_div->numer) {
|
||||
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
|
||||
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
|
||||
div_x = mclk_div->denom / div_z - 1;
|
||||
div_y = mclk_div->denom % div_z;
|
||||
}
|
||||
float decimal = freq_diff / (float)mclk;
|
||||
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
|
||||
if (decimal > 125.0 / 126.0) {
|
||||
mclk_div++;
|
||||
goto finish;
|
||||
}
|
||||
uint32_t min = ~0;
|
||||
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
|
||||
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
|
||||
ma = freq_diff * a;
|
||||
mb = mclk * b;
|
||||
if (ma == mb) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
goto finish;
|
||||
}
|
||||
if (abs((mb - ma)) < min) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
min = abs(mb - ma);
|
||||
}
|
||||
}
|
||||
finish:
|
||||
if (denominator == 0 || numerator == 0) {
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_x = 0;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_y = 0;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_z = 0;
|
||||
} else {
|
||||
if (numerator > denominator / 2) {
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / (denominator - numerator) - 1;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % (denominator - numerator);
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_z = denominator - numerator;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 1;
|
||||
} else {
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / numerator - 1;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % numerator;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_z = numerator;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
|
||||
}
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
|
||||
i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -332,62 +313,28 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
|
||||
* @note mclk on ESP32 is shared by both TX and RX channel
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param sclk system clock, 0 means use apll
|
||||
* @param mclk module clock
|
||||
* @param mclk_div integer part of the division from sclk to mclk
|
||||
* @param mclk_div The mclk division coefficients
|
||||
*/
|
||||
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
|
||||
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
|
||||
{
|
||||
int ma = 0;
|
||||
int mb = 0;
|
||||
int denominator = 1;
|
||||
int numerator = 0;
|
||||
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
|
||||
* Set to particular coefficients first then update to the target coefficients,
|
||||
* otherwise the clock division might be inaccurate.
|
||||
* the general idea is to set a value that impossible to calculate from the regular decimal */
|
||||
i2s_ll_rx_set_raw_clk_div(hw, 8, 1, 1, 73, 1);
|
||||
|
||||
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
|
||||
if (!freq_diff) {
|
||||
goto finish;
|
||||
uint32_t div_x = 0;
|
||||
uint32_t div_y = 0;
|
||||
uint32_t div_z = 0;
|
||||
uint32_t div_yn1 = 0;
|
||||
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
|
||||
if (mclk_div->denom && mclk_div->numer) {
|
||||
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
|
||||
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
|
||||
div_x = mclk_div->denom / div_z - 1;
|
||||
div_y = mclk_div->denom % div_z;
|
||||
}
|
||||
float decimal = freq_diff / (float)mclk;
|
||||
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
|
||||
if (decimal > 125.0 / 126.0) {
|
||||
mclk_div++;
|
||||
goto finish;
|
||||
}
|
||||
uint32_t min = ~0;
|
||||
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
|
||||
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
|
||||
ma = freq_diff * a;
|
||||
mb = mclk * b;
|
||||
if (ma == mb) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
goto finish;
|
||||
}
|
||||
if (abs((mb - ma)) < min) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
min = abs(mb - ma);
|
||||
}
|
||||
}
|
||||
finish:
|
||||
if (denominator == 0 || numerator == 0) {
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = 0;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = 0;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = 0;
|
||||
} else {
|
||||
if (numerator > denominator / 2) {
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / (denominator - numerator) - 1;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % (denominator - numerator);
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = denominator - numerator;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 1;
|
||||
} else {
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / numerator - 1;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % numerator;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = numerator;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
|
||||
}
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
|
||||
i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -435,7 +382,7 @@ static inline void i2s_ll_rx_stop(i2s_dev_t *hw)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure TX WS signal width
|
||||
* @brief Start I2S TX
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param width WS width in BCK cycle
|
||||
@ -567,10 +514,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
|
||||
*/
|
||||
static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
|
||||
{
|
||||
typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl;
|
||||
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
|
||||
hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val;
|
||||
uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
|
||||
tdm_ctrl &= 0xFFFF0000;
|
||||
tdm_ctrl |= chan_mask;
|
||||
hw->tx_tdm_ctrl.val = tdm_ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -581,10 +528,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
|
||||
*/
|
||||
static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
|
||||
{
|
||||
typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl;
|
||||
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
|
||||
hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val;
|
||||
uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
|
||||
tdm_ctrl &= 0xFFFF0000;
|
||||
tdm_ctrl |= chan_mask;
|
||||
hw->rx_tdm_ctrl.val = tdm_ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -598,21 +545,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
|
||||
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
|
||||
* Otherwise always enable the first two slots */
|
||||
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
|
||||
hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
uint32_t chan_mask = 0;
|
||||
switch (slot_mask)
|
||||
{
|
||||
case I2S_STD_SLOT_LEFT:
|
||||
hw->tx_tdm_ctrl.val |= 0x01;
|
||||
chan_mask |= 0x01;
|
||||
break;
|
||||
case I2S_STD_SLOT_RIGHT:
|
||||
hw->tx_tdm_ctrl.val |= 0x02;
|
||||
chan_mask |= 0x02;
|
||||
break;
|
||||
case I2S_STD_SLOT_BOTH:
|
||||
hw->tx_tdm_ctrl.val |= 0x03;
|
||||
chan_mask |= 0x03;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -626,21 +574,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
|
||||
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
|
||||
* Otherwise always enable the first two slots */
|
||||
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
|
||||
hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
uint32_t chan_mask = 0;
|
||||
switch (slot_mask)
|
||||
{
|
||||
case I2S_STD_SLOT_LEFT:
|
||||
hw->rx_tdm_ctrl.val |= 0x01;
|
||||
chan_mask |= 0x01;
|
||||
break;
|
||||
case I2S_STD_SLOT_RIGHT:
|
||||
hw->rx_tdm_ctrl.val |= 0x02;
|
||||
chan_mask |= 0x02;
|
||||
break;
|
||||
case I2S_STD_SLOT_BOTH:
|
||||
hw->rx_tdm_ctrl.val |= 0x03;
|
||||
chan_mask |= 0x03;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -44,11 +44,14 @@ extern "C" {
|
||||
#define I2S_LL_TX_EVENT_MASK I2S_LL_EVENT_TX_EOF
|
||||
#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
|
||||
|
||||
/* I2S clock configuration structure */
|
||||
/**
|
||||
* @brief I2S clock configuration structure
|
||||
* @note Fmclk = Fsclk /(integ+numer/denom)
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
|
||||
uint16_t a;
|
||||
uint16_t b; // The decimal part of module clock divider, the decimal is: b/a
|
||||
uint16_t integ; // Integer part of I2S module clock divider
|
||||
uint16_t denom; // Denominator part of I2S module clock divider
|
||||
uint16_t numer; // Numerator part of I2S module clock divider
|
||||
} i2s_ll_mclk_div_t;
|
||||
|
||||
/**
|
||||
@ -275,57 +278,9 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
|
||||
hw->sample_rate_conf.tx_bck_div_num = val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2S TX module clock divider
|
||||
* @note mclk on ESP32S2 is shared by both TX and RX channel
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param sclk system clock, 0 means use apll
|
||||
* @param mclk module clock
|
||||
* @param mclk_div integer part of the division from sclk to mclk
|
||||
*/
|
||||
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
|
||||
{
|
||||
int ma = 0;
|
||||
int mb = 0;
|
||||
int denominator = 1;
|
||||
int numerator = 0;
|
||||
|
||||
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
|
||||
if (!freq_diff) {
|
||||
goto finish;
|
||||
}
|
||||
float decimal = freq_diff / (float)mclk;
|
||||
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
|
||||
if (decimal > 125.0 / 126.0) {
|
||||
mclk_div++;
|
||||
goto finish;
|
||||
}
|
||||
uint32_t min = ~0;
|
||||
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
|
||||
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
|
||||
ma = freq_diff * a;
|
||||
mb = mclk * b;
|
||||
if (ma == mb) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
goto finish;
|
||||
}
|
||||
if (abs((mb - ma)) < min) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
min = abs(mb - ma);
|
||||
}
|
||||
}
|
||||
finish:
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, mclk_div);
|
||||
hw->clkm_conf.clkm_div_b = numerator;
|
||||
hw->clkm_conf.clkm_div_a = denominator;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2S module clock divider
|
||||
* @note mclk on ESP32 is shared by both TX and RX channel
|
||||
* @note mclk on ESP32S2 is shared by both TX and RX channel
|
||||
* mclk = sclk / (mclk_div + b/a)
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
@ -340,6 +295,24 @@ static inline void i2s_ll_set_raw_mclk_div(i2s_dev_t *hw, uint32_t mclk_div, uin
|
||||
hw->clkm_conf.clkm_div_a = a;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2S TX module clock divider
|
||||
*
|
||||
* @note mclk on ESP32 is shared by both TX and RX channel
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param mclk_div The mclk division coefficients
|
||||
*/
|
||||
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
|
||||
{
|
||||
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
|
||||
* Set to particular coefficients first then update to the target coefficients,
|
||||
* otherwise the clock division might be inaccurate.
|
||||
* the general idea is to set a value that unlike to calculate from the regular decimal */
|
||||
i2s_ll_set_raw_mclk_div(hw, 7, 47, 3);
|
||||
i2s_ll_set_raw_mclk_div(hw, mclk_div->integ, mclk_div->denom, mclk_div->numer);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set I2S rx bck div num
|
||||
*
|
||||
@ -353,16 +326,15 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
|
||||
|
||||
/**
|
||||
* @brief Configure I2S RX module clock divider
|
||||
* @note mclk on ESP32S2 is shared by both TX and RX channel
|
||||
* @note mclk on ESP32 is shared by both TX and RX channel
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param sclk system clock, 0 means use apll
|
||||
* @param mclk module clock
|
||||
* @param mclk_div integer part of the division from sclk to mclk
|
||||
* @param mclk_div The mclk division coefficients
|
||||
*/
|
||||
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
|
||||
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
|
||||
{
|
||||
i2s_ll_tx_set_mclk(hw, sclk, mclk, mclk_div);
|
||||
// TX and RX channel on ESP32 shares a same mclk
|
||||
i2s_ll_tx_set_mclk(hw, mclk_div);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -374,11 +346,13 @@ static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
|
||||
*/
|
||||
static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
|
||||
{
|
||||
uint32_t int_ena_mask = hw->int_ena.val;
|
||||
if (en) {
|
||||
hw->int_ena.val |= mask;
|
||||
int_ena_mask |= mask;
|
||||
} else {
|
||||
hw->int_ena.val &= ~mask;
|
||||
int_ena_mask &= ~mask;
|
||||
}
|
||||
hw->int_ena.val = int_ena_mask;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -33,11 +33,14 @@ extern "C" {
|
||||
#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9)
|
||||
#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
|
||||
|
||||
/* I2S clock configuration structure */
|
||||
/**
|
||||
* @brief I2S clock configuration structure
|
||||
* @note Fmclk = Fsclk /(integ+numer/denom)
|
||||
*/
|
||||
typedef struct {
|
||||
uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
|
||||
uint16_t a;
|
||||
uint16_t b; // The decimal part of module clock divider, the decimal is: b/a
|
||||
uint16_t integ; // Integer part of I2S module clock divider
|
||||
uint16_t denom; // Denominator part of I2S module clock divider
|
||||
uint16_t numer; // Numerator part of I2S module clock divider
|
||||
} i2s_ll_mclk_div_t;
|
||||
|
||||
/**
|
||||
@ -225,96 +228,74 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
|
||||
* @brief Set I2S tx raw clock division
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param div_int Integer part of division
|
||||
* @param x div x
|
||||
* @param y div y
|
||||
* @param z div z
|
||||
* @param yn1 yn1
|
||||
*/
|
||||
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
|
||||
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
|
||||
{
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_x = x;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_y = y;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_z = z;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = yn1;
|
||||
/* Set the integer part of mclk division */
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, div_int);
|
||||
/* Set the decimal part of the mclk division */
|
||||
typeof(hw->tx_clkm_div_conf) div = {};
|
||||
div.tx_clkm_div_x = x;
|
||||
div.tx_clkm_div_y = y;
|
||||
div.tx_clkm_div_z = z;
|
||||
div.tx_clkm_div_yn1 = yn1;
|
||||
hw->tx_clkm_div_conf.val = div.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set I2S rx raw clock division
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param div_int Integer part of division
|
||||
* @param x div x
|
||||
* @param y div y
|
||||
* @param z div z
|
||||
* @param yn1 yn1
|
||||
*/
|
||||
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
|
||||
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
|
||||
{
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = x;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = y;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = z;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = yn1;
|
||||
/* Set the integer part of mclk division */
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, div_int);
|
||||
/* Set the decimal part of the mclk division */
|
||||
typeof(hw->rx_clkm_div_conf) div = {};
|
||||
div.rx_clkm_div_x = x;
|
||||
div.rx_clkm_div_y = y;
|
||||
div.rx_clkm_div_z = z;
|
||||
div.rx_clkm_div_yn1 = yn1;
|
||||
hw->rx_clkm_div_conf.val = div.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2S TX module clock divider
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param sclk system clock, 0 means use apll
|
||||
* @param mclk module clock
|
||||
* @param mclk_div integer part of the division from sclk to mclk
|
||||
* @param mclk_div The mclk division coefficients
|
||||
*/
|
||||
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
|
||||
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
|
||||
{
|
||||
int ma = 0;
|
||||
int mb = 0;
|
||||
int denominator = 1;
|
||||
int numerator = 0;
|
||||
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
|
||||
* Set to particular coefficients first then update to the target coefficients,
|
||||
* otherwise the clock division might be inaccurate.
|
||||
* the general idea is to set a value that impossible to calculate from the regular decimal */
|
||||
i2s_ll_tx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
|
||||
|
||||
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
|
||||
if (!freq_diff) {
|
||||
goto finish;
|
||||
uint32_t div_x = 0;
|
||||
uint32_t div_y = 0;
|
||||
uint32_t div_z = 0;
|
||||
uint32_t div_yn1 = 0;
|
||||
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
|
||||
if (mclk_div->denom && mclk_div->numer) {
|
||||
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
|
||||
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
|
||||
div_x = mclk_div->denom / div_z - 1;
|
||||
div_y = mclk_div->denom % div_z;
|
||||
}
|
||||
float decimal = freq_diff / (float)mclk;
|
||||
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
|
||||
if (decimal > 125.0 / 126.0) {
|
||||
mclk_div++;
|
||||
goto finish;
|
||||
}
|
||||
uint32_t min = ~0;
|
||||
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
|
||||
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
|
||||
ma = freq_diff * a;
|
||||
mb = mclk * b;
|
||||
if (ma == mb) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
goto finish;
|
||||
}
|
||||
if (abs((mb - ma)) < min) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
min = abs(mb - ma);
|
||||
}
|
||||
}
|
||||
finish:
|
||||
if (denominator == 0 || numerator == 0) {
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_x = 0;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_y = 0;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_z = 0;
|
||||
} else {
|
||||
if (numerator > denominator / 2) {
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / (denominator - numerator) - 1;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % (denominator - numerator);
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_z = denominator - numerator;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 1;
|
||||
} else {
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / numerator - 1;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % numerator;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_z = numerator;
|
||||
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
|
||||
}
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
|
||||
i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -333,64 +314,31 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
|
||||
* @note mclk on ESP32 is shared by both TX and RX channel
|
||||
*
|
||||
* @param hw Peripheral I2S hardware instance address.
|
||||
* @param sclk system clock, 0 means use apll
|
||||
* @param mclk module clock
|
||||
* @param mclk_div integer part of the division from sclk to mclk
|
||||
* @param mclk_div The mclk division coefficients
|
||||
*/
|
||||
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
|
||||
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
|
||||
{
|
||||
int ma = 0;
|
||||
int mb = 0;
|
||||
int denominator = 1;
|
||||
int numerator = 0;
|
||||
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
|
||||
* Set to particular coefficients first then update to the target coefficients,
|
||||
* otherwise the clock division might be inaccurate.
|
||||
* the general idea is to set a value that impossible to calculate from the regular decimal */
|
||||
i2s_ll_rx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
|
||||
|
||||
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
|
||||
if (!freq_diff) {
|
||||
goto finish;
|
||||
uint32_t div_x = 0;
|
||||
uint32_t div_y = 0;
|
||||
uint32_t div_z = 0;
|
||||
uint32_t div_yn1 = 0;
|
||||
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
|
||||
if (mclk_div->denom && mclk_div->numer) {
|
||||
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
|
||||
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
|
||||
div_x = mclk_div->denom / div_z - 1;
|
||||
div_y = mclk_div->denom % div_z;
|
||||
}
|
||||
float decimal = freq_diff / (float)mclk;
|
||||
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
|
||||
if (decimal > 125.0 / 126.0) {
|
||||
mclk_div++;
|
||||
goto finish;
|
||||
}
|
||||
uint32_t min = ~0;
|
||||
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
|
||||
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
|
||||
ma = freq_diff * a;
|
||||
mb = mclk * b;
|
||||
if (ma == mb) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
goto finish;
|
||||
}
|
||||
if (abs((mb - ma)) < min) {
|
||||
denominator = a;
|
||||
numerator = b;
|
||||
min = abs(mb - ma);
|
||||
}
|
||||
}
|
||||
finish:
|
||||
if (denominator == 0 || numerator == 0) {
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = 0;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = 0;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = 0;
|
||||
} else {
|
||||
if (numerator > denominator / 2) {
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / (denominator - numerator) - 1;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % (denominator - numerator);
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = denominator - numerator;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 1;
|
||||
} else {
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / numerator - 1;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % numerator;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_z = numerator;
|
||||
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
|
||||
}
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
|
||||
i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Start I2S TX
|
||||
*
|
||||
@ -568,10 +516,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
|
||||
*/
|
||||
static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
|
||||
{
|
||||
typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl;
|
||||
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
|
||||
hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val;
|
||||
uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
|
||||
tdm_ctrl &= 0xFFFF0000;
|
||||
tdm_ctrl |= chan_mask;
|
||||
hw->tx_tdm_ctrl.val = tdm_ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -582,10 +530,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
|
||||
*/
|
||||
static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
|
||||
{
|
||||
typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl;
|
||||
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
|
||||
hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val;
|
||||
uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
|
||||
tdm_ctrl &= 0xFFFF0000;
|
||||
tdm_ctrl |= chan_mask;
|
||||
hw->rx_tdm_ctrl.val = tdm_ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -599,21 +547,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
|
||||
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
|
||||
* Otherwise always enable the first two slots */
|
||||
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
|
||||
hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
uint32_t chan_mask = 0;
|
||||
switch (slot_mask)
|
||||
{
|
||||
case I2S_STD_SLOT_LEFT:
|
||||
hw->tx_tdm_ctrl.val |= 0x01;
|
||||
chan_mask |= 0x01;
|
||||
break;
|
||||
case I2S_STD_SLOT_RIGHT:
|
||||
hw->tx_tdm_ctrl.val |= 0x02;
|
||||
chan_mask |= 0x02;
|
||||
break;
|
||||
case I2S_STD_SLOT_BOTH:
|
||||
hw->tx_tdm_ctrl.val |= 0x03;
|
||||
chan_mask |= 0x03;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -627,21 +576,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
|
||||
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
|
||||
* Otherwise always enable the first two slots */
|
||||
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
|
||||
hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
|
||||
uint32_t chan_mask = 0;
|
||||
switch (slot_mask)
|
||||
{
|
||||
case I2S_STD_SLOT_LEFT:
|
||||
hw->rx_tdm_ctrl.val |= 0x01;
|
||||
chan_mask |= 0x01;
|
||||
break;
|
||||
case I2S_STD_SLOT_RIGHT:
|
||||
hw->rx_tdm_ctrl.val |= 0x02;
|
||||
chan_mask |= 0x02;
|
||||
break;
|
||||
case I2S_STD_SLOT_BOTH:
|
||||
hw->rx_tdm_ctrl.val |= 0x03;
|
||||
chan_mask |= 0x03;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -11,7 +11,7 @@
|
||||
#include "hal/i2s_hal.h"
|
||||
|
||||
#if SOC_I2S_HW_VERSION_2 && SOC_I2S_SUPPORTS_PDM_TX
|
||||
/* PDM tx high pass filter cut-off frequency and coeffecients list
|
||||
/* PDM tx high pass filter cut-off frequency and coefficients list
|
||||
* [0]: cut-off frequency; [1]: param0; [2]: param5 */
|
||||
static const float cut_off_coef[21][3] = {
|
||||
{185, 0, 0}, {172, 0, 1}, {160, 1, 1},
|
||||
@ -24,6 +24,53 @@ static const float cut_off_coef[21][3] = {
|
||||
};
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Calculate the precise mclk division by sclk and mclk
|
||||
*
|
||||
* @param sclk system clock
|
||||
* @param mclk module clock
|
||||
* @param integer output the integer part of the division
|
||||
* @param denominator output the denominator part of the division
|
||||
* @param numerator output the numerator part of the division
|
||||
*/
|
||||
void i2s_hal_calc_mclk_precise_division(uint32_t sclk, uint32_t mclk, i2s_ll_mclk_div_t *mclk_div)
|
||||
{
|
||||
int ma = 0;
|
||||
int mb = 0;
|
||||
int min = INT32_MAX;
|
||||
uint32_t div_denom = 1;
|
||||
uint32_t div_numer = 0;
|
||||
uint32_t div_inter = sclk / mclk;
|
||||
uint32_t freq_diff = sclk % mclk;
|
||||
|
||||
if (freq_diff) {
|
||||
float decimal = freq_diff / (float)mclk;
|
||||
// Carry bit if the decimal is greater than 1.0 - 1.0 / (I2S_LL_MCLK_DIVIDER_MAX * 2)
|
||||
if (decimal <= 1.0 - 1.0 / (float)(I2S_LL_MCLK_DIVIDER_MAX * 2)) {
|
||||
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
|
||||
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
|
||||
ma = freq_diff * a;
|
||||
mb = mclk * b;
|
||||
if (ma == mb) {
|
||||
div_denom = (uint32_t)a;
|
||||
div_numer = (uint32_t)b;
|
||||
break;
|
||||
}
|
||||
if (abs(mb - ma) < min) {
|
||||
div_denom = (uint32_t)a;
|
||||
div_numer = (uint32_t)b;
|
||||
min = abs(mb - ma);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
div_inter++;
|
||||
}
|
||||
}
|
||||
mclk_div->integ = div_inter;
|
||||
mclk_div->denom = div_denom;
|
||||
mclk_div->numer = div_numer;
|
||||
}
|
||||
|
||||
void i2s_hal_init(i2s_hal_context_t *hal, int port_id)
|
||||
{
|
||||
/* Get hardware instance */
|
||||
@ -32,23 +79,27 @@ void i2s_hal_init(i2s_hal_context_t *hal, int port_id)
|
||||
|
||||
void i2s_hal_set_tx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src)
|
||||
{
|
||||
i2s_ll_mclk_div_t mclk_div = {};
|
||||
#if SOC_I2S_HW_VERSION_2
|
||||
i2s_ll_tx_enable_clock(hal->dev);
|
||||
i2s_ll_mclk_bind_to_tx_clk(hal->dev);
|
||||
#endif
|
||||
i2s_ll_tx_clk_set_src(hal->dev, clk_src);
|
||||
i2s_ll_tx_set_mclk(hal->dev, clk_info->sclk, clk_info->mclk, clk_info->mclk_div);
|
||||
i2s_hal_calc_mclk_precise_division(clk_info->sclk, clk_info->mclk, &mclk_div);
|
||||
i2s_ll_tx_set_mclk(hal->dev, &mclk_div);
|
||||
i2s_ll_tx_set_bck_div_num(hal->dev, clk_info->bclk_div);
|
||||
}
|
||||
|
||||
void i2s_hal_set_rx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src)
|
||||
{
|
||||
i2s_ll_mclk_div_t mclk_div = {};
|
||||
#if SOC_I2S_HW_VERSION_2
|
||||
i2s_ll_rx_enable_clock(hal->dev);
|
||||
i2s_ll_mclk_bind_to_rx_clk(hal->dev);
|
||||
#endif
|
||||
i2s_ll_rx_clk_set_src(hal->dev, clk_src);
|
||||
i2s_ll_rx_set_mclk(hal->dev, clk_info->sclk, clk_info->mclk, clk_info->mclk_div);
|
||||
i2s_hal_calc_mclk_precise_division(clk_info->sclk, clk_info->mclk, &mclk_div);
|
||||
i2s_ll_rx_set_mclk(hal->dev, &mclk_div);
|
||||
i2s_ll_rx_set_bck_div_num(hal->dev, clk_info->bclk_div);
|
||||
}
|
||||
|
||||
@ -200,7 +251,7 @@ void i2s_hal_pdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
|
||||
i2s_ll_rx_enable_msb_right(hal->dev, false);
|
||||
i2s_ll_rx_enable_right_first(hal->dev, false);
|
||||
#elif SOC_I2S_HW_VERSION_2
|
||||
i2s_ll_tx_set_half_sample_bit(hal->dev, 16);
|
||||
i2s_ll_rx_set_half_sample_bit(hal->dev, 16);
|
||||
i2s_ll_rx_enable_mono_mode(hal->dev, false);
|
||||
/* Set the channel mask to enable corresponding slots, always enable two slots for stereo mode */
|
||||
i2s_ll_rx_set_active_chan_mask(hal->dev, slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO ?
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -120,6 +120,15 @@ typedef struct {
|
||||
*/
|
||||
void i2s_hal_init(i2s_hal_context_t *hal, int port_id);
|
||||
|
||||
/**
|
||||
* @brief Helper function for calculating the precise mclk division by sclk and mclk
|
||||
*
|
||||
* @param sclk system clock
|
||||
* @param mclk module clock
|
||||
* @param mclk_div mclk division coefficients, including integer part and decimal part
|
||||
*/
|
||||
void i2s_hal_calc_mclk_precise_division(uint32_t sclk, uint32_t mclk, i2s_ll_mclk_div_t *mclk_div);
|
||||
|
||||
/**
|
||||
* @brief Set tx channel clock
|
||||
*
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user