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81f6d7abbe
For targets that only contain a USJ peripheral (and not a DWC OTG), their
'usb_fsls_phy_ll.h' headers only contain a single function
('usb_fsls_phy_ll_int_jtag_enable()') whose feature is already covered by
functions in 'usb_serial_jtag_ll.h'. Thus, this header is redundant.
This commit does the following:
- Remove 'usb_fsls_phy_ll.h' for targets that only contain a USJ peripheral
- Rename 'usb_fsls_phy_[hal|ll].[h|c]' to `usb_wrap_[hal|ll].[h|c]` for targets
that contain a DWC OTG peripheral. This better reflects the underlying peripheral
that the LL header accesses.
79 lines
2.7 KiB
C
79 lines
2.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/soc_caps.h"
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#include "soc/rtc_cntl_struct.h"
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#if SOC_USB_SERIAL_JTAG_SUPPORTED
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#include "hal/usb_serial_jtag_ll.h"
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#endif
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#include "hal/usb_wrap_ll.h"
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#include "hal/usb_wrap_hal.h"
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void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal)
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{
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hal->wrap_dev = &USB_WRAP;
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#if SOC_USB_SERIAL_JTAG_SUPPORTED
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hal->jtag_dev = &USB_SERIAL_JTAG;
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#endif
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}
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void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
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{
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if (phy_target == USB_PHY_TARGET_EXT) {
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usb_fsls_phy_ll_ext_otg_enable(hal->wrap_dev);
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} else if (phy_target == USB_PHY_TARGET_INT) {
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usb_fsls_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true);
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usb_fsls_phy_ll_int_otg_enable(hal->wrap_dev);
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}
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}
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#if SOC_USB_SERIAL_JTAG_SUPPORTED
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void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
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{
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if (phy_target == USB_PHY_TARGET_EXT) {
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usb_serial_jtag_ll_phy_enable_external(true); // USJ uses external PHY
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// Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY
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RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
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// Internal USB FSLS PHY is mapped to the USJ
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RTCCNTL.usb_conf.sw_usb_phy_sel = 1;
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} else if (phy_target == USB_PHY_TARGET_INT) {
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usb_serial_jtag_ll_phy_enable_external(true); // USJ uses internal PHY
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usb_serial_jtag_ll_phy_enable_pad(true); // Enable USB PHY pads
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// Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY
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RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
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// Internal USB FSLS PHY is mapped to the USJ
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RTCCNTL.usb_conf.sw_usb_phy_sel = 0;
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}
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}
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#endif
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void usb_fsls_phy_hal_int_load_conf_host(usb_fsls_phy_hal_context_t *hal)
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{
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// HOST - upstream: dp_pd = 1, dm_pd = 1
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usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true);
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}
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void usb_fsls_phy_hal_int_load_conf_dev(usb_fsls_phy_hal_context_t *hal, usb_phy_speed_t speed)
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{
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// DEVICE - downstream
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if (speed == USB_PHY_SPEED_LOW) {
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// LS: dm_pu = 1
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usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false);
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} else {
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// FS: dp_pu = 1
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usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, true, false, false, false);
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}
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}
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void usb_fsls_phy_hal_int_mimick_disconn(usb_fsls_phy_hal_context_t *hal, bool disconn)
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{
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/*
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We mimick a disconnect by enabling the internal PHY's test mode, then forcing the output_enable to HIGH. This will:
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A HIGH output_enable will cause the received VP and VM to be zero, thus mimicking a disconnection.
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*/
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usb_fsls_phy_ll_int_enable_test_mode(hal->wrap_dev, disconn);
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}
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