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https://github.com/espressif/esp-idf.git
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133 lines
3.4 KiB
C
133 lines
3.4 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_err.h"
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#include "soc/soc_caps.h"
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#include "hal/cpu_types.h"
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#include "hal/cpu_ll.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Return the ID of the core currently executing this code.
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*
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* @return core id [0..SOC_CPU_CORES_NUM - 1]
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*/
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#define cpu_hal_get_core_id() cpu_ll_get_core_id()
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/**
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* Get the current value of the stack pointer.
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*
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* @return the current stack pointer
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*/
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#define cpu_hal_get_sp() cpu_ll_get_sp()
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/**
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* Get the current value of the internal counter that increments
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* every processor-clock cycle.
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*
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* @return cycle count; returns 0 if not supported
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*/
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#define cpu_hal_get_cycle_count() cpu_ll_get_cycle_count()
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/**
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* Set the given value into the internal counter that increments
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* every processor-clock cycle.
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*/
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#define cpu_hal_set_cycle_count(val) cpu_ll_set_cycle_count(val)
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/**
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* Check if some form of debugger is attached to CPU.
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*
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* @return true debugger is attached
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* @return false no debugger is attached/ no support for debuggers
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*/
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#define cpu_hal_is_debugger_attached() cpu_ll_is_debugger_attached()
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/**
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* Init HW loop status.
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*/
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#define cpu_hal_init_hwloop() cpu_ll_init_hwloop()
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/**
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* Trigger a call to debugger.
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*/
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#define cpu_hal_break() cpu_ll_break()
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/**
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* Wait for interrupt.
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*/
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#define cpu_hal_waiti() cpu_ll_waiti()
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#if SOC_CPU_BREAKPOINTS_NUM > 0
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/**
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* Set and enable breakpoint at an instruction address.
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*
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* @note Overwrites previously set breakpoint with same breakpoint ID.
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*
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* @param id breakpoint to set [0..SOC_CPU_BREAKPOINTS_NUM - 1]
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* @param addr address to set a breakpoint on
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*/
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void cpu_hal_set_breakpoint(int id, const void* addr);
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/**
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* Clear and disable breakpoint.
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*
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* @param id breakpoint to clear [0..SOC_CPU_BREAKPOINTS_NUM - 1]
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*/
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void cpu_hal_clear_breakpoint(int id);
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#endif // SOC_CPU_BREAKPOINTS_NUM > 0
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#if SOC_CPU_WATCHPOINTS_NUM > 0
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/**
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* Set and enable a watchpoint, specifying the memory range and trigger operation.
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*
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* @param id watchpoint to set [0..SOC_CPU_WATCHPOINTS_NUM - 1]
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* @param addr starting address
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* @param size number of bytes from starting address to watch
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* @param trigger operation on specified memory range that triggers the watchpoint (read, write, read/write)
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*/
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void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger);
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/**
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* Clear and disable watchpoint.
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*
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* @param id watchpoint to clear [0..SOC_CPU_WATCHPOINTS_NUM - 1]
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*/
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void cpu_hal_clear_watchpoint(int id);
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#endif // SOC_CPU_WATCHPOINTS_NUM > 0
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/**
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* Set exception vector table base address.
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*
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* @param base address to move the exception vector table to
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*/
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void cpu_hal_set_vecbase(const void* base);
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#ifdef __cplusplus
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}
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#endif
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