Gustavo Henrique Nihei 24484887a9 esp_system: Ensure TIMG0 clock is always enabled during normal operation ... If the TimerGroup 0 clock is disabled and then reenabled, the watchdog registers (Flashboot protection included) will be re-enabled, and some seconds later, will trigger an unintended reset. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>		2023-03-07 10:02:06 +08:00
..
cache_err_int.c	bugfix: esprv_intc_int_set_type should not use bitmap parameter	2022-10-14 15:39:24 +08:00
clk.c	esp_system: Ensure TIMG0 clock is always enabled during normal operation	2023-03-07 10:02:06 +08:00
CMakeLists.txt	esp32c2: fix gcov example build	2022-07-28 13:59:29 +02:00
Kconfig.cache	g0: resolve MMU_PAGE_SIZE not defined in g0 build issue	2023-02-23 12:35:52 +08:00
Kconfig.cpu	soc: moved kconfig options out of the target component.	2022-04-21 12:09:43 +08:00
Kconfig.system	system: move kconfig options out of target component	2022-03-02 01:22:26 +00:00
reset_reason.c	esp32c2: support rtc time feature depend on rtc memory, since c2 does not have rtc memory	2023-02-16 10:52:59 +08:00
system_internal.c	riscv: Remove redundant riscv_interrupts.h header	2022-09-19 14:19:11 +08:00