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On first reset, ROM code writes the estimated XTAL frequency into RTC_APB_FREQ_REG (aka STORE5). If the application doesn’t specify exact XTAL frequency (which is always the case for now), rtc_clk_init will guess what kind of XTAL is used (26M or 40M), based on the estimated frequency. Later, detected frequency is written into RTC_XTAL_FREQ_REG (aka STORE4). When the application switches clock source to PLL, APB frequency changes and RTC_APB_FREQ_REG is updated. If the application encounters an RTC WDT reset, RTC_APB_FREQ_REG will not be updated prior to reset. Once the application starts up again, it will attempt to auto-detect XTAL frequency based on RTC_APB_FREQ_REG, which now has value of 80000000. This will fail, and rtc_clk_xtal_freq_estimate will fall back to the default value of 26 MHz. Due to an incorrect XTAL frequency, PLL initialization will also take incorrect path, and PLL will run at a different frequency. Depending on the application this may cause just garbage output on UART or a crash (if WiFi is used).