Angus Gratton 420aef1ffe Updates for riscv support
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00
..
2020-11-13 07:49:11 +11:00
2016-08-17 23:08:22 +08:00
2016-08-17 23:08:22 +08:00
2020-11-13 07:49:11 +11:00
2020-03-10 19:56:24 +08:00
2018-09-03 04:39:45 +00:00
2020-11-13 07:49:11 +11:00
2020-11-13 07:49:11 +11:00
2019-07-02 17:17:18 +02:00
2020-11-13 07:49:11 +11:00