mirror of
https://github.com/espressif/esp-idf.git
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310 lines
11 KiB
C
310 lines
11 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Version Control Registers */
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/** Type of lp_peri_pms_date register
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* Version control register
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*/
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typedef union {
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struct {
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/** lp_peri_pms_date : R/W; bitpos: [31:0]; default: 2294537;
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* Version control register
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*/
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uint32_t lp_peri_pms_date:32;
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};
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uint32_t val;
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} pms_lp_peri_pms_date_reg_t;
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/** Group: Clock Gating Registers */
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/** Type of lp_peri_pms_clk_en register
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* Clock gating register
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*/
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typedef union {
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struct {
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/** lp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
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* Configures whether to keep the clock always on.
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* 0: Enable automatic clock gating
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* 1: Keep the clock always on
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*/
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uint32_t lp_peri_pms_clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} pms_lp_peri_pms_clk_en_reg_t;
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/** Group: LP CPU Permission Control Registers */
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/** Type of lp_mm_lp_peri_pms_reg0 register
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* Permission control register0 for LP CPU in machine mode
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*/
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typedef union {
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struct {
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/** lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP system
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* registers.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_sysreg_allow:1;
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/** lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP
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* always-on clock and reset).
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_aonclkrst_allow:1;
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/** lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP timer.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_timer_allow:1;
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/** lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP ANAPERI
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* (analog peripherals).
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_anaperi_allow:1;
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/** lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP PMU (Power
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* Management Unit).
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_pmu_allow:1;
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/** lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog
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* timer).
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_wdt_allow:1;
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/** lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP Mailbox
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* Controller.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_mailbox_allow:1;
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/** lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP RTC.
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* 0: Not allowed
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* 1: Allow
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*/
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uint32_t lp_mm_lp_rtc_allow:1;
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/** lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP PREICLKRST
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* (peripheral clock and reset).
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_periclkrst_allow:1;
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/** lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP UART.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_uart_allow:1;
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/** lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP I2S.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_i2c_allow:1;
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/** lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP SPI.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_spi_allow:1;
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/** lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP I2C master.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_i2cmst_allow:1;
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/** lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP I2S.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_i2s_allow:1;
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/** lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP ADC.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_adc_allow:1;
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/** lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP touch sensor.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_touch_allow:1;
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/** lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP IO MUX.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_iomux_allow:1;
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/** lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP INTR
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* (interrupt).
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_intr_allow:1;
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/** lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP eFuse.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_efuse_allow:1;
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/** lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_pms_allow:1;
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/** lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access
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* HP2LP_PERI_PMS_REG.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_hp2lp_pms_allow:1;
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/** lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP temperature
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* sensor.
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_tsens_allow:1;
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/** lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware
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* Unique Key).
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* 0: Not allowed
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* 1: Allowed
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*/
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uint32_t lp_mm_lp_huk_allow:1;
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/** lp_mm_lp_sram_allow : R/W; bitpos: [23]; default: 1;
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* Configures whether LP CPU in machine mode has permission to access LP SRAM.
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* 0: Not allowed
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* 1: Allow
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*/
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uint32_t lp_mm_lp_sram_allow:1;
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uint32_t reserved_24:8;
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};
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uint32_t val;
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} pms_lp_mm_lp_peri_pms_reg0_reg_t;
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/** Group: Configurable Address Range Configuration Registers */
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/** Type of peri_regionn_low register
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* Regionn start address configuration register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:2;
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/** peri_regionn_low : R/W; bitpos: [31:2]; default: 0;
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* Configures the high 30 bits of the start address of peripheral register's regionn.
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*/
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uint32_t peri_regionn_low:30;
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};
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uint32_t val;
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} pms_peri_regionn_low_reg_t;
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/** Type of peri_regionn_high register
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* Regionn end address configuration register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:2;
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/** peri_regionn_high : R/W; bitpos: [31:2]; default: 1073741823;
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* Configures the high 30 bits of the end address of peripheral register's regionn.
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*/
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uint32_t peri_regionn_high:30;
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};
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uint32_t val;
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} pms_peri_regionn_high_reg_t;
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/** Group: PMS Peripheral Region Permission Control Registers */
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/** Type of peri_region_pms register
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* Permission register of region
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*/
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typedef union {
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struct {
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/** lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
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* Configures whether LP core in machine mode has permission to access address region0
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* and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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uint32_t lp_core_region_pms:2;
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/** hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
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* Configures whether HP CPU0 in user mode has permission to access address region0
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* and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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uint32_t hp_core0_um_region_pms:2;
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/** hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
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* Configures whether HP CPU0 in machine mode has permission to access address region0
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* and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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uint32_t hp_core0_mm_region_pms:2;
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/** hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
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* Configures whether HP CPU1 in user mode has permission to access address region0
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* and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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uint32_t hp_core1_um_region_pms:2;
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/** hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
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* Configures whether HP CPU1 in machine mode has permission to access address region0
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* and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1.
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* 0: Not allowed
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* 1: Allow
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*/
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uint32_t hp_core1_mm_region_pms:2;
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uint32_t reserved_10:22;
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};
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uint32_t val;
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} pms_peri_region_pms_reg_t;
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typedef struct {
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volatile pms_lp_peri_pms_date_reg_t lp_peri_pms_date;
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volatile pms_lp_peri_pms_clk_en_reg_t lp_peri_pms_clk_en;
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volatile pms_lp_mm_lp_peri_pms_reg0_reg_t lp_mm_lp_peri_pms_reg0;
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volatile pms_peri_regionn_low_reg_t peri_region0_low;
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volatile pms_peri_regionn_high_reg_t peri_region0_high;
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volatile pms_peri_regionn_low_reg_t peri_region1_low;
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volatile pms_peri_regionn_high_reg_t peri_region1_high;
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volatile pms_peri_region_pms_reg_t peri_region_pms;
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} lp_peri_pms_dev_t;
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extern lp_peri_pms_dev_t LP_PERI_PMS;
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#ifndef __cplusplus
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_Static_assert(sizeof(lp_peri_pms_dev_t) == 0x20, "Invalid size of lp_peri_pms_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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