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fix(soc): fixed redefined soc reg names on P4

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laokaiyao 2024-04-16 20:02:46 +08:00
parent 4499b7ee8f
commit fc9555f355
11 changed files with 8256 additions and 7906 deletions
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2980
components/soc/esp32p4/include/soc/dma_pms_reg.h
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components/soc/esp32p4/include/soc/dma_pms_struct.h
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components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h
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components/soc/esp32p4/include/soc/hp2lp_peri_pms_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,502 +10,397 @@
extern "C" {
#endif
/** Group: TEE HP2LP TEE PMS DATE REG */
/** Type of hp2lp_tee_pms_date register
* NA
/** Group: Version Control Registers */
/** Type of hp2lp_peri_pms_date register
* Version control register
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2294790;
* NA
/** hp2lp_peri_pms_date : R/W; bitpos: [31:0]; default: 2294790;
* Version control register
*/
uint32_t tee_date:32;
uint32_t hp2lp_peri_pms_date:32;
};
uint32_t val;
} tee_hp2lp_tee_pms_date_reg_t;
} pms_hp2lp_peri_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
/** Group: Clock Gating Registers */
/** Type of hp2lp_peri_pms_clk_en register
* Clock gating register
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
/** hp2lp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
uint32_t reg_clk_en:1;
uint32_t hp2lp_peri_pms_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
} pms_hp2lp_peri_pms_clk_en_reg_t;
/** Group: TEE HP CORE0 MM PMS REG0 REG */
/** Type of hp_core0_mm_pms_reg0 register
* NA
/** Group: HP CPU Permission Control Registers */
/** Type of hp_coren_mm_pms_reg0 register
* Permission control register0 for HP CPUn in machine mode
*/
typedef union {
struct {
/** reg_hp_core0_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** hp_coren_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP System
* Registers.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_sysreg_allow:1;
/** reg_hp_core0_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t hp_coren_mm_lp_sysreg_allow:1;
/** hp_coren_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP_AONCLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_aonclkrst_allow:1;
/** reg_hp_core0_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t hp_coren_mm_lp_aonclkrst_allow:1;
/** hp_coren_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_timer_allow:1;
/** reg_hp_core0_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t hp_coren_mm_lp_timer_allow:1;
/** hp_coren_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP ANAPERI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_anaperi_allow:1;
/** reg_hp_core0_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t hp_coren_mm_lp_anaperi_allow:1;
/** hp_coren_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP PMU.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_pmu_allow:1;
/** reg_hp_core0_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t hp_coren_mm_lp_pmu_allow:1;
/** hp_coren_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP WDT.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_wdt_allow:1;
/** reg_hp_core0_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t hp_coren_mm_lp_wdt_allow:1;
/** hp_coren_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_mailbox_allow:1;
/** reg_hp_core0_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t hp_coren_mm_lp_mailbox_allow:1;
/** hp_coren_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_mm_lp_rtc_allow:1;
/** reg_hp_core0_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t hp_coren_mm_lp_rtc_allow:1;
/** hp_coren_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP PERICLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_periclkrst_allow:1;
/** reg_hp_core0_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t hp_coren_mm_lp_periclkrst_allow:1;
/** hp_coren_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_uart_allow:1;
/** reg_hp_core0_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t hp_coren_mm_lp_uart_allow:1;
/** hp_coren_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP I2C.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_i2c_allow:1;
/** reg_hp_core0_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t hp_coren_mm_lp_i2c_allow:1;
/** hp_coren_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_spi_allow:1;
/** reg_hp_core0_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t hp_coren_mm_lp_spi_allow:1;
/** hp_coren_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_i2cmst_allow:1;
/** reg_hp_core0_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t hp_coren_mm_lp_i2cmst_allow:1;
/** hp_coren_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_i2s_allow:1;
/** reg_hp_core0_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t hp_coren_mm_lp_i2s_allow:1;
/** hp_coren_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_adc_allow:1;
/** reg_hp_core0_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t hp_coren_mm_lp_adc_allow:1;
/** hp_coren_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP touch
* sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_touch_allow:1;
/** reg_hp_core0_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t hp_coren_mm_lp_touch_allow:1;
/** hp_coren_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_iomux_allow:1;
/** reg_hp_core0_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t hp_coren_mm_lp_iomux_allow:1;
/** hp_coren_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP INTR.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_intr_allow:1;
/** reg_hp_core0_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t hp_coren_mm_lp_intr_allow:1;
/** hp_coren_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_efuse_allow:1;
/** reg_hp_core0_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t hp_coren_mm_lp_efuse_allow:1;
/** hp_coren_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access
* LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_pms_allow:1;
/** reg_hp_core0_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
uint32_t hp_coren_mm_lp_pms_allow:1;
/** hp_coren_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_hp2lp_pms_allow:1;
/** reg_hp_core0_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
uint32_t hp_coren_mm_hp2lp_pms_allow:1;
/** hp_coren_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_tsens_allow:1;
/** reg_hp_core0_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t hp_coren_mm_lp_tsens_allow:1;
/** hp_coren_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* Configures whether HP CPUn in machine mode has permission to LP HUK.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_huk_allow:1;
/** reg_hp_core0_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t hp_coren_mm_lp_huk_allow:1;
/** hp_coren_mm_lp_sram_allow : R/W; bitpos: [23]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_tcm_ram_allow:1;
uint32_t hp_coren_mm_lp_sram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_hp_core0_mm_pms_reg0_reg_t;
} pms_hp_coren_mm_pms_reg0_reg_t;
/** Group: TEE HP CORE0 UM PMS REG0 REG */
/** Type of hp_core0_um_pms_reg0 register
* NA
/** Type of hp_coren_um_pms_reg0 register
* Permission control register0 for HP CPUn in user mode
*/
typedef union {
struct {
/** reg_hp_core0_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** hp_coren_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP System
* Registers.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_sysreg_allow:1;
/** reg_hp_core0_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t hp_coren_um_lp_sysreg_allow:1;
/** hp_coren_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP_AONCLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_aonclkrst_allow:1;
/** reg_hp_core0_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t hp_coren_um_lp_aonclkrst_allow:1;
/** hp_coren_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_timer_allow:1;
/** reg_hp_core0_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t hp_coren_um_lp_timer_allow:1;
/** hp_coren_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP ANAPERI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_anaperi_allow:1;
/** reg_hp_core0_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t hp_coren_um_lp_anaperi_allow:1;
/** hp_coren_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP PMU.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_pmu_allow:1;
/** reg_hp_core0_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t hp_coren_um_lp_pmu_allow:1;
/** hp_coren_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP WDT.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_wdt_allow:1;
/** reg_hp_core0_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t hp_coren_um_lp_wdt_allow:1;
/** hp_coren_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_mailbox_allow:1;
/** reg_hp_core0_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t hp_coren_um_lp_mailbox_allow:1;
/** hp_coren_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_um_lp_rtc_allow:1;
/** reg_hp_core0_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t hp_coren_um_lp_rtc_allow:1;
/** hp_coren_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP PERICLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_periclkrst_allow:1;
/** reg_hp_core0_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t hp_coren_um_lp_periclkrst_allow:1;
/** hp_coren_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_uart_allow:1;
/** reg_hp_core0_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t hp_coren_um_lp_uart_allow:1;
/** hp_coren_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP I2C.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_i2c_allow:1;
/** reg_hp_core0_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t hp_coren_um_lp_i2c_allow:1;
/** hp_coren_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_spi_allow:1;
/** reg_hp_core0_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t hp_coren_um_lp_spi_allow:1;
/** hp_coren_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_i2cmst_allow:1;
/** reg_hp_core0_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t hp_coren_um_lp_i2cmst_allow:1;
/** hp_coren_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_i2s_allow:1;
/** reg_hp_core0_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t hp_coren_um_lp_i2s_allow:1;
/** hp_coren_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_adc_allow:1;
/** reg_hp_core0_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t hp_coren_um_lp_adc_allow:1;
/** hp_coren_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP touch sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_touch_allow:1;
/** reg_hp_core0_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t hp_coren_um_lp_touch_allow:1;
/** hp_coren_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_iomux_allow:1;
/** reg_hp_core0_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t hp_coren_um_lp_iomux_allow:1;
/** hp_coren_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP INTR.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_intr_allow:1;
/** reg_hp_core0_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t hp_coren_um_lp_intr_allow:1;
/** hp_coren_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_efuse_allow:1;
/** reg_hp_core0_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t hp_coren_um_lp_efuse_allow:1;
/** hp_coren_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_pms_allow:1;
/** reg_hp_core0_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
uint32_t hp_coren_um_lp_pms_allow:1;
/** hp_coren_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* Configures whether HP CPUn in user mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_hp2lp_pms_allow:1;
/** reg_hp_core0_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
uint32_t hp_coren_um_hp2lp_pms_allow:1;
/** hp_coren_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_tsens_allow:1;
/** reg_hp_core0_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t hp_coren_um_lp_tsens_allow:1;
/** hp_coren_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* Configures whether HP CPUn in user mode has permission to LP HUK.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_huk_allow:1;
/** reg_hp_core0_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t hp_coren_um_lp_huk_allow:1;
/** hp_coren_um_lp_sram_allow : R/W; bitpos: [23]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_tcm_ram_allow:1;
uint32_t hp_coren_um_lp_sram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_hp_core0_um_pms_reg0_reg_t;
} pms_hp_coren_um_pms_reg0_reg_t;
/** Group: TEE HP CORE1 MM PMS REG0 REG */
/** Type of hp_core1_mm_pms_reg0 register
* NA
/** Group: TEE Peripheral Permission Control Register */
/** Type of regdma_lp_peri_pms register
* LP Peripheral Permission register for REGDMA
*/
typedef union {
struct {
/** reg_hp_core1_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** regdma_peri_lp_sram_allow : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access LP SRAM.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_mm_lp_sysreg_allow:1;
/** reg_hp_core1_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t regdma_peri_lp_sram_allow:1;
/** regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
* Configures whether REGDMA has permission to access all LP peripherals.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_mm_lp_aonclkrst_allow:1;
/** reg_hp_core1_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_timer_allow:1;
/** reg_hp_core1_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_anaperi_allow:1;
/** reg_hp_core1_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_pmu_allow:1;
/** reg_hp_core1_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_wdt_allow:1;
/** reg_hp_core1_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_mailbox_allow:1;
/** reg_hp_core1_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_rtc_allow:1;
/** reg_hp_core1_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_periclkrst_allow:1;
/** reg_hp_core1_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_uart_allow:1;
/** reg_hp_core1_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2c_allow:1;
/** reg_hp_core1_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_spi_allow:1;
/** reg_hp_core1_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2cmst_allow:1;
/** reg_hp_core1_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2s_allow:1;
/** reg_hp_core1_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_adc_allow:1;
/** reg_hp_core1_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_touch_allow:1;
/** reg_hp_core1_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_iomux_allow:1;
/** reg_hp_core1_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_intr_allow:1;
/** reg_hp_core1_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_efuse_allow:1;
/** reg_hp_core1_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_pms_allow:1;
/** reg_hp_core1_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_hp2lp_pms_allow:1;
/** reg_hp_core1_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_tsens_allow:1;
/** reg_hp_core1_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_huk_allow:1;
/** reg_hp_core1_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_tcm_ram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_hp_core1_mm_pms_reg0_reg_t;
/** Group: TEE HP CORE1 UM PMS REG0 REG */
/** Type of hp_core1_um_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core1_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_sysreg_allow:1;
/** reg_hp_core1_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_aonclkrst_allow:1;
/** reg_hp_core1_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_timer_allow:1;
/** reg_hp_core1_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_anaperi_allow:1;
/** reg_hp_core1_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_pmu_allow:1;
/** reg_hp_core1_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_wdt_allow:1;
/** reg_hp_core1_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_mailbox_allow:1;
/** reg_hp_core1_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_rtc_allow:1;
/** reg_hp_core1_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_periclkrst_allow:1;
/** reg_hp_core1_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_uart_allow:1;
/** reg_hp_core1_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2c_allow:1;
/** reg_hp_core1_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_spi_allow:1;
/** reg_hp_core1_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2cmst_allow:1;
/** reg_hp_core1_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2s_allow:1;
/** reg_hp_core1_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_adc_allow:1;
/** reg_hp_core1_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_touch_allow:1;
/** reg_hp_core1_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_iomux_allow:1;
/** reg_hp_core1_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_intr_allow:1;
/** reg_hp_core1_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_efuse_allow:1;
/** reg_hp_core1_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_pms_allow:1;
/** reg_hp_core1_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_hp2lp_pms_allow:1;
/** reg_hp_core1_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_tsens_allow:1;
/** reg_hp_core1_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_huk_allow:1;
/** reg_hp_core1_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_tcm_ram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_hp_core1_um_pms_reg0_reg_t;
/** Group: TEE REGDMA PERI PMS REG */
/** Type of regdma_peri_pms register
* NA
*/
typedef union {
struct {
/** reg_regdma_peri_lp_ram_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_regdma_peri_lp_ram_allow:1;
/** reg_regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_regdma_peri_lp_peri_allow:1;
uint32_t regdma_peri_lp_peri_allow:1;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_regdma_peri_pms_reg_t;
} pms_regdma_lp_peri_pms_reg_t;
typedef struct {
volatile tee_hp2lp_tee_pms_date_reg_t hp2lp_tee_pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_hp_core0_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
volatile tee_hp_core0_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
volatile tee_hp_core1_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
volatile tee_hp_core1_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
volatile tee_regdma_peri_pms_reg_t regdma_peri_pms;
} tee_dev_t;
volatile pms_hp2lp_peri_pms_date_reg_t hp2lp_peri_pms_date;
volatile pms_hp2lp_peri_pms_clk_en_reg_t hp2lp_peri_pms_clk_en;
volatile pms_hp_coren_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
volatile pms_hp_coren_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
volatile pms_hp_coren_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
volatile pms_hp_coren_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
volatile pms_regdma_lp_peri_pms_reg_t regdma_lp_peri_pms;
} hp2lp_peri_pms_dev_t;
extern hp2lp_peri_pms_dev_t HP2LP_PERI_PMS;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x1c, "Invalid size of tee_dev_t structure");
_Static_assert(sizeof(hp2lp_peri_pms_dev_t) == 0x1c, "Invalid size of hp2lp_peri_pms_dev_t structure");
#endif
#ifdef __cplusplus

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components/soc/esp32p4/include/soc/hp_peri_pms_reg.h
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components/soc/esp32p4/include/soc/hp_peri_pms_struct.h
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components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h
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components/soc/esp32p4/include/soc/lp2hp_peri_pms_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,398 +10,574 @@
extern "C" {
#endif
/** Group: TEE LP2HP PMS DATE REG */
/** Type of lp2hp_pms_date register
* NA
/** Group: Version Control Registers */
/** Type of lp2hp_peri_pms_date register
* Version control register
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2294790;
* NA
/** lp2hp_peri_pms_date : R/W; bitpos: [31:0]; default: 2294790;
* Version control register.
*/
uint32_t tee_date:32;
uint32_t lp2hp_peri_pms_date:32;
};
uint32_t val;
} tee_lp2hp_pms_date_reg_t;
} pms_lp2hp_peri_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
/** Group: Clock Gating Registers */
/** Type of lp2hp_peri_pms_clk_en register
* Clock gating register
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
/** lp2hp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating.
* 1: Keep the clock always on.
*/
uint32_t reg_clk_en:1;
uint32_t lp2hp_peri_pms_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
} pms_lp2hp_peri_pms_clk_en_reg_t;
/** Group: TEE LP MM PMS REG0 REG */
/** Group: LP CPU Permission Control Registers */
/** Type of lp_mm_pms_reg0 register
* NA
* Permission control register0 for the LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_psram_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_psram_allow : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access external RAM
* without going through cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_psram_allow:1;
/** reg_lp_mm_flash_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_psram_allow:1;
/** lp_mm_flash_allow : R/W; bitpos: [1]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access external
* flash without going through cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_flash_allow:1;
/** reg_lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_flash_allow:1;
/** lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP L2M2M
* without going through cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_l2mem_allow:1;
/** reg_lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_l2mem_allow:1;
/** lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP ROM
* without going through cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_l2rom_allow:1;
uint32_t lp_mm_l2rom_allow:1;
uint32_t reserved_4:2;
/** reg_lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
* NA
/** lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access TRACE0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_trace0_allow:1;
/** reg_lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t lp_mm_trace0_allow:1;
/** lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access TRACE1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_trace1_allow:1;
/** reg_lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t lp_mm_trace1_allow:1;
/** lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access CPU bus
* monitor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_cpu_bus_mon_allow:1;
/** reg_lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t lp_mm_cpu_bus_mon_allow:1;
/** lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access L2MEM
* monitor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_l2mem_mon_allow:1;
/** reg_lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t lp_mm_l2mem_mon_allow:1;
/** lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access TCM monitor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_tcm_mon_allow:1;
/** reg_lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t lp_mm_tcm_mon_allow:1;
/** lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_cache_allow:1;
uint32_t lp_mm_cache_allow:1;
uint32_t reserved_12:20;
};
uint32_t val;
} tee_lp_mm_pms_reg0_reg_t;
} pms_lp_mm_pms_reg0_reg_t;
/** Group: TEE LP MM PMS REG1 REG */
/** Type of lp_mm_pms_reg1 register
* NA
* Permission control register1 for the LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* high-speed USB 2.0 OTG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_usbotg_allow:1;
/** reg_lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_hp_usbotg_allow:1;
/** lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* full-speed USB 2.0 OTG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_usbotg11_allow:1;
/** reg_lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_hp_usbotg11_allow:1;
/** lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* full-speed USB 2.0 OTG's wrap.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_usbotg11_wrap_allow:1;
/** reg_lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_hp_usbotg11_wrap_allow:1;
/** lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP DW-GDMA.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gdma_allow:1;
/** reg_lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t lp_mm_hp_gdma_allow:1;
/** lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GDMA (DW
* GDMA).
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_mm_hp_regdma_allow:1;
/** reg_lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t lp_mm_hp_regdma_allow:1;
/** lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_sdmmc_allow:1;
/** reg_lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t lp_mm_hp_sdmmc_allow:1;
/** lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access GDMA-AHB.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_ahb_pdma_allow:1;
/** reg_lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t lp_mm_hp_ahb_pdma_allow:1;
/** lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP JPEG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_jpeg_allow:1;
/** reg_lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t lp_mm_hp_jpeg_allow:1;
/** lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PPA.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_ppa_allow:1;
/** reg_lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t lp_mm_hp_ppa_allow:1;
/** lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP 2D-DMA.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_dma2d_allow:1;
/** reg_lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t lp_mm_hp_dma2d_allow:1;
/** lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP key
* manager.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_key_manager_allow:1;
/** reg_lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t lp_mm_hp_key_manager_allow:1;
/** lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GDMA-AXI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_axi_pdma_allow:1;
/** reg_lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t lp_mm_hp_axi_pdma_allow:1;
/** lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP flash
* MSPI controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_flash_allow:1;
/** reg_lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t lp_mm_hp_flash_allow:1;
/** lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PSRAM
* MSPI controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_psram_allow:1;
/** reg_lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t lp_mm_hp_psram_allow:1;
/** lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP CRYPTO.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_crypto_allow:1;
/** reg_lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t lp_mm_hp_crypto_allow:1;
/** lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP EMAC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gmac_allow:1;
/** reg_lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t lp_mm_hp_gmac_allow:1;
/** lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* high-speed USB 2.0 OTG PHY.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_usb_phy_allow:1;
/** reg_lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t lp_mm_hp_usb_phy_allow:1;
/** lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PVT.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_mm_hp_pvt_allow:1;
/** reg_lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t lp_mm_hp_pvt_allow:1;
/** lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP MIPI CSI
* host.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_csi_host_allow:1;
/** reg_lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t lp_mm_hp_csi_host_allow:1;
/** lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP MIPI DSI
* host.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_dsi_host_allow:1;
/** reg_lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
* NA
uint32_t lp_mm_hp_dsi_host_allow:1;
/** lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP ISP.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_isp_allow:1;
/** reg_lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
* NA
uint32_t lp_mm_hp_isp_allow:1;
/** lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP H264
* Encoder.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_h264_core_allow:1;
/** reg_lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t lp_mm_hp_h264_core_allow:1;
/** lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP RMT.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_rmt_allow:1;
/** reg_lp_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t lp_mm_hp_rmt_allow:1;
/** lp_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP bit
* scrambler.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_bitsrambler_allow:1;
/** reg_lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
* NA
uint32_t lp_mm_hp_bitsrambler_allow:1;
/** lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP AXI ICM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_axi_icm_allow:1;
/** reg_lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
* NA
uint32_t lp_mm_hp_axi_icm_allow:1;
/** lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access
* HP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_peri_pms_allow:1;
/** reg_lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
* NA
uint32_t lp_mm_hp_peri_pms_allow:1;
/** lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access
* LP2HP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp2hp_peri_pms_allow:1;
/** reg_lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
* NA
uint32_t lp_mm_lp2hp_peri_pms_allow:1;
/** lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access
* HP_DMA_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_dma_pms_allow:1;
/** reg_lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
* NA
uint32_t lp_mm_dma_pms_allow:1;
/** lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access 2D-DMA.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_h264_dma2d_allow:1;
uint32_t lp_mm_hp_h264_dma2d_allow:1;
uint32_t reserved_29:3;
};
uint32_t val;
} tee_lp_mm_pms_reg1_reg_t;
} pms_lp_mm_pms_reg1_reg_t;
/** Group: TEE LP MM PMS REG2 REG */
/** Type of lp_mm_pms_reg2 register
* NA
* Permission control register2 for the LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP MCPWM0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_mcpwm0_allow:1;
/** reg_lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_hp_mcpwm0_allow:1;
/** lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP MCPWM1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_mcpwm1_allow:1;
/** reg_lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_hp_mcpwm1_allow:1;
/** lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP timer
* group0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_timer_group0_allow:1;
/** reg_lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_hp_timer_group0_allow:1;
/** lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP timer
* group1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_timer_group1_allow:1;
/** reg_lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t lp_mm_hp_timer_group1_allow:1;
/** lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2C0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2c0_allow:1;
/** reg_lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t lp_mm_hp_i2c0_allow:1;
/** lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2C1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2c1_allow:1;
/** reg_lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t lp_mm_hp_i2c1_allow:1;
/** lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2S0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2s0_allow:1;
/** reg_lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t lp_mm_hp_i2s0_allow:1;
/** lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2S1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2s1_allow:1;
/** reg_lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t lp_mm_hp_i2s1_allow:1;
/** lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2S2.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2s2_allow:1;
/** reg_lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t lp_mm_hp_i2s2_allow:1;
/** lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PCNT.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_pcnt_allow:1;
/** reg_lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t lp_mm_hp_pcnt_allow:1;
/** lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart0_allow:1;
/** reg_lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t lp_mm_hp_uart0_allow:1;
/** lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart1_allow:1;
/** reg_lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t lp_mm_hp_uart1_allow:1;
/** lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART2.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart2_allow:1;
/** reg_lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t lp_mm_hp_uart2_allow:1;
/** lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART3.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart3_allow:1;
/** reg_lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t lp_mm_hp_uart3_allow:1;
/** lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART4.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart4_allow:1;
/** reg_lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t lp_mm_hp_uart4_allow:1;
/** lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PARLIO.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_parlio_allow:1;
/** reg_lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t lp_mm_hp_parlio_allow:1;
/** lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GP-SPI2.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gpspi2_allow:1;
/** reg_lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t lp_mm_hp_gpspi2_allow:1;
/** lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GP-SPI3.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gpspi3_allow:1;
/** reg_lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t lp_mm_hp_gpspi3_allow:1;
/** lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* USB/Serial JTAG Controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_usbdevice_allow:1;
/** reg_lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t lp_mm_hp_usbdevice_allow:1;
/** lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP LEDC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_ledc_allow:1;
uint32_t lp_mm_hp_ledc_allow:1;
uint32_t reserved_20:1;
/** reg_lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
* NA
/** lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP ETM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_etm_allow:1;
/** reg_lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t lp_mm_hp_etm_allow:1;
/** lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP interrupt
* matrix.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_intrmtx_allow:1;
/** reg_lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t lp_mm_hp_intrmtx_allow:1;
/** lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP TWAI0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_twai0_allow:1;
/** reg_lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
* NA
uint32_t lp_mm_hp_twai0_allow:1;
/** lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP TWAI1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_twai1_allow:1;
/** reg_lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
* NA
uint32_t lp_mm_hp_twai1_allow:1;
/** lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP TWAI2.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_twai2_allow:1;
/** reg_lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
* NA
uint32_t lp_mm_hp_twai2_allow:1;
/** lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I3C
* master controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i3c_mst_allow:1;
/** reg_lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
* NA
uint32_t lp_mm_hp_i3c_mst_allow:1;
/** lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I3C slave
* controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i3c_slv_allow:1;
/** reg_lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
* NA
uint32_t lp_mm_hp_i3c_slv_allow:1;
/** lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP LCD_CAM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_lcdcam_allow:1;
uint32_t lp_mm_hp_lcdcam_allow:1;
uint32_t reserved_29:1;
/** reg_lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
* NA
/** lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP ADC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_adc_allow:1;
/** reg_lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
* NA
uint32_t lp_mm_hp_adc_allow:1;
/** lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UHCI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uhci_allow:1;
uint32_t lp_mm_hp_uhci_allow:1;
};
uint32_t val;
} tee_lp_mm_pms_reg2_reg_t;
} pms_lp_mm_pms_reg2_reg_t;
/** Group: TEE LP MM PMS REG3 REG */
/** Type of lp_mm_pms_reg3 register
* NA
* Permission control register3 for the LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GPIO
* Matrix.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gpio_allow:1;
/** reg_lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_hp_gpio_allow:1;
/** lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_iomux_allow:1;
/** reg_lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_hp_iomux_allow:1;
/** lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP system
* timer.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_systimer_allow:1;
/** reg_lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_hp_systimer_allow:1;
/** lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP system
* register.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_sys_reg_allow:1;
/** reg_lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t lp_mm_hp_sys_reg_allow:1;
/** lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access
* HP_SYS_CLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_clkrst_allow:1;
uint32_t lp_mm_hp_clkrst_allow:1;
uint32_t reserved_5:27;
};
uint32_t val;
} tee_lp_mm_pms_reg3_reg_t;
} pms_lp_mm_pms_reg3_reg_t;
typedef struct {
volatile tee_lp2hp_pms_date_reg_t lp2hp_pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
volatile pms_lp2hp_peri_pms_date_reg_t lp2hp_peri_pms_date;
volatile pms_lp2hp_peri_pms_clk_en_reg_t lp2hp_peri_pms_clk_en;
volatile pms_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
uint32_t reserved_00c[9];
volatile tee_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1;
volatile pms_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1;
uint32_t reserved_034[28];
volatile tee_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2;
volatile pms_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2;
uint32_t reserved_0a8[29];
volatile tee_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3;
} tee_dev_t;
volatile pms_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3;
} lp2hp_peri_pms_dev_t;
extern lp2hp_peri_pms_dev_t LP2HP_PERI_PMS;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x120, "Invalid size of tee_dev_t structure");
_Static_assert(sizeof(lp2hp_peri_pms_dev_t) == 0x120, "Invalid size of lp2hp_peri_pms_dev_t structure");
#endif
#ifdef __cplusplus

546
components/soc/esp32p4/include/soc/lp_peri_pms_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,290 +11,366 @@
extern "C" {
#endif
/** TEE_PMS_DATE_REG register
* NA
/** PMS_LP_PERI_PMS_DATE_REG register
* Version control register
*/
#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2294537;
* NA
#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
* Version control register
*/
#define TEE_TEE_DATE 0xFFFFFFFFU
#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
#define TEE_TEE_DATE_V 0xFFFFFFFFU
#define TEE_TEE_DATE_S 0
#define PMS_LP_PERI_PMS_DATE 0xFFFFFFFFU
#define PMS_LP_PERI_PMS_DATE_M (PMS_LP_PERI_PMS_DATE_V << PMS_LP_PERI_PMS_DATE_S)
#define PMS_LP_PERI_PMS_DATE_V 0xFFFFFFFFU
#define PMS_LP_PERI_PMS_DATE_S 0
/** TEE_PMS_CLK_EN_REG register
* NA
/** PMS_LP_PERI_PMS_CLK_EN_REG register
* Clock gating register
*/
#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* NA
#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
/** PMS_LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
#define TEE_REG_CLK_EN (BIT(0))
#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
#define TEE_REG_CLK_EN_V 0x00000001U
#define TEE_REG_CLK_EN_S 0
#define PMS_LP_PERI_PMS_CLK_EN (BIT(0))
#define PMS_LP_PERI_PMS_CLK_EN_M (PMS_LP_PERI_PMS_CLK_EN_V << PMS_LP_PERI_PMS_CLK_EN_S)
#define PMS_LP_PERI_PMS_CLK_EN_V 0x00000001U
#define PMS_LP_PERI_PMS_CLK_EN_S 0
/** TEE_LP_MM_PMS_REG0_REG register
* NA
/** PMS_LP_MM_LP_PERI_PMS_REG0_REG register
* Permission control register0 for LP CPU in machine mode
*/
#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_REG_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
/** PMS_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP system
* registers.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_M (TEE_REG_LP_MM_LP_SYSREG_ALLOW_V << TEE_REG_LP_MM_LP_SYSREG_ALLOW_S)
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
#define PMS_LP_MM_LP_SYSREG_ALLOW (BIT(0))
#define PMS_LP_MM_LP_SYSREG_ALLOW_M (PMS_LP_MM_LP_SYSREG_ALLOW_V << PMS_LP_MM_LP_SYSREG_ALLOW_S)
#define PMS_LP_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_SYSREG_ALLOW_S 0
/** PMS_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP
* always-on clock and reset).
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
#define PMS_LP_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define PMS_LP_MM_LP_AONCLKRST_ALLOW_M (PMS_LP_MM_LP_AONCLKRST_ALLOW_V << PMS_LP_MM_LP_AONCLKRST_ALLOW_S)
#define PMS_LP_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_AONCLKRST_ALLOW_S 1
/** PMS_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_LP_MM_LP_TIMER_ALLOW_M (TEE_REG_LP_MM_LP_TIMER_ALLOW_V << TEE_REG_LP_MM_LP_TIMER_ALLOW_S)
#define TEE_REG_LP_MM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TIMER_ALLOW_S 2
/** TEE_REG_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
#define PMS_LP_MM_LP_TIMER_ALLOW (BIT(2))
#define PMS_LP_MM_LP_TIMER_ALLOW_M (PMS_LP_MM_LP_TIMER_ALLOW_V << PMS_LP_MM_LP_TIMER_ALLOW_S)
#define PMS_LP_MM_LP_TIMER_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_TIMER_ALLOW_S 2
/** PMS_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP ANAPERI
* (analog peripherals).
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_M (TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V << TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
#define PMS_LP_MM_LP_ANAPERI_ALLOW (BIT(3))
#define PMS_LP_MM_LP_ANAPERI_ALLOW_M (PMS_LP_MM_LP_ANAPERI_ALLOW_V << PMS_LP_MM_LP_ANAPERI_ALLOW_S)
#define PMS_LP_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_ANAPERI_ALLOW_S 3
/** PMS_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP PMU (Power
* Management Unit).
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_LP_MM_LP_PMU_ALLOW_M (TEE_REG_LP_MM_LP_PMU_ALLOW_V << TEE_REG_LP_MM_LP_PMU_ALLOW_S)
#define TEE_REG_LP_MM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_PMU_ALLOW_S 4
/** TEE_REG_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
#define PMS_LP_MM_LP_PMU_ALLOW (BIT(4))
#define PMS_LP_MM_LP_PMU_ALLOW_M (PMS_LP_MM_LP_PMU_ALLOW_V << PMS_LP_MM_LP_PMU_ALLOW_S)
#define PMS_LP_MM_LP_PMU_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_PMU_ALLOW_S 4
/** PMS_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog
* timer).
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_LP_MM_LP_WDT_ALLOW_M (TEE_REG_LP_MM_LP_WDT_ALLOW_V << TEE_REG_LP_MM_LP_WDT_ALLOW_S)
#define TEE_REG_LP_MM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_WDT_ALLOW_S 5
/** TEE_REG_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
#define PMS_LP_MM_LP_WDT_ALLOW (BIT(5))
#define PMS_LP_MM_LP_WDT_ALLOW_M (PMS_LP_MM_LP_WDT_ALLOW_V << PMS_LP_MM_LP_WDT_ALLOW_S)
#define PMS_LP_MM_LP_WDT_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_WDT_ALLOW_S 5
/** PMS_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_M (TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V << TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
#define PMS_LP_MM_LP_MAILBOX_ALLOW (BIT(6))
#define PMS_LP_MM_LP_MAILBOX_ALLOW_M (PMS_LP_MM_LP_MAILBOX_ALLOW_V << PMS_LP_MM_LP_MAILBOX_ALLOW_S)
#define PMS_LP_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_MAILBOX_ALLOW_S 6
/** PMS_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
#define TEE_REG_LP_MM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_LP_MM_LP_RTC_ALLOW_M (TEE_REG_LP_MM_LP_RTC_ALLOW_V << TEE_REG_LP_MM_LP_RTC_ALLOW_S)
#define TEE_REG_LP_MM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_RTC_ALLOW_S 7
/** TEE_REG_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
#define PMS_LP_MM_LP_RTC_ALLOW (BIT(7))
#define PMS_LP_MM_LP_RTC_ALLOW_M (PMS_LP_MM_LP_RTC_ALLOW_V << PMS_LP_MM_LP_RTC_ALLOW_S)
#define PMS_LP_MM_LP_RTC_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_RTC_ALLOW_S 7
/** PMS_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP PREICLKRST
* (peripheral clock and reset).
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
#define PMS_LP_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define PMS_LP_MM_LP_PERICLKRST_ALLOW_M (PMS_LP_MM_LP_PERICLKRST_ALLOW_V << PMS_LP_MM_LP_PERICLKRST_ALLOW_S)
#define PMS_LP_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_PERICLKRST_ALLOW_S 8
/** PMS_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_LP_MM_LP_UART_ALLOW_M (TEE_REG_LP_MM_LP_UART_ALLOW_V << TEE_REG_LP_MM_LP_UART_ALLOW_S)
#define TEE_REG_LP_MM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_UART_ALLOW_S 9
/** TEE_REG_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
#define PMS_LP_MM_LP_UART_ALLOW (BIT(9))
#define PMS_LP_MM_LP_UART_ALLOW_M (PMS_LP_MM_LP_UART_ALLOW_V << PMS_LP_MM_LP_UART_ALLOW_S)
#define PMS_LP_MM_LP_UART_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_UART_ALLOW_S 9
/** PMS_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_LP_MM_LP_I2C_ALLOW_M (TEE_REG_LP_MM_LP_I2C_ALLOW_V << TEE_REG_LP_MM_LP_I2C_ALLOW_S)
#define TEE_REG_LP_MM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_I2C_ALLOW_S 10
/** TEE_REG_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
#define PMS_LP_MM_LP_I2C_ALLOW (BIT(10))
#define PMS_LP_MM_LP_I2C_ALLOW_M (PMS_LP_MM_LP_I2C_ALLOW_V << PMS_LP_MM_LP_I2C_ALLOW_S)
#define PMS_LP_MM_LP_I2C_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_I2C_ALLOW_S 10
/** PMS_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_LP_MM_LP_SPI_ALLOW_M (TEE_REG_LP_MM_LP_SPI_ALLOW_V << TEE_REG_LP_MM_LP_SPI_ALLOW_S)
#define TEE_REG_LP_MM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_SPI_ALLOW_S 11
/** TEE_REG_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
#define PMS_LP_MM_LP_SPI_ALLOW (BIT(11))
#define PMS_LP_MM_LP_SPI_ALLOW_M (PMS_LP_MM_LP_SPI_ALLOW_V << PMS_LP_MM_LP_SPI_ALLOW_S)
#define PMS_LP_MM_LP_SPI_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_SPI_ALLOW_S 11
/** PMS_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_M (TEE_REG_LP_MM_LP_I2CMST_ALLOW_V << TEE_REG_LP_MM_LP_I2CMST_ALLOW_S)
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
#define PMS_LP_MM_LP_I2CMST_ALLOW (BIT(12))
#define PMS_LP_MM_LP_I2CMST_ALLOW_M (PMS_LP_MM_LP_I2CMST_ALLOW_V << PMS_LP_MM_LP_I2CMST_ALLOW_S)
#define PMS_LP_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_I2CMST_ALLOW_S 12
/** PMS_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_LP_MM_LP_I2S_ALLOW_M (TEE_REG_LP_MM_LP_I2S_ALLOW_V << TEE_REG_LP_MM_LP_I2S_ALLOW_S)
#define TEE_REG_LP_MM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_I2S_ALLOW_S 13
/** TEE_REG_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
#define PMS_LP_MM_LP_I2S_ALLOW (BIT(13))
#define PMS_LP_MM_LP_I2S_ALLOW_M (PMS_LP_MM_LP_I2S_ALLOW_V << PMS_LP_MM_LP_I2S_ALLOW_S)
#define PMS_LP_MM_LP_I2S_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_I2S_ALLOW_S 13
/** PMS_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_LP_MM_LP_ADC_ALLOW_M (TEE_REG_LP_MM_LP_ADC_ALLOW_V << TEE_REG_LP_MM_LP_ADC_ALLOW_S)
#define TEE_REG_LP_MM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_ADC_ALLOW_S 14
/** TEE_REG_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
#define PMS_LP_MM_LP_ADC_ALLOW (BIT(14))
#define PMS_LP_MM_LP_ADC_ALLOW_M (PMS_LP_MM_LP_ADC_ALLOW_V << PMS_LP_MM_LP_ADC_ALLOW_S)
#define PMS_LP_MM_LP_ADC_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_ADC_ALLOW_S 14
/** PMS_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP touch sensor.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_M (TEE_REG_LP_MM_LP_TOUCH_ALLOW_V << TEE_REG_LP_MM_LP_TOUCH_ALLOW_S)
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
#define PMS_LP_MM_LP_TOUCH_ALLOW (BIT(15))
#define PMS_LP_MM_LP_TOUCH_ALLOW_M (PMS_LP_MM_LP_TOUCH_ALLOW_V << PMS_LP_MM_LP_TOUCH_ALLOW_S)
#define PMS_LP_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_TOUCH_ALLOW_S 15
/** PMS_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_M (TEE_REG_LP_MM_LP_IOMUX_ALLOW_V << TEE_REG_LP_MM_LP_IOMUX_ALLOW_S)
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
#define PMS_LP_MM_LP_IOMUX_ALLOW (BIT(16))
#define PMS_LP_MM_LP_IOMUX_ALLOW_M (PMS_LP_MM_LP_IOMUX_ALLOW_V << PMS_LP_MM_LP_IOMUX_ALLOW_S)
#define PMS_LP_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_IOMUX_ALLOW_S 16
/** PMS_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP INTR
* (interrupt).
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_LP_MM_LP_INTR_ALLOW_M (TEE_REG_LP_MM_LP_INTR_ALLOW_V << TEE_REG_LP_MM_LP_INTR_ALLOW_S)
#define TEE_REG_LP_MM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_INTR_ALLOW_S 17
/** TEE_REG_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
#define PMS_LP_MM_LP_INTR_ALLOW (BIT(17))
#define PMS_LP_MM_LP_INTR_ALLOW_M (PMS_LP_MM_LP_INTR_ALLOW_V << PMS_LP_MM_LP_INTR_ALLOW_S)
#define PMS_LP_MM_LP_INTR_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_INTR_ALLOW_S 17
/** PMS_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_M (TEE_REG_LP_MM_LP_EFUSE_ALLOW_V << TEE_REG_LP_MM_LP_EFUSE_ALLOW_S)
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
#define PMS_LP_MM_LP_EFUSE_ALLOW (BIT(18))
#define PMS_LP_MM_LP_EFUSE_ALLOW_M (PMS_LP_MM_LP_EFUSE_ALLOW_V << PMS_LP_MM_LP_EFUSE_ALLOW_S)
#define PMS_LP_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_EFUSE_ALLOW_S 18
/** PMS_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_LP_MM_LP_PMS_ALLOW_M (TEE_REG_LP_MM_LP_PMS_ALLOW_V << TEE_REG_LP_MM_LP_PMS_ALLOW_S)
#define TEE_REG_LP_MM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_PMS_ALLOW_S 19
/** TEE_REG_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
#define PMS_LP_MM_LP_PMS_ALLOW (BIT(19))
#define PMS_LP_MM_LP_PMS_ALLOW_M (PMS_LP_MM_LP_PMS_ALLOW_V << PMS_LP_MM_LP_PMS_ALLOW_S)
#define PMS_LP_MM_LP_PMS_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_PMS_ALLOW_S 19
/** PMS_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* Configures whether LP CPU in machine mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_M (TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V << TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
#define PMS_LP_MM_HP2LP_PMS_ALLOW (BIT(20))
#define PMS_LP_MM_HP2LP_PMS_ALLOW_M (PMS_LP_MM_HP2LP_PMS_ALLOW_V << PMS_LP_MM_HP2LP_PMS_ALLOW_S)
#define PMS_LP_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define PMS_LP_MM_HP2LP_PMS_ALLOW_S 20
/** PMS_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_LP_MM_LP_TSENS_ALLOW_M (TEE_REG_LP_MM_LP_TSENS_ALLOW_V << TEE_REG_LP_MM_LP_TSENS_ALLOW_S)
#define TEE_REG_LP_MM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TSENS_ALLOW_S 21
/** TEE_REG_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
#define PMS_LP_MM_LP_TSENS_ALLOW (BIT(21))
#define PMS_LP_MM_LP_TSENS_ALLOW_M (PMS_LP_MM_LP_TSENS_ALLOW_V << PMS_LP_MM_LP_TSENS_ALLOW_S)
#define PMS_LP_MM_LP_TSENS_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_TSENS_ALLOW_S 21
/** PMS_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware
* Unique Key).
* 0: Not allowed
* 1: Allowed
*/
#define TEE_REG_LP_MM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_LP_MM_LP_HUK_ALLOW_M (TEE_REG_LP_MM_LP_HUK_ALLOW_V << TEE_REG_LP_MM_LP_HUK_ALLOW_S)
#define TEE_REG_LP_MM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_HUK_ALLOW_S 22
/** TEE_REG_LP_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
#define PMS_LP_MM_LP_HUK_ALLOW (BIT(22))
#define PMS_LP_MM_LP_HUK_ALLOW_M (PMS_LP_MM_LP_HUK_ALLOW_V << PMS_LP_MM_LP_HUK_ALLOW_S)
#define PMS_LP_MM_LP_HUK_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_HUK_ALLOW_S 22
/** PMS_LP_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allow
*/
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S 23
#define PMS_LP_MM_LP_SRAM_ALLOW (BIT(23))
#define PMS_LP_MM_LP_SRAM_ALLOW_M (PMS_LP_MM_LP_SRAM_ALLOW_V << PMS_LP_MM_LP_SRAM_ALLOW_S)
#define PMS_LP_MM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_SRAM_ALLOW_S 23
/** TEE_PERI_REGION0_LOW_REG register
* NA
/** PMS_PERI_REGION0_LOW_REG register
* Region0 start address configuration register
*/
#define TEE_PERI_REGION0_LOW_REG (DR_REG_TEE_BASE + 0xc)
/** TEE_REG_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
#define PMS_PERI_REGION0_LOW_REG (DR_REG_PMS_BASE + 0xc)
/** PMS_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region0.
*/
#define TEE_REG_PERI_REGION0_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_LOW_M (TEE_REG_PERI_REGION0_LOW_V << TEE_REG_PERI_REGION0_LOW_S)
#define TEE_REG_PERI_REGION0_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_LOW_S 2
#define PMS_PERI_REGION0_LOW 0x3FFFFFFFU
#define PMS_PERI_REGION0_LOW_M (PMS_PERI_REGION0_LOW_V << PMS_PERI_REGION0_LOW_S)
#define PMS_PERI_REGION0_LOW_V 0x3FFFFFFFU
#define PMS_PERI_REGION0_LOW_S 2
/** TEE_PERI_REGION0_HIGH_REG register
* NA
/** PMS_PERI_REGION0_HIGH_REG register
* Region0 end address configuration register
*/
#define TEE_PERI_REGION0_HIGH_REG (DR_REG_TEE_BASE + 0x10)
/** TEE_REG_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
#define PMS_PERI_REGION0_HIGH_REG (DR_REG_PMS_BASE + 0x10)
/** PMS_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region0.
*/
#define TEE_REG_PERI_REGION0_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_HIGH_M (TEE_REG_PERI_REGION0_HIGH_V << TEE_REG_PERI_REGION0_HIGH_S)
#define TEE_REG_PERI_REGION0_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_HIGH_S 2
#define PMS_PERI_REGION0_HIGH 0x3FFFFFFFU
#define PMS_PERI_REGION0_HIGH_M (PMS_PERI_REGION0_HIGH_V << PMS_PERI_REGION0_HIGH_S)
#define PMS_PERI_REGION0_HIGH_V 0x3FFFFFFFU
#define PMS_PERI_REGION0_HIGH_S 2
/** TEE_PERI_REGION1_LOW_REG register
* NA
/** PMS_PERI_REGION1_LOW_REG register
* Region1 start address configuration register
*/
#define TEE_PERI_REGION1_LOW_REG (DR_REG_TEE_BASE + 0x14)
/** TEE_REG_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
#define PMS_PERI_REGION1_LOW_REG (DR_REG_PMS_BASE + 0x14)
/** PMS_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region1.
*/
#define TEE_REG_PERI_REGION1_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_LOW_M (TEE_REG_PERI_REGION1_LOW_V << TEE_REG_PERI_REGION1_LOW_S)
#define TEE_REG_PERI_REGION1_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_LOW_S 2
#define PMS_PERI_REGION1_LOW 0x3FFFFFFFU
#define PMS_PERI_REGION1_LOW_M (PMS_PERI_REGION1_LOW_V << PMS_PERI_REGION1_LOW_S)
#define PMS_PERI_REGION1_LOW_V 0x3FFFFFFFU
#define PMS_PERI_REGION1_LOW_S 2
/** TEE_PERI_REGION1_HIGH_REG register
* NA
/** PMS_PERI_REGION1_HIGH_REG register
* Region1 end address configuration register
*/
#define TEE_PERI_REGION1_HIGH_REG (DR_REG_TEE_BASE + 0x18)
/** TEE_REG_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
#define PMS_PERI_REGION1_HIGH_REG (DR_REG_PMS_BASE + 0x18)
/** PMS_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region1.
*/
#define TEE_REG_PERI_REGION1_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_HIGH_M (TEE_REG_PERI_REGION1_HIGH_V << TEE_REG_PERI_REGION1_HIGH_S)
#define TEE_REG_PERI_REGION1_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_HIGH_S 2
#define PMS_PERI_REGION1_HIGH 0x3FFFFFFFU
#define PMS_PERI_REGION1_HIGH_M (PMS_PERI_REGION1_HIGH_V << PMS_PERI_REGION1_HIGH_S)
#define PMS_PERI_REGION1_HIGH_V 0x3FFFFFFFU
#define PMS_PERI_REGION1_HIGH_S 2
/** TEE_PERI_REGION_PMS_REG register
* NA
/** PMS_PERI_REGION_PMS_REG register
* Permission register of region
*/
#define TEE_PERI_REGION_PMS_REG (DR_REG_TEE_BASE + 0x1c)
/** TEE_REG_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
* NA
#define PMS_PERI_REGION_PMS_REG (DR_REG_PMS_BASE + 0x1c)
/** PMS_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
* Configures whether LP core in machine mode has permission to access address region0
* and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
#define TEE_REG_LP_CORE_REGION_PMS 0x00000003U
#define TEE_REG_LP_CORE_REGION_PMS_M (TEE_REG_LP_CORE_REGION_PMS_V << TEE_REG_LP_CORE_REGION_PMS_S)
#define TEE_REG_LP_CORE_REGION_PMS_V 0x00000003U
#define TEE_REG_LP_CORE_REGION_PMS_S 0
/** TEE_REG_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
* NA
#define PMS_LP_CORE_REGION_PMS 0x00000003U
#define PMS_LP_CORE_REGION_PMS_M (PMS_LP_CORE_REGION_PMS_V << PMS_LP_CORE_REGION_PMS_S)
#define PMS_LP_CORE_REGION_PMS_V 0x00000003U
#define PMS_LP_CORE_REGION_PMS_S 0
/** PMS_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
* Configures whether HP CPU0 in user mode has permission to access address region0
* and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
#define TEE_REG_HP_CORE0_UM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE0_UM_REGION_PMS_M (TEE_REG_HP_CORE0_UM_REGION_PMS_V << TEE_REG_HP_CORE0_UM_REGION_PMS_S)
#define TEE_REG_HP_CORE0_UM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE0_UM_REGION_PMS_S 2
/** TEE_REG_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
* NA
#define PMS_HP_CORE0_UM_REGION_PMS 0x00000003U
#define PMS_HP_CORE0_UM_REGION_PMS_M (PMS_HP_CORE0_UM_REGION_PMS_V << PMS_HP_CORE0_UM_REGION_PMS_S)
#define PMS_HP_CORE0_UM_REGION_PMS_V 0x00000003U
#define PMS_HP_CORE0_UM_REGION_PMS_S 2
/** PMS_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
* Configures whether HP CPU0 in machine mode has permission to access address region0
* and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
#define TEE_REG_HP_CORE0_MM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE0_MM_REGION_PMS_M (TEE_REG_HP_CORE0_MM_REGION_PMS_V << TEE_REG_HP_CORE0_MM_REGION_PMS_S)
#define TEE_REG_HP_CORE0_MM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE0_MM_REGION_PMS_S 4
/** TEE_REG_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
* NA
#define PMS_HP_CORE0_MM_REGION_PMS 0x00000003U
#define PMS_HP_CORE0_MM_REGION_PMS_M (PMS_HP_CORE0_MM_REGION_PMS_V << PMS_HP_CORE0_MM_REGION_PMS_S)
#define PMS_HP_CORE0_MM_REGION_PMS_V 0x00000003U
#define PMS_HP_CORE0_MM_REGION_PMS_S 4
/** PMS_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
* Configures whether HP CPU1 in user mode has permission to access address region0
* and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
#define TEE_REG_HP_CORE1_UM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE1_UM_REGION_PMS_M (TEE_REG_HP_CORE1_UM_REGION_PMS_V << TEE_REG_HP_CORE1_UM_REGION_PMS_S)
#define TEE_REG_HP_CORE1_UM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE1_UM_REGION_PMS_S 6
/** TEE_REG_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
* NA
#define PMS_HP_CORE1_UM_REGION_PMS 0x00000003U
#define PMS_HP_CORE1_UM_REGION_PMS_M (PMS_HP_CORE1_UM_REGION_PMS_V << PMS_HP_CORE1_UM_REGION_PMS_S)
#define PMS_HP_CORE1_UM_REGION_PMS_V 0x00000003U
#define PMS_HP_CORE1_UM_REGION_PMS_S 6
/** PMS_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
* Configures whether HP CPU1 in machine mode has permission to access address region0
* and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
#define TEE_REG_HP_CORE1_MM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE1_MM_REGION_PMS_M (TEE_REG_HP_CORE1_MM_REGION_PMS_V << TEE_REG_HP_CORE1_MM_REGION_PMS_S)
#define TEE_REG_HP_CORE1_MM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE1_MM_REGION_PMS_S 8
#define PMS_HP_CORE1_MM_REGION_PMS 0x00000003U
#define PMS_HP_CORE1_MM_REGION_PMS_M (PMS_HP_CORE1_MM_REGION_PMS_V << PMS_HP_CORE1_MM_REGION_PMS_S)
#define PMS_HP_CORE1_MM_REGION_PMS_V 0x00000003U
#define PMS_HP_CORE1_MM_REGION_PMS_S 8
#ifdef __cplusplus
}

375
components/soc/esp32p4/include/soc/lp_peri_pms_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,255 +10,298 @@
extern "C" {
#endif
/** Group: TEE PMS DATE REG */
/** Type of pms_date register
* NA
/** Group: Version Control Registers */
/** Type of lp_peri_pms_date register
* Version control register
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2294537;
* NA
/** lp_peri_pms_date : R/W; bitpos: [31:0]; default: 2294537;
* Version control register
*/
uint32_t tee_date:32;
uint32_t lp_peri_pms_date:32;
};
uint32_t val;
} tee_pms_date_reg_t;
} pms_lp_peri_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
/** Group: Clock Gating Registers */
/** Type of lp_peri_pms_clk_en register
* Clock gating register
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
/** lp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
uint32_t reg_clk_en:1;
uint32_t lp_peri_pms_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
} pms_lp_peri_pms_clk_en_reg_t;
/** Group: TEE LP MM PMS REG0 REG */
/** Type of lp_mm_pms_reg0 register
* NA
/** Group: LP CPU Permission Control Registers */
/** Type of lp_mm_lp_peri_pms_reg0 register
* Permission control register0 for LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP system
* registers.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_sysreg_allow:1;
/** reg_lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_lp_sysreg_allow:1;
/** lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP
* always-on clock and reset).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_aonclkrst_allow:1;
/** reg_lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_lp_aonclkrst_allow:1;
/** lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_timer_allow:1;
/** reg_lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_lp_timer_allow:1;
/** lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP ANAPERI
* (analog peripherals).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_anaperi_allow:1;
/** reg_lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t lp_mm_lp_anaperi_allow:1;
/** lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP PMU (Power
* Management Unit).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_pmu_allow:1;
/** reg_lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t lp_mm_lp_pmu_allow:1;
/** lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog
* timer).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_wdt_allow:1;
/** reg_lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t lp_mm_lp_wdt_allow:1;
/** lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_mailbox_allow:1;
/** reg_lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t lp_mm_lp_mailbox_allow:1;
/** lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_mm_lp_rtc_allow:1;
/** reg_lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t lp_mm_lp_rtc_allow:1;
/** lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP PREICLKRST
* (peripheral clock and reset).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_periclkrst_allow:1;
/** reg_lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t lp_mm_lp_periclkrst_allow:1;
/** lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_uart_allow:1;
/** reg_lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t lp_mm_lp_uart_allow:1;
/** lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_i2c_allow:1;
/** reg_lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t lp_mm_lp_i2c_allow:1;
/** lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_spi_allow:1;
/** reg_lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t lp_mm_lp_spi_allow:1;
/** lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_i2cmst_allow:1;
/** reg_lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t lp_mm_lp_i2cmst_allow:1;
/** lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_i2s_allow:1;
/** reg_lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t lp_mm_lp_i2s_allow:1;
/** lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_adc_allow:1;
/** reg_lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t lp_mm_lp_adc_allow:1;
/** lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP touch sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_touch_allow:1;
/** reg_lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t lp_mm_lp_touch_allow:1;
/** lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_iomux_allow:1;
/** reg_lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t lp_mm_lp_iomux_allow:1;
/** lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP INTR
* (interrupt).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_intr_allow:1;
/** reg_lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t lp_mm_lp_intr_allow:1;
/** lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_efuse_allow:1;
/** reg_lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t lp_mm_lp_efuse_allow:1;
/** lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_pms_allow:1;
/** reg_lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
uint32_t lp_mm_lp_pms_allow:1;
/** lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* Configures whether LP CPU in machine mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp2lp_pms_allow:1;
/** reg_lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
uint32_t lp_mm_hp2lp_pms_allow:1;
/** lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_tsens_allow:1;
/** reg_lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t lp_mm_lp_tsens_allow:1;
/** lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware
* Unique Key).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_huk_allow:1;
/** reg_lp_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t lp_mm_lp_huk_allow:1;
/** lp_mm_lp_sram_allow : R/W; bitpos: [23]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_mm_lp_tcm_ram_allow:1;
uint32_t lp_mm_lp_sram_allow:1;
uint32_t reserved_24:8;
};
uint32_t val;
} tee_lp_mm_pms_reg0_reg_t;
} pms_lp_mm_lp_peri_pms_reg0_reg_t;
/** Group: TEE PERI REGION0 LOW REG */
/** Type of peri_region0_low register
* NA
/** Group: Configurable Address Range Configuration Registers */
/** Type of peri_regionn_low register
* Regionn start address configuration register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region0_low : R/W; bitpos: [31:2]; default: 0;
* NA
/** peri_regionn_low : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's regionn.
*/
uint32_t reg_peri_region0_low:30;
uint32_t peri_regionn_low:30;
};
uint32_t val;
} tee_peri_region0_low_reg_t;
} pms_peri_regionn_low_reg_t;
/** Group: TEE PERI REGION0 HIGH REG */
/** Type of peri_region0_high register
* NA
/** Type of peri_regionn_high register
* Regionn end address configuration register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region0_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
/** peri_regionn_high : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's regionn.
*/
uint32_t reg_peri_region0_high:30;
uint32_t peri_regionn_high:30;
};
uint32_t val;
} tee_peri_region0_high_reg_t;
} pms_peri_regionn_high_reg_t;
/** Group: TEE PERI REGION1 LOW REG */
/** Type of peri_region1_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region1_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region1_low:30;
};
uint32_t val;
} tee_peri_region1_low_reg_t;
/** Group: TEE PERI REGION1 HIGH REG */
/** Type of peri_region1_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region1_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region1_high:30;
};
uint32_t val;
} tee_peri_region1_high_reg_t;
/** Group: TEE PERI REGION PMS REG */
/** Group: PMS Peripheral Region Permission Control Registers */
/** Type of peri_region_pms register
* NA
* Permission register of region
*/
typedef union {
struct {
/** reg_lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
* NA
/** lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
* Configures whether LP core in machine mode has permission to access address region0
* and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_core_region_pms:2;
/** reg_hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
* NA
uint32_t lp_core_region_pms:2;
/** hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
* Configures whether HP CPU0 in user mode has permission to access address region0
* and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_um_region_pms:2;
/** reg_hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
* NA
uint32_t hp_core0_um_region_pms:2;
/** hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
* Configures whether HP CPU0 in machine mode has permission to access address region0
* and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_mm_region_pms:2;
/** reg_hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
* NA
uint32_t hp_core0_mm_region_pms:2;
/** hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
* Configures whether HP CPU1 in user mode has permission to access address region0
* and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_um_region_pms:2;
/** reg_hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
* NA
uint32_t hp_core1_um_region_pms:2;
/** hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
* Configures whether HP CPU1 in machine mode has permission to access address region0
* and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_mm_region_pms:2;
uint32_t hp_core1_mm_region_pms:2;
uint32_t reserved_10:22;
};
uint32_t val;
} tee_peri_region_pms_reg_t;
} pms_peri_region_pms_reg_t;
typedef struct {
volatile tee_pms_date_reg_t pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
volatile tee_peri_region0_low_reg_t peri_region0_low;
volatile tee_peri_region0_high_reg_t peri_region0_high;
volatile tee_peri_region1_low_reg_t peri_region1_low;
volatile tee_peri_region1_high_reg_t peri_region1_high;
volatile tee_peri_region_pms_reg_t peri_region_pms;
} tee_dev_t;
volatile pms_lp_peri_pms_date_reg_t lp_peri_pms_date;
volatile pms_lp_peri_pms_clk_en_reg_t lp_peri_pms_clk_en;
volatile pms_lp_mm_lp_peri_pms_reg0_reg_t lp_mm_lp_peri_pms_reg0;
volatile pms_peri_regionn_low_reg_t peri_region0_low;
volatile pms_peri_regionn_high_reg_t peri_region0_high;
volatile pms_peri_regionn_low_reg_t peri_region1_low;
volatile pms_peri_regionn_high_reg_t peri_region1_high;
volatile pms_peri_region_pms_reg_t peri_region_pms;
} lp_peri_pms_dev_t;
extern lp_peri_pms_dev_t LP_PERI_PMS;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x20, "Invalid size of tee_dev_t structure");
_Static_assert(sizeof(lp_peri_pms_dev_t) == 0x20, "Invalid size of lp_peri_pms_dev_t structure");
#endif
#ifdef __cplusplus

5
components/soc/esp32p4/ld/esp32p4.peripherals.ld
View File

@ -19,6 +19,9 @@ PROVIDE ( I2C1 = 0x500C5000 );
PROVIDE ( UHCI0 = 0x500DF000 );
PROVIDE ( RMT = 0x500A2000 );
PROVIDE ( RMTMEM = 0x500A2800 );
PROVIDE ( HP_PERI_PMS = 0x500A5000 );
PROVIDE ( LP2HP_PERI_PMS = 0x500A5800 );
PROVIDE ( DMA_PMS = 0x500A6000 );
PROVIDE ( LEDC = 0x500D3000 );
PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 );
PROVIDE ( TIMERG0 = 0x500C2000 );
@ -79,6 +82,8 @@ PROVIDE ( LP_WDT = 0x50116000 );
PROVIDE ( LP_I2S = 0x50125000 );
PROVIDE ( LP_TOUCH = 0x50128000 );
PROVIDE ( LP_GPIO = 0x5012A000 );
PROVIDE ( LP_PERI_PMS = 0x5012E000 );
PROVIDE ( HP2LP_PERI_PMS = 0x5012E800 );
PROVIDE ( LP_I2C_ANA_MST = 0x50124000 );
PROVIDE ( LP_ANA_PERI = 0x50113000 );
PROVIDE ( LP_APM = 0x600B3800 ); /* TODO: IDF-7542 */