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3c358dd074
Do not enable co-processor trap wakeup source when running ULP FSM, as this could cause spurious wake-ups.
49 lines
1.5 KiB
Python
49 lines
1.5 KiB
Python
from __future__ import unicode_literals
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import re
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import time
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import tiny_test_fw
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import ttfw_idf
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from tiny_test_fw import DUT
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@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2', 'esp32s3'])
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def test_examples_ulp_riscv(env, extra_data): # type: (tiny_test_fw.Env.Env, None) -> None # pylint: disable=unused-argument
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dut = env.get_dut('ulp_riscv', 'examples/system/ulp_riscv/gpio')
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dut.start_app()
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dut.expect_all('Not a ULP-RISC-V wakeup, initializing it!',
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'Entering in deep sleep',
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timeout=30)
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# Give the chip time to enter deepsleep
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time.sleep(1)
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# Run two times to make sure device sleep
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# and wake up properly
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for i in range(0, 2):
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# Set GPIO0 using DTR
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dut.port_inst.setDTR(i % 2 == 0)
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dut.expect('ULP-RISC-V woke up the main CPU!', timeout=5)
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# Check GPIO state
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state = 'Low' if i % 2 == 0 else 'High'
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dut.expect(re.compile(r'ULP-RISC-V read changes in GPIO_0 current is: %s' % state), timeout=5)
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# Go back to sleep
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dut.expect('Entering in deep sleep', timeout=5)
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try:
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# We expect a timeout here, otherwise it means that
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# the main CPU woke up unexpectedly!
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dut.expect('ULP-RISC-V woke up the main CPU!', timeout=20)
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raise Exception('Main CPU woke up unexpectedly!')
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except DUT.ExpectTimeout:
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pass
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if __name__ == '__main__':
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test_examples_ulp_riscv()
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